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8d725fac AF |
1 | /* |
2 | * QEMU float support | |
3 | * | |
16017c48 PM |
4 | * The code in this source file is derived from release 2a of the SoftFloat |
5 | * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and | |
6 | * some later contributions) are provided under that license, as detailed below. | |
7 | * It has subsequently been modified by contributors to the QEMU Project, | |
8 | * so some portions are provided under: | |
9 | * the SoftFloat-2a license | |
10 | * the BSD license | |
11 | * GPL-v2-or-later | |
12 | * | |
13 | * Any future contributions to this file after December 1st 2014 will be | |
14 | * taken to be licensed under the Softfloat-2a license unless specifically | |
15 | * indicated otherwise. | |
8d725fac | 16 | */ |
158142c2 | 17 | |
a7d1ac78 PM |
18 | /* |
19 | =============================================================================== | |
158142c2 | 20 | This C source fragment is part of the SoftFloat IEC/IEEE Floating-point |
a7d1ac78 | 21 | Arithmetic Package, Release 2a. |
158142c2 FB |
22 | |
23 | Written by John R. Hauser. This work was made possible in part by the | |
24 | International Computer Science Institute, located at Suite 600, 1947 Center | |
25 | Street, Berkeley, California 94704. Funding was partially provided by the | |
26 | National Science Foundation under grant MIP-9311980. The original version | |
27 | of this code was written as part of a project to build a fixed-point vector | |
28 | processor in collaboration with the University of California at Berkeley, | |
29 | overseen by Profs. Nelson Morgan and John Wawrzynek. More information | |
a7d1ac78 | 30 | is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ |
158142c2 FB |
31 | arithmetic/SoftFloat.html'. |
32 | ||
a7d1ac78 PM |
33 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort |
34 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT | |
35 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO | |
36 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY | |
37 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. | |
158142c2 FB |
38 | |
39 | Derivative works are acceptable, even for commercial purposes, so long as | |
a7d1ac78 PM |
40 | (1) they include prominent notice that the work is derivative, and (2) they |
41 | include prominent notice akin to these four paragraphs for those parts of | |
42 | this code that are retained. | |
158142c2 | 43 | |
a7d1ac78 PM |
44 | =============================================================================== |
45 | */ | |
158142c2 | 46 | |
16017c48 PM |
47 | /* BSD licensing: |
48 | * Copyright (c) 2006, Fabrice Bellard | |
49 | * All rights reserved. | |
50 | * | |
51 | * Redistribution and use in source and binary forms, with or without | |
52 | * modification, are permitted provided that the following conditions are met: | |
53 | * | |
54 | * 1. Redistributions of source code must retain the above copyright notice, | |
55 | * this list of conditions and the following disclaimer. | |
56 | * | |
57 | * 2. Redistributions in binary form must reproduce the above copyright notice, | |
58 | * this list of conditions and the following disclaimer in the documentation | |
59 | * and/or other materials provided with the distribution. | |
60 | * | |
61 | * 3. Neither the name of the copyright holder nor the names of its contributors | |
62 | * may be used to endorse or promote products derived from this software without | |
63 | * specific prior written permission. | |
64 | * | |
65 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
66 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
67 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
68 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | |
69 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
70 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
71 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
72 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
73 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
74 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
75 | * THE POSSIBILITY OF SUCH DAMAGE. | |
76 | */ | |
77 | ||
78 | /* Portions of this work are licensed under the terms of the GNU GPL, | |
79 | * version 2 or later. See the COPYING file in the top-level directory. | |
80 | */ | |
81 | ||
cc43c692 MF |
82 | /* |
83 | * Define whether architecture deviates from IEEE in not supporting | |
213ff4e6 MF |
84 | * signaling NaNs (so all NaNs are treated as quiet). |
85 | */ | |
cc43c692 MF |
86 | static inline bool no_signaling_nans(float_status *status) |
87 | { | |
03385dfd | 88 | #if defined(TARGET_XTENSA) |
cc43c692 MF |
89 | return status->no_signaling_nans; |
90 | #else | |
91 | return false; | |
213ff4e6 | 92 | #endif |
cc43c692 | 93 | } |
213ff4e6 | 94 | |
03385dfd RH |
95 | /* Define how the architecture discriminates signaling NaNs. |
96 | * This done with the most significant bit of the fraction. | |
97 | * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 | |
98 | * the msb must be zero. MIPS is (so far) unique in supporting both the | |
99 | * 2008 revision and backward compatibility with their original choice. | |
100 | * Thus for MIPS we must make the choice at runtime. | |
101 | */ | |
c120391c | 102 | static inline bool snan_bit_is_one(float_status *status) |
03385dfd RH |
103 | { |
104 | #if defined(TARGET_MIPS) | |
105 | return status->snan_bit_is_one; | |
43692239 | 106 | #elif defined(TARGET_HPPA) || defined(TARGET_SH4) |
03385dfd RH |
107 | return 1; |
108 | #else | |
109 | return 0; | |
110 | #endif | |
111 | } | |
112 | ||
298b468e RH |
113 | /*---------------------------------------------------------------------------- |
114 | | For the deconstructed floating-point with fraction FRAC, return true | |
115 | | if the fraction represents a signalling NaN; otherwise false. | |
116 | *----------------------------------------------------------------------------*/ | |
117 | ||
118 | static bool parts_is_snan_frac(uint64_t frac, float_status *status) | |
119 | { | |
cc43c692 MF |
120 | if (no_signaling_nans(status)) { |
121 | return false; | |
122 | } else { | |
123 | bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); | |
124 | return msb == snan_bit_is_one(status); | |
125 | } | |
298b468e RH |
126 | } |
127 | ||
f7e598e2 RH |
128 | /*---------------------------------------------------------------------------- |
129 | | The pattern for a default generated deconstructed floating-point NaN. | |
130 | *----------------------------------------------------------------------------*/ | |
131 | ||
0fc07cad | 132 | static void parts64_default_nan(FloatParts64 *p, float_status *status) |
f7e598e2 RH |
133 | { |
134 | bool sign = 0; | |
135 | uint64_t frac; | |
136 | ||
137 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | |
8fb3d902 | 138 | /* !snan_bit_is_one, set all bits */ |
f7e598e2 | 139 | frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; |
8fb3d902 RH |
140 | #elif defined(TARGET_I386) || defined(TARGET_X86_64) \ |
141 | || defined(TARGET_MICROBLAZE) | |
142 | /* !snan_bit_is_one, set sign and msb */ | |
f7e598e2 | 143 | frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); |
8fb3d902 | 144 | sign = 1; |
f7e598e2 | 145 | #elif defined(TARGET_HPPA) |
8fb3d902 | 146 | /* snan_bit_is_one, set msb-1. */ |
f7e598e2 | 147 | frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); |
c0336c87 TS |
148 | #elif defined(TARGET_HEXAGON) |
149 | sign = 1; | |
150 | frac = ~0ULL; | |
f7e598e2 | 151 | #else |
43692239 MA |
152 | /* |
153 | * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | |
154 | * S390, SH4, TriCore, and Xtensa. Our other supported targets, | |
155 | * CRIS, Nios2, and Tile, do not have floating-point. | |
8fb3d902 | 156 | */ |
03385dfd | 157 | if (snan_bit_is_one(status)) { |
8fb3d902 | 158 | /* set all bits other than msb */ |
f7e598e2 RH |
159 | frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; |
160 | } else { | |
8fb3d902 | 161 | /* set msb */ |
f7e598e2 | 162 | frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); |
f7e598e2 RH |
163 | } |
164 | #endif | |
165 | ||
0fc07cad | 166 | *p = (FloatParts64) { |
f7e598e2 RH |
167 | .cls = float_class_qnan, |
168 | .sign = sign, | |
169 | .exp = INT_MAX, | |
170 | .frac = frac | |
171 | }; | |
172 | } | |
173 | ||
e9034ea8 RH |
174 | static void parts128_default_nan(FloatParts128 *p, float_status *status) |
175 | { | |
176 | /* | |
177 | * Extrapolate from the choices made by parts64_default_nan to fill | |
178 | * in the quad-floating format. If the low bit is set, assume we | |
179 | * want to set all non-snan bits. | |
180 | */ | |
181 | FloatParts64 p64; | |
182 | parts64_default_nan(&p64, status); | |
183 | ||
184 | *p = (FloatParts128) { | |
185 | .cls = float_class_qnan, | |
186 | .sign = p64.sign, | |
187 | .exp = INT_MAX, | |
188 | .frac_hi = p64.frac, | |
189 | .frac_lo = -(p64.frac & 1) | |
190 | }; | |
191 | } | |
192 | ||
0bcfbcbe RH |
193 | /*---------------------------------------------------------------------------- |
194 | | Returns a quiet NaN from a signalling NaN for the deconstructed | |
195 | | floating-point parts. | |
196 | *----------------------------------------------------------------------------*/ | |
197 | ||
92ff426d | 198 | static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) |
0bcfbcbe | 199 | { |
cc43c692 | 200 | g_assert(!no_signaling_nans(status)); |
a777d603 RH |
201 | |
202 | /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ | |
03385dfd | 203 | if (snan_bit_is_one(status)) { |
92ff426d RH |
204 | frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); |
205 | frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); | |
0bcfbcbe | 206 | } else { |
92ff426d | 207 | frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); |
0bcfbcbe | 208 | } |
92ff426d RH |
209 | return frac; |
210 | } | |
211 | ||
212 | static void parts64_silence_nan(FloatParts64 *p, float_status *status) | |
213 | { | |
214 | p->frac = parts_silence_nan_frac(p->frac, status); | |
215 | p->cls = float_class_qnan; | |
0bcfbcbe RH |
216 | } |
217 | ||
0018b1f4 RH |
218 | static void parts128_silence_nan(FloatParts128 *p, float_status *status) |
219 | { | |
220 | p->frac_hi = parts_silence_nan_frac(p->frac_hi, status); | |
221 | p->cls = float_class_qnan; | |
222 | } | |
223 | ||
789ec7ce PB |
224 | /*---------------------------------------------------------------------------- |
225 | | The pattern for a default generated extended double-precision NaN. | |
226 | *----------------------------------------------------------------------------*/ | |
af39bc8c AM |
227 | floatx80 floatx80_default_nan(float_status *status) |
228 | { | |
229 | floatx80 r; | |
0218a16e RH |
230 | |
231 | /* None of the targets that have snan_bit_is_one use floatx80. */ | |
232 | assert(!snan_bit_is_one(status)); | |
e5b0cbe8 | 233 | #if defined(TARGET_M68K) |
f7e81a94 | 234 | r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); |
e5b0cbe8 LV |
235 | r.high = 0x7FFF; |
236 | #else | |
0218a16e | 237 | /* X86 */ |
f7e81a94 | 238 | r.low = UINT64_C(0xC000000000000000); |
0218a16e | 239 | r.high = 0xFFFF; |
e5b0cbe8 | 240 | #endif |
af39bc8c AM |
241 | return r; |
242 | } | |
789ec7ce | 243 | |
0f605c88 LV |
244 | /*---------------------------------------------------------------------------- |
245 | | The pattern for a default generated extended double-precision inf. | |
246 | *----------------------------------------------------------------------------*/ | |
247 | ||
248 | #define floatx80_infinity_high 0x7FFF | |
249 | #if defined(TARGET_M68K) | |
f7e81a94 | 250 | #define floatx80_infinity_low UINT64_C(0x0000000000000000) |
0f605c88 | 251 | #else |
f7e81a94 | 252 | #define floatx80_infinity_low UINT64_C(0x8000000000000000) |
0f605c88 LV |
253 | #endif |
254 | ||
255 | const floatx80 floatx80_infinity | |
256 | = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); | |
257 | ||
bb4d4bb3 PM |
258 | /*---------------------------------------------------------------------------- |
259 | | Returns 1 if the half-precision floating-point value `a' is a quiet | |
260 | | NaN; otherwise returns 0. | |
261 | *----------------------------------------------------------------------------*/ | |
262 | ||
150c7a91 | 263 | bool float16_is_quiet_nan(float16 a_, float_status *status) |
bb4d4bb3 | 264 | { |
cc43c692 MF |
265 | if (no_signaling_nans(status)) { |
266 | return float16_is_any_nan(a_); | |
af39bc8c | 267 | } else { |
cc43c692 MF |
268 | uint16_t a = float16_val(a_); |
269 | if (snan_bit_is_one(status)) { | |
270 | return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); | |
271 | } else { | |
272 | ||
273 | return ((a >> 9) & 0x3F) == 0x3F; | |
274 | } | |
af39bc8c | 275 | } |
bb4d4bb3 PM |
276 | } |
277 | ||
5ebf5f4b LZ |
278 | /*---------------------------------------------------------------------------- |
279 | | Returns 1 if the bfloat16 value `a' is a quiet | |
280 | | NaN; otherwise returns 0. | |
281 | *----------------------------------------------------------------------------*/ | |
282 | ||
283 | bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) | |
284 | { | |
285 | if (no_signaling_nans(status)) { | |
286 | return bfloat16_is_any_nan(a_); | |
287 | } else { | |
288 | uint16_t a = a_; | |
289 | if (snan_bit_is_one(status)) { | |
290 | return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); | |
291 | } else { | |
292 | return ((a >> 6) & 0x1FF) == 0x1FF; | |
293 | } | |
294 | } | |
295 | } | |
296 | ||
bb4d4bb3 PM |
297 | /*---------------------------------------------------------------------------- |
298 | | Returns 1 if the half-precision floating-point value `a' is a signaling | |
299 | | NaN; otherwise returns 0. | |
300 | *----------------------------------------------------------------------------*/ | |
301 | ||
150c7a91 | 302 | bool float16_is_signaling_nan(float16 a_, float_status *status) |
bb4d4bb3 | 303 | { |
cc43c692 MF |
304 | if (no_signaling_nans(status)) { |
305 | return 0; | |
af39bc8c | 306 | } else { |
cc43c692 MF |
307 | uint16_t a = float16_val(a_); |
308 | if (snan_bit_is_one(status)) { | |
309 | return ((a >> 9) & 0x3F) == 0x3F; | |
310 | } else { | |
311 | return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); | |
312 | } | |
af39bc8c | 313 | } |
bca52234 | 314 | } |
bb4d4bb3 | 315 | |
5ebf5f4b LZ |
316 | /*---------------------------------------------------------------------------- |
317 | | Returns 1 if the bfloat16 value `a' is a signaling | |
318 | | NaN; otherwise returns 0. | |
319 | *----------------------------------------------------------------------------*/ | |
320 | ||
321 | bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) | |
322 | { | |
323 | if (no_signaling_nans(status)) { | |
324 | return 0; | |
325 | } else { | |
326 | uint16_t a = a_; | |
327 | if (snan_bit_is_one(status)) { | |
328 | return ((a >> 6) & 0x1FF) == 0x1FF; | |
329 | } else { | |
330 | return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); | |
331 | } | |
332 | } | |
333 | } | |
334 | ||
158142c2 | 335 | /*---------------------------------------------------------------------------- |
5a6932d5 TS |
336 | | Returns 1 if the single-precision floating-point value `a' is a quiet |
337 | | NaN; otherwise returns 0. | |
158142c2 FB |
338 | *----------------------------------------------------------------------------*/ |
339 | ||
150c7a91 | 340 | bool float32_is_quiet_nan(float32 a_, float_status *status) |
158142c2 | 341 | { |
cc43c692 MF |
342 | if (no_signaling_nans(status)) { |
343 | return float32_is_any_nan(a_); | |
af39bc8c | 344 | } else { |
cc43c692 MF |
345 | uint32_t a = float32_val(a_); |
346 | if (snan_bit_is_one(status)) { | |
347 | return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); | |
348 | } else { | |
349 | return ((uint32_t)(a << 1) >= 0xFF800000); | |
350 | } | |
af39bc8c | 351 | } |
158142c2 FB |
352 | } |
353 | ||
354 | /*---------------------------------------------------------------------------- | |
355 | | Returns 1 if the single-precision floating-point value `a' is a signaling | |
356 | | NaN; otherwise returns 0. | |
357 | *----------------------------------------------------------------------------*/ | |
358 | ||
150c7a91 | 359 | bool float32_is_signaling_nan(float32 a_, float_status *status) |
158142c2 | 360 | { |
cc43c692 MF |
361 | if (no_signaling_nans(status)) { |
362 | return 0; | |
af39bc8c | 363 | } else { |
cc43c692 MF |
364 | uint32_t a = float32_val(a_); |
365 | if (snan_bit_is_one(status)) { | |
366 | return ((uint32_t)(a << 1) >= 0xFF800000); | |
367 | } else { | |
368 | return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); | |
369 | } | |
af39bc8c | 370 | } |
bca52234 | 371 | } |
158142c2 | 372 | |
354f211b PM |
373 | /*---------------------------------------------------------------------------- |
374 | | Select which NaN to propagate for a two-input operation. | |
375 | | IEEE754 doesn't specify all the details of this, so the | |
376 | | algorithm is target-specific. | |
377 | | The routine is passed various bits of information about the | |
378 | | two NaNs and should return 0 to select NaN a and 1 for NaN b. | |
379 | | Note that signalling NaNs are always squashed to quiet NaNs | |
4885312f | 380 | | by the caller, by calling floatXX_silence_nan() before |
1f398e08 | 381 | | returning them. |
354f211b PM |
382 | | |
383 | | aIsLargerSignificand is only valid if both a and b are NaNs | |
384 | | of some kind, and is true if a has the larger significand, | |
385 | | or if both a and b have the same significand but a is | |
386 | | positive but b is negative. It is only needed for the x87 | |
387 | | tie-break rule. | |
388 | *----------------------------------------------------------------------------*/ | |
389 | ||
4f251cfd | 390 | static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
913602e3 | 391 | bool aIsLargerSignificand, float_status *status) |
011da610 | 392 | { |
4f251cfd | 393 | #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) |
13894527 AB |
394 | /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take |
395 | * the first of: | |
011da610 PM |
396 | * 1. A if it is signaling |
397 | * 2. B if it is signaling | |
398 | * 3. A (quiet) | |
399 | * 4. B (quiet) | |
400 | * A signaling NaN is always quietened before returning it. | |
401 | */ | |
084d19ba AJ |
402 | /* According to MIPS specifications, if one of the two operands is |
403 | * a sNaN, a new qNaN has to be generated. This is done in | |
4885312f | 404 | * floatXX_silence_nan(). For qNaN inputs the specifications |
084d19ba AJ |
405 | * says: "When possible, this QNaN result is one of the operand QNaN |
406 | * values." In practice it seems that most implementations choose | |
407 | * the first operand if both operands are qNaN. In short this gives | |
408 | * the following rules: | |
409 | * 1. A if it is signaling | |
410 | * 2. B if it is signaling | |
411 | * 3. A (quiet) | |
412 | * 4. B (quiet) | |
413 | * A signaling NaN is always silenced before returning it. | |
414 | */ | |
4f251cfd | 415 | if (is_snan(a_cls)) { |
084d19ba | 416 | return 0; |
4f251cfd | 417 | } else if (is_snan(b_cls)) { |
084d19ba | 418 | return 1; |
4f251cfd | 419 | } else if (is_qnan(a_cls)) { |
084d19ba AJ |
420 | return 0; |
421 | } else { | |
422 | return 1; | |
423 | } | |
913602e3 | 424 | #elif defined(TARGET_PPC) || defined(TARGET_M68K) |
e024e881 AJ |
425 | /* PowerPC propagation rules: |
426 | * 1. A if it sNaN or qNaN | |
427 | * 2. B if it sNaN or qNaN | |
428 | * A signaling NaN is always silenced before returning it. | |
429 | */ | |
e5b0cbe8 LV |
430 | /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL |
431 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS | |
432 | * If either operand, but not both operands, of an operation is a | |
433 | * nonsignaling NaN, then that NaN is returned as the result. If both | |
434 | * operands are nonsignaling NaNs, then the destination operand | |
435 | * nonsignaling NaN is returned as the result. | |
436 | * If either operand to an operation is a signaling NaN (SNaN), then the | |
437 | * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit | |
438 | * is set in the FPCR ENABLE byte, then the exception is taken and the | |
439 | * destination is not modified. If the SNaN exception enable bit is not | |
440 | * set, setting the SNaN bit in the operand to a one converts the SNaN to | |
441 | * a nonsignaling NaN. The operation then continues as described in the | |
442 | * preceding paragraph for nonsignaling NaNs. | |
443 | */ | |
4f251cfd RH |
444 | if (is_nan(a_cls)) { |
445 | return 0; | |
e5b0cbe8 | 446 | } else { |
4f251cfd | 447 | return 1; |
e5b0cbe8 | 448 | } |
913602e3 MF |
449 | #elif defined(TARGET_XTENSA) |
450 | /* | |
451 | * Xtensa has two NaN propagation modes. | |
452 | * Which one is active is controlled by float_status::use_first_nan. | |
453 | */ | |
454 | if (status->use_first_nan) { | |
455 | if (is_nan(a_cls)) { | |
456 | return 0; | |
457 | } else { | |
458 | return 1; | |
459 | } | |
460 | } else { | |
461 | if (is_nan(b_cls)) { | |
462 | return 1; | |
463 | } else { | |
464 | return 0; | |
465 | } | |
466 | } | |
011da610 | 467 | #else |
354f211b PM |
468 | /* This implements x87 NaN propagation rules: |
469 | * SNaN + QNaN => return the QNaN | |
470 | * two SNaNs => return the one with the larger significand, silenced | |
471 | * two QNaNs => return the one with the larger significand | |
472 | * SNaN and a non-NaN => return the SNaN, silenced | |
473 | * QNaN and a non-NaN => return the QNaN | |
474 | * | |
475 | * If we get down to comparing significands and they are the same, | |
476 | * return the NaN with the positive sign bit (if any). | |
477 | */ | |
4f251cfd RH |
478 | if (is_snan(a_cls)) { |
479 | if (is_snan(b_cls)) { | |
354f211b PM |
480 | return aIsLargerSignificand ? 0 : 1; |
481 | } | |
4f251cfd RH |
482 | return is_qnan(b_cls) ? 1 : 0; |
483 | } else if (is_qnan(a_cls)) { | |
484 | if (is_snan(b_cls) || !is_qnan(b_cls)) { | |
354f211b | 485 | return 0; |
a59eaea6 | 486 | } else { |
354f211b PM |
487 | return aIsLargerSignificand ? 0 : 1; |
488 | } | |
489 | } else { | |
490 | return 1; | |
491 | } | |
011da610 | 492 | #endif |
4f251cfd | 493 | } |
354f211b | 494 | |
369be8f6 PM |
495 | /*---------------------------------------------------------------------------- |
496 | | Select which NaN to propagate for a three-input operation. | |
497 | | For the moment we assume that no CPU needs the 'larger significand' | |
498 | | information. | |
499 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | |
500 | *----------------------------------------------------------------------------*/ | |
3bd2dec1 RH |
501 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
502 | bool infzero, float_status *status) | |
369be8f6 | 503 | { |
3bd2dec1 | 504 | #if defined(TARGET_ARM) |
369be8f6 PM |
505 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns |
506 | * the default NaN | |
507 | */ | |
3bd2dec1 | 508 | if (infzero && is_qnan(c_cls)) { |
bead3c9b | 509 | float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
369be8f6 PM |
510 | return 3; |
511 | } | |
512 | ||
513 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | |
514 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | |
515 | */ | |
3bd2dec1 | 516 | if (is_snan(c_cls)) { |
369be8f6 | 517 | return 2; |
3bd2dec1 | 518 | } else if (is_snan(a_cls)) { |
369be8f6 | 519 | return 0; |
3bd2dec1 | 520 | } else if (is_snan(b_cls)) { |
369be8f6 | 521 | return 1; |
3bd2dec1 | 522 | } else if (is_qnan(c_cls)) { |
369be8f6 | 523 | return 2; |
3bd2dec1 | 524 | } else if (is_qnan(a_cls)) { |
369be8f6 PM |
525 | return 0; |
526 | } else { | |
527 | return 1; | |
528 | } | |
bbc1dede | 529 | #elif defined(TARGET_MIPS) |
03385dfd | 530 | if (snan_bit_is_one(status)) { |
7ca96e1a MM |
531 | /* |
532 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | |
533 | * case sets InvalidOp and returns the default NaN | |
534 | */ | |
535 | if (infzero) { | |
bead3c9b | 536 | float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
7ca96e1a MM |
537 | return 3; |
538 | } | |
c27644f0 | 539 | /* Prefer sNaN over qNaN, in the a, b, c order. */ |
3bd2dec1 | 540 | if (is_snan(a_cls)) { |
c27644f0 | 541 | return 0; |
3bd2dec1 | 542 | } else if (is_snan(b_cls)) { |
c27644f0 | 543 | return 1; |
3bd2dec1 | 544 | } else if (is_snan(c_cls)) { |
c27644f0 | 545 | return 2; |
3bd2dec1 | 546 | } else if (is_qnan(a_cls)) { |
c27644f0 | 547 | return 0; |
3bd2dec1 | 548 | } else if (is_qnan(b_cls)) { |
c27644f0 AM |
549 | return 1; |
550 | } else { | |
551 | return 2; | |
552 | } | |
bbc1dede | 553 | } else { |
7ca96e1a MM |
554 | /* |
555 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | |
556 | * case sets InvalidOp and returns the input value 'c' | |
557 | */ | |
558 | if (infzero) { | |
bead3c9b | 559 | float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
7ca96e1a MM |
560 | return 2; |
561 | } | |
c27644f0 | 562 | /* Prefer sNaN over qNaN, in the c, a, b order. */ |
3bd2dec1 | 563 | if (is_snan(c_cls)) { |
c27644f0 | 564 | return 2; |
3bd2dec1 | 565 | } else if (is_snan(a_cls)) { |
c27644f0 | 566 | return 0; |
3bd2dec1 | 567 | } else if (is_snan(b_cls)) { |
c27644f0 | 568 | return 1; |
3bd2dec1 | 569 | } else if (is_qnan(c_cls)) { |
c27644f0 | 570 | return 2; |
3bd2dec1 | 571 | } else if (is_qnan(a_cls)) { |
c27644f0 AM |
572 | return 0; |
573 | } else { | |
574 | return 1; | |
575 | } | |
bbc1dede | 576 | } |
369be8f6 | 577 | #elif defined(TARGET_PPC) |
369be8f6 PM |
578 | /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer |
579 | * to return an input NaN if we have one (ie c) rather than generating | |
580 | * a default NaN | |
581 | */ | |
582 | if (infzero) { | |
bead3c9b | 583 | float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
369be8f6 PM |
584 | return 2; |
585 | } | |
586 | ||
587 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | |
588 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | |
589 | */ | |
3bd2dec1 | 590 | if (is_nan(a_cls)) { |
369be8f6 | 591 | return 0; |
3bd2dec1 | 592 | } else if (is_nan(c_cls)) { |
369be8f6 PM |
593 | return 2; |
594 | } else { | |
595 | return 1; | |
596 | } | |
3a7f7757 FC |
597 | #elif defined(TARGET_RISCV) |
598 | /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ | |
599 | if (infzero) { | |
bead3c9b | 600 | float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
3a7f7757 FC |
601 | } |
602 | return 3; /* default NaN */ | |
fbcc38e4 MF |
603 | #elif defined(TARGET_XTENSA) |
604 | /* | |
605 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | |
606 | * an input NaN if we have one (ie c). | |
607 | */ | |
608 | if (infzero) { | |
bead3c9b | 609 | float_raise(float_flag_invalid | float_flag_invalid_imz, status); |
fbcc38e4 MF |
610 | return 2; |
611 | } | |
612 | if (status->use_first_nan) { | |
613 | if (is_nan(a_cls)) { | |
614 | return 0; | |
615 | } else if (is_nan(b_cls)) { | |
616 | return 1; | |
617 | } else { | |
618 | return 2; | |
619 | } | |
620 | } else { | |
621 | if (is_nan(c_cls)) { | |
622 | return 2; | |
623 | } else if (is_nan(b_cls)) { | |
624 | return 1; | |
625 | } else { | |
626 | return 0; | |
627 | } | |
628 | } | |
369be8f6 | 629 | #else |
3bd2dec1 RH |
630 | /* A default implementation: prefer a to b to c. |
631 | * This is unlikely to actually match any real implementation. | |
632 | */ | |
633 | if (is_nan(a_cls)) { | |
369be8f6 | 634 | return 0; |
3bd2dec1 | 635 | } else if (is_nan(b_cls)) { |
369be8f6 PM |
636 | return 1; |
637 | } else { | |
638 | return 2; | |
639 | } | |
369be8f6 | 640 | #endif |
3bd2dec1 | 641 | } |
369be8f6 | 642 | |
158142c2 | 643 | /*---------------------------------------------------------------------------- |
5a6932d5 TS |
644 | | Returns 1 if the double-precision floating-point value `a' is a quiet |
645 | | NaN; otherwise returns 0. | |
158142c2 FB |
646 | *----------------------------------------------------------------------------*/ |
647 | ||
150c7a91 | 648 | bool float64_is_quiet_nan(float64 a_, float_status *status) |
158142c2 | 649 | { |
cc43c692 MF |
650 | if (no_signaling_nans(status)) { |
651 | return float64_is_any_nan(a_); | |
af39bc8c | 652 | } else { |
cc43c692 MF |
653 | uint64_t a = float64_val(a_); |
654 | if (snan_bit_is_one(status)) { | |
655 | return (((a >> 51) & 0xFFF) == 0xFFE) | |
656 | && (a & 0x0007FFFFFFFFFFFFULL); | |
657 | } else { | |
658 | return ((a << 1) >= 0xFFF0000000000000ULL); | |
659 | } | |
af39bc8c | 660 | } |
158142c2 FB |
661 | } |
662 | ||
663 | /*---------------------------------------------------------------------------- | |
664 | | Returns 1 if the double-precision floating-point value `a' is a signaling | |
665 | | NaN; otherwise returns 0. | |
666 | *----------------------------------------------------------------------------*/ | |
667 | ||
150c7a91 | 668 | bool float64_is_signaling_nan(float64 a_, float_status *status) |
158142c2 | 669 | { |
cc43c692 MF |
670 | if (no_signaling_nans(status)) { |
671 | return 0; | |
af39bc8c | 672 | } else { |
cc43c692 MF |
673 | uint64_t a = float64_val(a_); |
674 | if (snan_bit_is_one(status)) { | |
675 | return ((a << 1) >= 0xFFF0000000000000ULL); | |
676 | } else { | |
677 | return (((a >> 51) & 0xFFF) == 0xFFE) | |
678 | && (a & UINT64_C(0x0007FFFFFFFFFFFF)); | |
679 | } | |
af39bc8c | 680 | } |
bca52234 | 681 | } |
158142c2 | 682 | |
158142c2 FB |
683 | /*---------------------------------------------------------------------------- |
684 | | Returns 1 if the extended double-precision floating-point value `a' is a | |
de4af5f7 AJ |
685 | | quiet NaN; otherwise returns 0. This slightly differs from the same |
686 | | function for other types as floatx80 has an explicit bit. | |
158142c2 FB |
687 | *----------------------------------------------------------------------------*/ |
688 | ||
af39bc8c | 689 | int floatx80_is_quiet_nan(floatx80 a, float_status *status) |
158142c2 | 690 | { |
cc43c692 MF |
691 | if (no_signaling_nans(status)) { |
692 | return floatx80_is_any_nan(a); | |
af39bc8c | 693 | } else { |
cc43c692 MF |
694 | if (snan_bit_is_one(status)) { |
695 | uint64_t aLow; | |
696 | ||
697 | aLow = a.low & ~0x4000000000000000ULL; | |
698 | return ((a.high & 0x7FFF) == 0x7FFF) | |
699 | && (aLow << 1) | |
700 | && (a.low == aLow); | |
701 | } else { | |
702 | return ((a.high & 0x7FFF) == 0x7FFF) | |
703 | && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); | |
704 | } | |
af39bc8c | 705 | } |
158142c2 FB |
706 | } |
707 | ||
708 | /*---------------------------------------------------------------------------- | |
709 | | Returns 1 if the extended double-precision floating-point value `a' is a | |
de4af5f7 AJ |
710 | | signaling NaN; otherwise returns 0. This slightly differs from the same |
711 | | function for other types as floatx80 has an explicit bit. | |
158142c2 FB |
712 | *----------------------------------------------------------------------------*/ |
713 | ||
af39bc8c | 714 | int floatx80_is_signaling_nan(floatx80 a, float_status *status) |
158142c2 | 715 | { |
cc43c692 MF |
716 | if (no_signaling_nans(status)) { |
717 | return 0; | |
af39bc8c | 718 | } else { |
cc43c692 MF |
719 | if (snan_bit_is_one(status)) { |
720 | return ((a.high & 0x7FFF) == 0x7FFF) | |
721 | && ((a.low << 1) >= 0x8000000000000000ULL); | |
722 | } else { | |
723 | uint64_t aLow; | |
158142c2 | 724 | |
cc43c692 MF |
725 | aLow = a.low & ~UINT64_C(0x4000000000000000); |
726 | return ((a.high & 0x7FFF) == 0x7FFF) | |
727 | && (uint64_t)(aLow << 1) | |
728 | && (a.low == aLow); | |
729 | } | |
af39bc8c | 730 | } |
bca52234 | 731 | } |
158142c2 | 732 | |
d619bb98 RH |
733 | /*---------------------------------------------------------------------------- |
734 | | Returns a quiet NaN from a signalling NaN for the extended double-precision | |
735 | | floating point value `a'. | |
736 | *----------------------------------------------------------------------------*/ | |
737 | ||
738 | floatx80 floatx80_silence_nan(floatx80 a, float_status *status) | |
739 | { | |
377ed926 RH |
740 | /* None of the targets that have snan_bit_is_one use floatx80. */ |
741 | assert(!snan_bit_is_one(status)); | |
f7e81a94 | 742 | a.low |= UINT64_C(0xC000000000000000); |
377ed926 | 743 | return a; |
d619bb98 RH |
744 | } |
745 | ||
158142c2 FB |
746 | /*---------------------------------------------------------------------------- |
747 | | Takes two extended double-precision floating-point values `a' and `b', one | |
748 | | of which is a NaN, and returns the appropriate NaN result. If either `a' or | |
749 | | `b' is a signaling NaN, the invalid exception is raised. | |
750 | *----------------------------------------------------------------------------*/ | |
751 | ||
88857aca | 752 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
158142c2 | 753 | { |
c120391c | 754 | bool aIsLargerSignificand; |
4f251cfd RH |
755 | FloatClass a_cls, b_cls; |
756 | ||
757 | /* This is not complete, but is good enough for pickNaN. */ | |
758 | a_cls = (!floatx80_is_any_nan(a) | |
759 | ? float_class_normal | |
760 | : floatx80_is_signaling_nan(a, status) | |
761 | ? float_class_snan | |
762 | : float_class_qnan); | |
763 | b_cls = (!floatx80_is_any_nan(b) | |
764 | ? float_class_normal | |
765 | : floatx80_is_signaling_nan(b, status) | |
766 | ? float_class_snan | |
767 | : float_class_qnan); | |
768 | ||
769 | if (is_snan(a_cls) || is_snan(b_cls)) { | |
ff32e16e PM |
770 | float_raise(float_flag_invalid, status); |
771 | } | |
354f211b | 772 | |
a2f2d288 | 773 | if (status->default_nan_mode) { |
af39bc8c | 774 | return floatx80_default_nan(status); |
10201602 AJ |
775 | } |
776 | ||
354f211b PM |
777 | if (a.low < b.low) { |
778 | aIsLargerSignificand = 0; | |
779 | } else if (b.low < a.low) { | |
780 | aIsLargerSignificand = 1; | |
781 | } else { | |
782 | aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | |
158142c2 | 783 | } |
354f211b | 784 | |
913602e3 | 785 | if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
4f251cfd | 786 | if (is_snan(b_cls)) { |
4885312f RH |
787 | return floatx80_silence_nan(b, status); |
788 | } | |
789 | return b; | |
354f211b | 790 | } else { |
4f251cfd | 791 | if (is_snan(a_cls)) { |
4885312f RH |
792 | return floatx80_silence_nan(a, status); |
793 | } | |
794 | return a; | |
158142c2 | 795 | } |
158142c2 FB |
796 | } |
797 | ||
158142c2 | 798 | /*---------------------------------------------------------------------------- |
5a6932d5 TS |
799 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet |
800 | | NaN; otherwise returns 0. | |
158142c2 FB |
801 | *----------------------------------------------------------------------------*/ |
802 | ||
150c7a91 | 803 | bool float128_is_quiet_nan(float128 a, float_status *status) |
158142c2 | 804 | { |
cc43c692 MF |
805 | if (no_signaling_nans(status)) { |
806 | return float128_is_any_nan(a); | |
af39bc8c | 807 | } else { |
cc43c692 MF |
808 | if (snan_bit_is_one(status)) { |
809 | return (((a.high >> 47) & 0xFFFF) == 0xFFFE) | |
810 | && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); | |
811 | } else { | |
812 | return ((a.high << 1) >= 0xFFFF000000000000ULL) | |
813 | && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); | |
814 | } | |
af39bc8c | 815 | } |
158142c2 FB |
816 | } |
817 | ||
818 | /*---------------------------------------------------------------------------- | |
819 | | Returns 1 if the quadruple-precision floating-point value `a' is a | |
820 | | signaling NaN; otherwise returns 0. | |
821 | *----------------------------------------------------------------------------*/ | |
822 | ||
150c7a91 | 823 | bool float128_is_signaling_nan(float128 a, float_status *status) |
158142c2 | 824 | { |
cc43c692 MF |
825 | if (no_signaling_nans(status)) { |
826 | return 0; | |
af39bc8c | 827 | } else { |
cc43c692 MF |
828 | if (snan_bit_is_one(status)) { |
829 | return ((a.high << 1) >= 0xFFFF000000000000ULL) | |
830 | && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); | |
831 | } else { | |
832 | return (((a.high >> 47) & 0xFFFF) == 0xFFFE) | |
833 | && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); | |
834 | } | |
af39bc8c | 835 | } |
bca52234 | 836 | } |