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8d725fac AF |
1 | /* |
2 | * QEMU float support | |
3 | * | |
16017c48 PM |
4 | * The code in this source file is derived from release 2a of the SoftFloat |
5 | * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and | |
6 | * some later contributions) are provided under that license, as detailed below. | |
7 | * It has subsequently been modified by contributors to the QEMU Project, | |
8 | * so some portions are provided under: | |
9 | * the SoftFloat-2a license | |
10 | * the BSD license | |
11 | * GPL-v2-or-later | |
12 | * | |
13 | * Any future contributions to this file after December 1st 2014 will be | |
14 | * taken to be licensed under the Softfloat-2a license unless specifically | |
15 | * indicated otherwise. | |
8d725fac | 16 | */ |
158142c2 | 17 | |
a7d1ac78 PM |
18 | /* |
19 | =============================================================================== | |
158142c2 | 20 | This C source fragment is part of the SoftFloat IEC/IEEE Floating-point |
a7d1ac78 | 21 | Arithmetic Package, Release 2a. |
158142c2 FB |
22 | |
23 | Written by John R. Hauser. This work was made possible in part by the | |
24 | International Computer Science Institute, located at Suite 600, 1947 Center | |
25 | Street, Berkeley, California 94704. Funding was partially provided by the | |
26 | National Science Foundation under grant MIP-9311980. The original version | |
27 | of this code was written as part of a project to build a fixed-point vector | |
28 | processor in collaboration with the University of California at Berkeley, | |
29 | overseen by Profs. Nelson Morgan and John Wawrzynek. More information | |
a7d1ac78 | 30 | is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ |
158142c2 FB |
31 | arithmetic/SoftFloat.html'. |
32 | ||
a7d1ac78 PM |
33 | THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort |
34 | has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT | |
35 | TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO | |
36 | PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY | |
37 | AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. | |
158142c2 FB |
38 | |
39 | Derivative works are acceptable, even for commercial purposes, so long as | |
a7d1ac78 PM |
40 | (1) they include prominent notice that the work is derivative, and (2) they |
41 | include prominent notice akin to these four paragraphs for those parts of | |
42 | this code that are retained. | |
158142c2 | 43 | |
a7d1ac78 PM |
44 | =============================================================================== |
45 | */ | |
158142c2 | 46 | |
16017c48 PM |
47 | /* BSD licensing: |
48 | * Copyright (c) 2006, Fabrice Bellard | |
49 | * All rights reserved. | |
50 | * | |
51 | * Redistribution and use in source and binary forms, with or without | |
52 | * modification, are permitted provided that the following conditions are met: | |
53 | * | |
54 | * 1. Redistributions of source code must retain the above copyright notice, | |
55 | * this list of conditions and the following disclaimer. | |
56 | * | |
57 | * 2. Redistributions in binary form must reproduce the above copyright notice, | |
58 | * this list of conditions and the following disclaimer in the documentation | |
59 | * and/or other materials provided with the distribution. | |
60 | * | |
61 | * 3. Neither the name of the copyright holder nor the names of its contributors | |
62 | * may be used to endorse or promote products derived from this software without | |
63 | * specific prior written permission. | |
64 | * | |
65 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
66 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
67 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
68 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | |
69 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
70 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
71 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
72 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
73 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
74 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
75 | * THE POSSIBILITY OF SUCH DAMAGE. | |
76 | */ | |
77 | ||
78 | /* Portions of this work are licensed under the terms of the GNU GPL, | |
79 | * version 2 or later. See the COPYING file in the top-level directory. | |
80 | */ | |
81 | ||
cc43c692 MF |
82 | /* |
83 | * Define whether architecture deviates from IEEE in not supporting | |
213ff4e6 MF |
84 | * signaling NaNs (so all NaNs are treated as quiet). |
85 | */ | |
cc43c692 MF |
86 | static inline bool no_signaling_nans(float_status *status) |
87 | { | |
03385dfd | 88 | #if defined(TARGET_XTENSA) |
cc43c692 MF |
89 | return status->no_signaling_nans; |
90 | #else | |
91 | return false; | |
213ff4e6 | 92 | #endif |
cc43c692 | 93 | } |
213ff4e6 | 94 | |
03385dfd RH |
95 | /* Define how the architecture discriminates signaling NaNs. |
96 | * This done with the most significant bit of the fraction. | |
97 | * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 | |
98 | * the msb must be zero. MIPS is (so far) unique in supporting both the | |
99 | * 2008 revision and backward compatibility with their original choice. | |
100 | * Thus for MIPS we must make the choice at runtime. | |
101 | */ | |
c120391c | 102 | static inline bool snan_bit_is_one(float_status *status) |
03385dfd RH |
103 | { |
104 | #if defined(TARGET_MIPS) | |
105 | return status->snan_bit_is_one; | |
106 | #elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) | |
107 | return 1; | |
108 | #else | |
109 | return 0; | |
110 | #endif | |
111 | } | |
112 | ||
298b468e RH |
113 | /*---------------------------------------------------------------------------- |
114 | | For the deconstructed floating-point with fraction FRAC, return true | |
115 | | if the fraction represents a signalling NaN; otherwise false. | |
116 | *----------------------------------------------------------------------------*/ | |
117 | ||
118 | static bool parts_is_snan_frac(uint64_t frac, float_status *status) | |
119 | { | |
cc43c692 MF |
120 | if (no_signaling_nans(status)) { |
121 | return false; | |
122 | } else { | |
123 | bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); | |
124 | return msb == snan_bit_is_one(status); | |
125 | } | |
298b468e RH |
126 | } |
127 | ||
f7e598e2 RH |
128 | /*---------------------------------------------------------------------------- |
129 | | The pattern for a default generated deconstructed floating-point NaN. | |
130 | *----------------------------------------------------------------------------*/ | |
131 | ||
132 | static FloatParts parts_default_nan(float_status *status) | |
133 | { | |
134 | bool sign = 0; | |
135 | uint64_t frac; | |
136 | ||
137 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | |
8fb3d902 | 138 | /* !snan_bit_is_one, set all bits */ |
f7e598e2 | 139 | frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; |
8fb3d902 RH |
140 | #elif defined(TARGET_I386) || defined(TARGET_X86_64) \ |
141 | || defined(TARGET_MICROBLAZE) | |
142 | /* !snan_bit_is_one, set sign and msb */ | |
f7e598e2 | 143 | frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); |
8fb3d902 | 144 | sign = 1; |
f7e598e2 | 145 | #elif defined(TARGET_HPPA) |
8fb3d902 | 146 | /* snan_bit_is_one, set msb-1. */ |
f7e598e2 RH |
147 | frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); |
148 | #else | |
8fb3d902 RH |
149 | /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, |
150 | * S390, SH4, TriCore, and Xtensa. I cannot find documentation | |
151 | * for Unicore32; the choice from the original commit is unchanged. | |
152 | * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, | |
153 | * do not have floating-point. | |
154 | */ | |
03385dfd | 155 | if (snan_bit_is_one(status)) { |
8fb3d902 | 156 | /* set all bits other than msb */ |
f7e598e2 RH |
157 | frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; |
158 | } else { | |
8fb3d902 | 159 | /* set msb */ |
f7e598e2 | 160 | frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); |
f7e598e2 RH |
161 | } |
162 | #endif | |
163 | ||
164 | return (FloatParts) { | |
165 | .cls = float_class_qnan, | |
166 | .sign = sign, | |
167 | .exp = INT_MAX, | |
168 | .frac = frac | |
169 | }; | |
170 | } | |
171 | ||
0bcfbcbe RH |
172 | /*---------------------------------------------------------------------------- |
173 | | Returns a quiet NaN from a signalling NaN for the deconstructed | |
174 | | floating-point parts. | |
175 | *----------------------------------------------------------------------------*/ | |
176 | ||
177 | static FloatParts parts_silence_nan(FloatParts a, float_status *status) | |
178 | { | |
cc43c692 MF |
179 | g_assert(!no_signaling_nans(status)); |
180 | #if defined(TARGET_HPPA) | |
0bcfbcbe RH |
181 | a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); |
182 | a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); | |
183 | #else | |
03385dfd | 184 | if (snan_bit_is_one(status)) { |
0bcfbcbe RH |
185 | return parts_default_nan(status); |
186 | } else { | |
187 | a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); | |
188 | } | |
189 | #endif | |
190 | a.cls = float_class_qnan; | |
191 | return a; | |
192 | } | |
193 | ||
789ec7ce PB |
194 | /*---------------------------------------------------------------------------- |
195 | | The pattern for a default generated extended double-precision NaN. | |
196 | *----------------------------------------------------------------------------*/ | |
af39bc8c AM |
197 | floatx80 floatx80_default_nan(float_status *status) |
198 | { | |
199 | floatx80 r; | |
0218a16e RH |
200 | |
201 | /* None of the targets that have snan_bit_is_one use floatx80. */ | |
202 | assert(!snan_bit_is_one(status)); | |
e5b0cbe8 | 203 | #if defined(TARGET_M68K) |
f7e81a94 | 204 | r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); |
e5b0cbe8 LV |
205 | r.high = 0x7FFF; |
206 | #else | |
0218a16e | 207 | /* X86 */ |
f7e81a94 | 208 | r.low = UINT64_C(0xC000000000000000); |
0218a16e | 209 | r.high = 0xFFFF; |
e5b0cbe8 | 210 | #endif |
af39bc8c AM |
211 | return r; |
212 | } | |
789ec7ce | 213 | |
0f605c88 LV |
214 | /*---------------------------------------------------------------------------- |
215 | | The pattern for a default generated extended double-precision inf. | |
216 | *----------------------------------------------------------------------------*/ | |
217 | ||
218 | #define floatx80_infinity_high 0x7FFF | |
219 | #if defined(TARGET_M68K) | |
f7e81a94 | 220 | #define floatx80_infinity_low UINT64_C(0x0000000000000000) |
0f605c88 | 221 | #else |
f7e81a94 | 222 | #define floatx80_infinity_low UINT64_C(0x8000000000000000) |
0f605c88 LV |
223 | #endif |
224 | ||
225 | const floatx80 floatx80_infinity | |
226 | = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); | |
227 | ||
158142c2 FB |
228 | /*---------------------------------------------------------------------------- |
229 | | Raises the exceptions specified by `flags'. Floating-point traps can be | |
230 | | defined here if desired. It is currently not possible for such a trap | |
231 | | to substitute a result value. If traps are not implemented, this routine | |
232 | | should be simply `float_exception_flags |= flags;'. | |
233 | *----------------------------------------------------------------------------*/ | |
234 | ||
dfd60767 | 235 | void float_raise(uint8_t flags, float_status *status) |
158142c2 | 236 | { |
a2f2d288 | 237 | status->float_exception_flags |= flags; |
158142c2 FB |
238 | } |
239 | ||
240 | /*---------------------------------------------------------------------------- | |
241 | | Internal canonical NaN format. | |
242 | *----------------------------------------------------------------------------*/ | |
243 | typedef struct { | |
c120391c | 244 | bool sign; |
bb98fe42 | 245 | uint64_t high, low; |
158142c2 FB |
246 | } commonNaNT; |
247 | ||
bb4d4bb3 PM |
248 | /*---------------------------------------------------------------------------- |
249 | | Returns 1 if the half-precision floating-point value `a' is a quiet | |
250 | | NaN; otherwise returns 0. | |
251 | *----------------------------------------------------------------------------*/ | |
252 | ||
150c7a91 | 253 | bool float16_is_quiet_nan(float16 a_, float_status *status) |
bb4d4bb3 | 254 | { |
cc43c692 MF |
255 | if (no_signaling_nans(status)) { |
256 | return float16_is_any_nan(a_); | |
af39bc8c | 257 | } else { |
cc43c692 MF |
258 | uint16_t a = float16_val(a_); |
259 | if (snan_bit_is_one(status)) { | |
260 | return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); | |
261 | } else { | |
262 | ||
263 | return ((a >> 9) & 0x3F) == 0x3F; | |
264 | } | |
af39bc8c | 265 | } |
bb4d4bb3 PM |
266 | } |
267 | ||
5ebf5f4b LZ |
268 | /*---------------------------------------------------------------------------- |
269 | | Returns 1 if the bfloat16 value `a' is a quiet | |
270 | | NaN; otherwise returns 0. | |
271 | *----------------------------------------------------------------------------*/ | |
272 | ||
273 | bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) | |
274 | { | |
275 | if (no_signaling_nans(status)) { | |
276 | return bfloat16_is_any_nan(a_); | |
277 | } else { | |
278 | uint16_t a = a_; | |
279 | if (snan_bit_is_one(status)) { | |
280 | return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); | |
281 | } else { | |
282 | return ((a >> 6) & 0x1FF) == 0x1FF; | |
283 | } | |
284 | } | |
285 | } | |
286 | ||
bb4d4bb3 PM |
287 | /*---------------------------------------------------------------------------- |
288 | | Returns 1 if the half-precision floating-point value `a' is a signaling | |
289 | | NaN; otherwise returns 0. | |
290 | *----------------------------------------------------------------------------*/ | |
291 | ||
150c7a91 | 292 | bool float16_is_signaling_nan(float16 a_, float_status *status) |
bb4d4bb3 | 293 | { |
cc43c692 MF |
294 | if (no_signaling_nans(status)) { |
295 | return 0; | |
af39bc8c | 296 | } else { |
cc43c692 MF |
297 | uint16_t a = float16_val(a_); |
298 | if (snan_bit_is_one(status)) { | |
299 | return ((a >> 9) & 0x3F) == 0x3F; | |
300 | } else { | |
301 | return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); | |
302 | } | |
af39bc8c | 303 | } |
bca52234 | 304 | } |
bb4d4bb3 | 305 | |
5ebf5f4b LZ |
306 | /*---------------------------------------------------------------------------- |
307 | | Returns 1 if the bfloat16 value `a' is a signaling | |
308 | | NaN; otherwise returns 0. | |
309 | *----------------------------------------------------------------------------*/ | |
310 | ||
311 | bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) | |
312 | { | |
313 | if (no_signaling_nans(status)) { | |
314 | return 0; | |
315 | } else { | |
316 | uint16_t a = a_; | |
317 | if (snan_bit_is_one(status)) { | |
318 | return ((a >> 6) & 0x1FF) == 0x1FF; | |
319 | } else { | |
320 | return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); | |
321 | } | |
322 | } | |
323 | } | |
324 | ||
158142c2 | 325 | /*---------------------------------------------------------------------------- |
5a6932d5 TS |
326 | | Returns 1 if the single-precision floating-point value `a' is a quiet |
327 | | NaN; otherwise returns 0. | |
158142c2 FB |
328 | *----------------------------------------------------------------------------*/ |
329 | ||
150c7a91 | 330 | bool float32_is_quiet_nan(float32 a_, float_status *status) |
158142c2 | 331 | { |
cc43c692 MF |
332 | if (no_signaling_nans(status)) { |
333 | return float32_is_any_nan(a_); | |
af39bc8c | 334 | } else { |
cc43c692 MF |
335 | uint32_t a = float32_val(a_); |
336 | if (snan_bit_is_one(status)) { | |
337 | return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); | |
338 | } else { | |
339 | return ((uint32_t)(a << 1) >= 0xFF800000); | |
340 | } | |
af39bc8c | 341 | } |
158142c2 FB |
342 | } |
343 | ||
344 | /*---------------------------------------------------------------------------- | |
345 | | Returns 1 if the single-precision floating-point value `a' is a signaling | |
346 | | NaN; otherwise returns 0. | |
347 | *----------------------------------------------------------------------------*/ | |
348 | ||
150c7a91 | 349 | bool float32_is_signaling_nan(float32 a_, float_status *status) |
158142c2 | 350 | { |
cc43c692 MF |
351 | if (no_signaling_nans(status)) { |
352 | return 0; | |
af39bc8c | 353 | } else { |
cc43c692 MF |
354 | uint32_t a = float32_val(a_); |
355 | if (snan_bit_is_one(status)) { | |
356 | return ((uint32_t)(a << 1) >= 0xFF800000); | |
357 | } else { | |
358 | return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); | |
359 | } | |
af39bc8c | 360 | } |
bca52234 | 361 | } |
158142c2 FB |
362 | |
363 | /*---------------------------------------------------------------------------- | |
364 | | Returns the result of converting the single-precision floating-point NaN | |
365 | | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid | |
366 | | exception is raised. | |
367 | *----------------------------------------------------------------------------*/ | |
368 | ||
e5a41ffa | 369 | static commonNaNT float32ToCommonNaN(float32 a, float_status *status) |
158142c2 FB |
370 | { |
371 | commonNaNT z; | |
372 | ||
af39bc8c | 373 | if (float32_is_signaling_nan(a, status)) { |
ff32e16e PM |
374 | float_raise(float_flag_invalid, status); |
375 | } | |
a59eaea6 | 376 | z.sign = float32_val(a) >> 31; |
158142c2 | 377 | z.low = 0; |
a59eaea6 | 378 | z.high = ((uint64_t)float32_val(a)) << 41; |
158142c2 | 379 | return z; |
158142c2 FB |
380 | } |
381 | ||
382 | /*---------------------------------------------------------------------------- | |
383 | | Returns the result of converting the canonical NaN `a' to the single- | |
384 | | precision floating-point format. | |
385 | *----------------------------------------------------------------------------*/ | |
386 | ||
e5a41ffa | 387 | static float32 commonNaNToFloat32(commonNaNT a, float_status *status) |
158142c2 | 388 | { |
a59eaea6 | 389 | uint32_t mantissa = a.high >> 41; |
bcd4d9af | 390 | |
a2f2d288 | 391 | if (status->default_nan_mode) { |
af39bc8c | 392 | return float32_default_nan(status); |
bcd4d9af CL |
393 | } |
394 | ||
af39bc8c | 395 | if (mantissa) { |
85016c98 | 396 | return make_float32( |
a59eaea6 | 397 | (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); |
af39bc8c AM |
398 | } else { |
399 | return float32_default_nan(status); | |
400 | } | |
158142c2 FB |
401 | } |
402 | ||
354f211b PM |
403 | /*---------------------------------------------------------------------------- |
404 | | Select which NaN to propagate for a two-input operation. | |
405 | | IEEE754 doesn't specify all the details of this, so the | |
406 | | algorithm is target-specific. | |
407 | | The routine is passed various bits of information about the | |
408 | | two NaNs and should return 0 to select NaN a and 1 for NaN b. | |
409 | | Note that signalling NaNs are always squashed to quiet NaNs | |
4885312f | 410 | | by the caller, by calling floatXX_silence_nan() before |
1f398e08 | 411 | | returning them. |
354f211b PM |
412 | | |
413 | | aIsLargerSignificand is only valid if both a and b are NaNs | |
414 | | of some kind, and is true if a has the larger significand, | |
415 | | or if both a and b have the same significand but a is | |
416 | | positive but b is negative. It is only needed for the x87 | |
417 | | tie-break rule. | |
418 | *----------------------------------------------------------------------------*/ | |
419 | ||
4f251cfd | 420 | static int pickNaN(FloatClass a_cls, FloatClass b_cls, |
913602e3 | 421 | bool aIsLargerSignificand, float_status *status) |
011da610 | 422 | { |
4f251cfd | 423 | #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) |
13894527 AB |
424 | /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take |
425 | * the first of: | |
011da610 PM |
426 | * 1. A if it is signaling |
427 | * 2. B if it is signaling | |
428 | * 3. A (quiet) | |
429 | * 4. B (quiet) | |
430 | * A signaling NaN is always quietened before returning it. | |
431 | */ | |
084d19ba AJ |
432 | /* According to MIPS specifications, if one of the two operands is |
433 | * a sNaN, a new qNaN has to be generated. This is done in | |
4885312f | 434 | * floatXX_silence_nan(). For qNaN inputs the specifications |
084d19ba AJ |
435 | * says: "When possible, this QNaN result is one of the operand QNaN |
436 | * values." In practice it seems that most implementations choose | |
437 | * the first operand if both operands are qNaN. In short this gives | |
438 | * the following rules: | |
439 | * 1. A if it is signaling | |
440 | * 2. B if it is signaling | |
441 | * 3. A (quiet) | |
442 | * 4. B (quiet) | |
443 | * A signaling NaN is always silenced before returning it. | |
444 | */ | |
4f251cfd | 445 | if (is_snan(a_cls)) { |
084d19ba | 446 | return 0; |
4f251cfd | 447 | } else if (is_snan(b_cls)) { |
084d19ba | 448 | return 1; |
4f251cfd | 449 | } else if (is_qnan(a_cls)) { |
084d19ba AJ |
450 | return 0; |
451 | } else { | |
452 | return 1; | |
453 | } | |
913602e3 | 454 | #elif defined(TARGET_PPC) || defined(TARGET_M68K) |
e024e881 AJ |
455 | /* PowerPC propagation rules: |
456 | * 1. A if it sNaN or qNaN | |
457 | * 2. B if it sNaN or qNaN | |
458 | * A signaling NaN is always silenced before returning it. | |
459 | */ | |
e5b0cbe8 LV |
460 | /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL |
461 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS | |
462 | * If either operand, but not both operands, of an operation is a | |
463 | * nonsignaling NaN, then that NaN is returned as the result. If both | |
464 | * operands are nonsignaling NaNs, then the destination operand | |
465 | * nonsignaling NaN is returned as the result. | |
466 | * If either operand to an operation is a signaling NaN (SNaN), then the | |
467 | * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit | |
468 | * is set in the FPCR ENABLE byte, then the exception is taken and the | |
469 | * destination is not modified. If the SNaN exception enable bit is not | |
470 | * set, setting the SNaN bit in the operand to a one converts the SNaN to | |
471 | * a nonsignaling NaN. The operation then continues as described in the | |
472 | * preceding paragraph for nonsignaling NaNs. | |
473 | */ | |
4f251cfd RH |
474 | if (is_nan(a_cls)) { |
475 | return 0; | |
e5b0cbe8 | 476 | } else { |
4f251cfd | 477 | return 1; |
e5b0cbe8 | 478 | } |
913602e3 MF |
479 | #elif defined(TARGET_XTENSA) |
480 | /* | |
481 | * Xtensa has two NaN propagation modes. | |
482 | * Which one is active is controlled by float_status::use_first_nan. | |
483 | */ | |
484 | if (status->use_first_nan) { | |
485 | if (is_nan(a_cls)) { | |
486 | return 0; | |
487 | } else { | |
488 | return 1; | |
489 | } | |
490 | } else { | |
491 | if (is_nan(b_cls)) { | |
492 | return 1; | |
493 | } else { | |
494 | return 0; | |
495 | } | |
496 | } | |
011da610 | 497 | #else |
354f211b PM |
498 | /* This implements x87 NaN propagation rules: |
499 | * SNaN + QNaN => return the QNaN | |
500 | * two SNaNs => return the one with the larger significand, silenced | |
501 | * two QNaNs => return the one with the larger significand | |
502 | * SNaN and a non-NaN => return the SNaN, silenced | |
503 | * QNaN and a non-NaN => return the QNaN | |
504 | * | |
505 | * If we get down to comparing significands and they are the same, | |
506 | * return the NaN with the positive sign bit (if any). | |
507 | */ | |
4f251cfd RH |
508 | if (is_snan(a_cls)) { |
509 | if (is_snan(b_cls)) { | |
354f211b PM |
510 | return aIsLargerSignificand ? 0 : 1; |
511 | } | |
4f251cfd RH |
512 | return is_qnan(b_cls) ? 1 : 0; |
513 | } else if (is_qnan(a_cls)) { | |
514 | if (is_snan(b_cls) || !is_qnan(b_cls)) { | |
354f211b | 515 | return 0; |
a59eaea6 | 516 | } else { |
354f211b PM |
517 | return aIsLargerSignificand ? 0 : 1; |
518 | } | |
519 | } else { | |
520 | return 1; | |
521 | } | |
011da610 | 522 | #endif |
4f251cfd | 523 | } |
354f211b | 524 | |
369be8f6 PM |
525 | /*---------------------------------------------------------------------------- |
526 | | Select which NaN to propagate for a three-input operation. | |
527 | | For the moment we assume that no CPU needs the 'larger significand' | |
528 | | information. | |
529 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | |
530 | *----------------------------------------------------------------------------*/ | |
3bd2dec1 RH |
531 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, |
532 | bool infzero, float_status *status) | |
369be8f6 | 533 | { |
3bd2dec1 | 534 | #if defined(TARGET_ARM) |
369be8f6 PM |
535 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns |
536 | * the default NaN | |
537 | */ | |
3bd2dec1 | 538 | if (infzero && is_qnan(c_cls)) { |
ff32e16e | 539 | float_raise(float_flag_invalid, status); |
369be8f6 PM |
540 | return 3; |
541 | } | |
542 | ||
543 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | |
544 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | |
545 | */ | |
3bd2dec1 | 546 | if (is_snan(c_cls)) { |
369be8f6 | 547 | return 2; |
3bd2dec1 | 548 | } else if (is_snan(a_cls)) { |
369be8f6 | 549 | return 0; |
3bd2dec1 | 550 | } else if (is_snan(b_cls)) { |
369be8f6 | 551 | return 1; |
3bd2dec1 | 552 | } else if (is_qnan(c_cls)) { |
369be8f6 | 553 | return 2; |
3bd2dec1 | 554 | } else if (is_qnan(a_cls)) { |
369be8f6 PM |
555 | return 0; |
556 | } else { | |
557 | return 1; | |
558 | } | |
bbc1dede | 559 | #elif defined(TARGET_MIPS) |
03385dfd | 560 | if (snan_bit_is_one(status)) { |
7ca96e1a MM |
561 | /* |
562 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | |
563 | * case sets InvalidOp and returns the default NaN | |
564 | */ | |
565 | if (infzero) { | |
566 | float_raise(float_flag_invalid, status); | |
567 | return 3; | |
568 | } | |
c27644f0 | 569 | /* Prefer sNaN over qNaN, in the a, b, c order. */ |
3bd2dec1 | 570 | if (is_snan(a_cls)) { |
c27644f0 | 571 | return 0; |
3bd2dec1 | 572 | } else if (is_snan(b_cls)) { |
c27644f0 | 573 | return 1; |
3bd2dec1 | 574 | } else if (is_snan(c_cls)) { |
c27644f0 | 575 | return 2; |
3bd2dec1 | 576 | } else if (is_qnan(a_cls)) { |
c27644f0 | 577 | return 0; |
3bd2dec1 | 578 | } else if (is_qnan(b_cls)) { |
c27644f0 AM |
579 | return 1; |
580 | } else { | |
581 | return 2; | |
582 | } | |
bbc1dede | 583 | } else { |
7ca96e1a MM |
584 | /* |
585 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | |
586 | * case sets InvalidOp and returns the input value 'c' | |
587 | */ | |
588 | if (infzero) { | |
589 | float_raise(float_flag_invalid, status); | |
590 | return 2; | |
591 | } | |
c27644f0 | 592 | /* Prefer sNaN over qNaN, in the c, a, b order. */ |
3bd2dec1 | 593 | if (is_snan(c_cls)) { |
c27644f0 | 594 | return 2; |
3bd2dec1 | 595 | } else if (is_snan(a_cls)) { |
c27644f0 | 596 | return 0; |
3bd2dec1 | 597 | } else if (is_snan(b_cls)) { |
c27644f0 | 598 | return 1; |
3bd2dec1 | 599 | } else if (is_qnan(c_cls)) { |
c27644f0 | 600 | return 2; |
3bd2dec1 | 601 | } else if (is_qnan(a_cls)) { |
c27644f0 AM |
602 | return 0; |
603 | } else { | |
604 | return 1; | |
605 | } | |
bbc1dede | 606 | } |
369be8f6 | 607 | #elif defined(TARGET_PPC) |
369be8f6 PM |
608 | /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer |
609 | * to return an input NaN if we have one (ie c) rather than generating | |
610 | * a default NaN | |
611 | */ | |
612 | if (infzero) { | |
ff32e16e | 613 | float_raise(float_flag_invalid, status); |
369be8f6 PM |
614 | return 2; |
615 | } | |
616 | ||
617 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | |
618 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | |
619 | */ | |
3bd2dec1 | 620 | if (is_nan(a_cls)) { |
369be8f6 | 621 | return 0; |
3bd2dec1 | 622 | } else if (is_nan(c_cls)) { |
369be8f6 PM |
623 | return 2; |
624 | } else { | |
625 | return 1; | |
626 | } | |
fbcc38e4 MF |
627 | #elif defined(TARGET_XTENSA) |
628 | /* | |
629 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | |
630 | * an input NaN if we have one (ie c). | |
631 | */ | |
632 | if (infzero) { | |
633 | float_raise(float_flag_invalid, status); | |
634 | return 2; | |
635 | } | |
636 | if (status->use_first_nan) { | |
637 | if (is_nan(a_cls)) { | |
638 | return 0; | |
639 | } else if (is_nan(b_cls)) { | |
640 | return 1; | |
641 | } else { | |
642 | return 2; | |
643 | } | |
644 | } else { | |
645 | if (is_nan(c_cls)) { | |
646 | return 2; | |
647 | } else if (is_nan(b_cls)) { | |
648 | return 1; | |
649 | } else { | |
650 | return 0; | |
651 | } | |
652 | } | |
369be8f6 | 653 | #else |
3bd2dec1 RH |
654 | /* A default implementation: prefer a to b to c. |
655 | * This is unlikely to actually match any real implementation. | |
656 | */ | |
657 | if (is_nan(a_cls)) { | |
369be8f6 | 658 | return 0; |
3bd2dec1 | 659 | } else if (is_nan(b_cls)) { |
369be8f6 PM |
660 | return 1; |
661 | } else { | |
662 | return 2; | |
663 | } | |
369be8f6 | 664 | #endif |
3bd2dec1 | 665 | } |
369be8f6 | 666 | |
158142c2 FB |
667 | /*---------------------------------------------------------------------------- |
668 | | Takes two single-precision floating-point values `a' and `b', one of which | |
669 | | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a | |
670 | | signaling NaN, the invalid exception is raised. | |
671 | *----------------------------------------------------------------------------*/ | |
672 | ||
e5a41ffa | 673 | static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) |
158142c2 | 674 | { |
c120391c | 675 | bool aIsLargerSignificand; |
bb98fe42 | 676 | uint32_t av, bv; |
4f251cfd RH |
677 | FloatClass a_cls, b_cls; |
678 | ||
679 | /* This is not complete, but is good enough for pickNaN. */ | |
680 | a_cls = (!float32_is_any_nan(a) | |
681 | ? float_class_normal | |
682 | : float32_is_signaling_nan(a, status) | |
683 | ? float_class_snan | |
684 | : float_class_qnan); | |
685 | b_cls = (!float32_is_any_nan(b) | |
686 | ? float_class_normal | |
687 | : float32_is_signaling_nan(b, status) | |
688 | ? float_class_snan | |
689 | : float_class_qnan); | |
158142c2 | 690 | |
f090c9d4 PB |
691 | av = float32_val(a); |
692 | bv = float32_val(b); | |
1f398e08 | 693 | |
4f251cfd | 694 | if (is_snan(a_cls) || is_snan(b_cls)) { |
ff32e16e PM |
695 | float_raise(float_flag_invalid, status); |
696 | } | |
354f211b | 697 | |
af39bc8c AM |
698 | if (status->default_nan_mode) { |
699 | return float32_default_nan(status); | |
700 | } | |
10201602 | 701 | |
a59eaea6 | 702 | if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { |
354f211b | 703 | aIsLargerSignificand = 0; |
a59eaea6 | 704 | } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { |
354f211b PM |
705 | aIsLargerSignificand = 1; |
706 | } else { | |
707 | aIsLargerSignificand = (av < bv) ? 1 : 0; | |
158142c2 | 708 | } |
354f211b | 709 | |
913602e3 | 710 | if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
4f251cfd | 711 | if (is_snan(b_cls)) { |
4885312f RH |
712 | return float32_silence_nan(b, status); |
713 | } | |
714 | return b; | |
354f211b | 715 | } else { |
4f251cfd | 716 | if (is_snan(a_cls)) { |
4885312f RH |
717 | return float32_silence_nan(a, status); |
718 | } | |
719 | return a; | |
158142c2 | 720 | } |
158142c2 FB |
721 | } |
722 | ||
158142c2 | 723 | /*---------------------------------------------------------------------------- |
5a6932d5 TS |
724 | | Returns 1 if the double-precision floating-point value `a' is a quiet |
725 | | NaN; otherwise returns 0. | |
158142c2 FB |
726 | *----------------------------------------------------------------------------*/ |
727 | ||
150c7a91 | 728 | bool float64_is_quiet_nan(float64 a_, float_status *status) |
158142c2 | 729 | { |
cc43c692 MF |
730 | if (no_signaling_nans(status)) { |
731 | return float64_is_any_nan(a_); | |
af39bc8c | 732 | } else { |
cc43c692 MF |
733 | uint64_t a = float64_val(a_); |
734 | if (snan_bit_is_one(status)) { | |
735 | return (((a >> 51) & 0xFFF) == 0xFFE) | |
736 | && (a & 0x0007FFFFFFFFFFFFULL); | |
737 | } else { | |
738 | return ((a << 1) >= 0xFFF0000000000000ULL); | |
739 | } | |
af39bc8c | 740 | } |
158142c2 FB |
741 | } |
742 | ||
743 | /*---------------------------------------------------------------------------- | |
744 | | Returns 1 if the double-precision floating-point value `a' is a signaling | |
745 | | NaN; otherwise returns 0. | |
746 | *----------------------------------------------------------------------------*/ | |
747 | ||
150c7a91 | 748 | bool float64_is_signaling_nan(float64 a_, float_status *status) |
158142c2 | 749 | { |
cc43c692 MF |
750 | if (no_signaling_nans(status)) { |
751 | return 0; | |
af39bc8c | 752 | } else { |
cc43c692 MF |
753 | uint64_t a = float64_val(a_); |
754 | if (snan_bit_is_one(status)) { | |
755 | return ((a << 1) >= 0xFFF0000000000000ULL); | |
756 | } else { | |
757 | return (((a >> 51) & 0xFFF) == 0xFFE) | |
758 | && (a & UINT64_C(0x0007FFFFFFFFFFFF)); | |
759 | } | |
af39bc8c | 760 | } |
bca52234 | 761 | } |
158142c2 FB |
762 | |
763 | /*---------------------------------------------------------------------------- | |
764 | | Returns the result of converting the double-precision floating-point NaN | |
765 | | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid | |
766 | | exception is raised. | |
767 | *----------------------------------------------------------------------------*/ | |
768 | ||
e5a41ffa | 769 | static commonNaNT float64ToCommonNaN(float64 a, float_status *status) |
158142c2 FB |
770 | { |
771 | commonNaNT z; | |
772 | ||
af39bc8c | 773 | if (float64_is_signaling_nan(a, status)) { |
ff32e16e PM |
774 | float_raise(float_flag_invalid, status); |
775 | } | |
a59eaea6 | 776 | z.sign = float64_val(a) >> 63; |
158142c2 | 777 | z.low = 0; |
a59eaea6 | 778 | z.high = float64_val(a) << 12; |
158142c2 | 779 | return z; |
158142c2 FB |
780 | } |
781 | ||
782 | /*---------------------------------------------------------------------------- | |
783 | | Returns the result of converting the canonical NaN `a' to the double- | |
784 | | precision floating-point format. | |
785 | *----------------------------------------------------------------------------*/ | |
786 | ||
e5a41ffa | 787 | static float64 commonNaNToFloat64(commonNaNT a, float_status *status) |
158142c2 | 788 | { |
a59eaea6 | 789 | uint64_t mantissa = a.high >> 12; |
85016c98 | 790 | |
a2f2d288 | 791 | if (status->default_nan_mode) { |
af39bc8c | 792 | return float64_default_nan(status); |
bcd4d9af CL |
793 | } |
794 | ||
af39bc8c | 795 | if (mantissa) { |
85016c98 | 796 | return make_float64( |
a59eaea6 | 797 | (((uint64_t) a.sign) << 63) |
f7e81a94 | 798 | | UINT64_C(0x7FF0000000000000) |
a59eaea6 | 799 | | (a.high >> 12)); |
af39bc8c AM |
800 | } else { |
801 | return float64_default_nan(status); | |
802 | } | |
158142c2 FB |
803 | } |
804 | ||
805 | /*---------------------------------------------------------------------------- | |
806 | | Takes two double-precision floating-point values `a' and `b', one of which | |
807 | | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a | |
808 | | signaling NaN, the invalid exception is raised. | |
809 | *----------------------------------------------------------------------------*/ | |
810 | ||
e5a41ffa | 811 | static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) |
158142c2 | 812 | { |
c120391c | 813 | bool aIsLargerSignificand; |
bb98fe42 | 814 | uint64_t av, bv; |
4f251cfd RH |
815 | FloatClass a_cls, b_cls; |
816 | ||
817 | /* This is not complete, but is good enough for pickNaN. */ | |
818 | a_cls = (!float64_is_any_nan(a) | |
819 | ? float_class_normal | |
820 | : float64_is_signaling_nan(a, status) | |
821 | ? float_class_snan | |
822 | : float_class_qnan); | |
823 | b_cls = (!float64_is_any_nan(b) | |
824 | ? float_class_normal | |
825 | : float64_is_signaling_nan(b, status) | |
826 | ? float_class_snan | |
827 | : float_class_qnan); | |
158142c2 | 828 | |
f090c9d4 PB |
829 | av = float64_val(a); |
830 | bv = float64_val(b); | |
1f398e08 | 831 | |
4f251cfd | 832 | if (is_snan(a_cls) || is_snan(b_cls)) { |
ff32e16e PM |
833 | float_raise(float_flag_invalid, status); |
834 | } | |
354f211b | 835 | |
af39bc8c AM |
836 | if (status->default_nan_mode) { |
837 | return float64_default_nan(status); | |
838 | } | |
10201602 | 839 | |
a59eaea6 | 840 | if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { |
354f211b | 841 | aIsLargerSignificand = 0; |
a59eaea6 | 842 | } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { |
354f211b PM |
843 | aIsLargerSignificand = 1; |
844 | } else { | |
845 | aIsLargerSignificand = (av < bv) ? 1 : 0; | |
158142c2 | 846 | } |
354f211b | 847 | |
913602e3 | 848 | if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
4f251cfd | 849 | if (is_snan(b_cls)) { |
4885312f RH |
850 | return float64_silence_nan(b, status); |
851 | } | |
852 | return b; | |
354f211b | 853 | } else { |
4f251cfd | 854 | if (is_snan(a_cls)) { |
4885312f RH |
855 | return float64_silence_nan(a, status); |
856 | } | |
857 | return a; | |
158142c2 | 858 | } |
158142c2 FB |
859 | } |
860 | ||
158142c2 FB |
861 | /*---------------------------------------------------------------------------- |
862 | | Returns 1 if the extended double-precision floating-point value `a' is a | |
de4af5f7 AJ |
863 | | quiet NaN; otherwise returns 0. This slightly differs from the same |
864 | | function for other types as floatx80 has an explicit bit. | |
158142c2 FB |
865 | *----------------------------------------------------------------------------*/ |
866 | ||
af39bc8c | 867 | int floatx80_is_quiet_nan(floatx80 a, float_status *status) |
158142c2 | 868 | { |
cc43c692 MF |
869 | if (no_signaling_nans(status)) { |
870 | return floatx80_is_any_nan(a); | |
af39bc8c | 871 | } else { |
cc43c692 MF |
872 | if (snan_bit_is_one(status)) { |
873 | uint64_t aLow; | |
874 | ||
875 | aLow = a.low & ~0x4000000000000000ULL; | |
876 | return ((a.high & 0x7FFF) == 0x7FFF) | |
877 | && (aLow << 1) | |
878 | && (a.low == aLow); | |
879 | } else { | |
880 | return ((a.high & 0x7FFF) == 0x7FFF) | |
881 | && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); | |
882 | } | |
af39bc8c | 883 | } |
158142c2 FB |
884 | } |
885 | ||
886 | /*---------------------------------------------------------------------------- | |
887 | | Returns 1 if the extended double-precision floating-point value `a' is a | |
de4af5f7 AJ |
888 | | signaling NaN; otherwise returns 0. This slightly differs from the same |
889 | | function for other types as floatx80 has an explicit bit. | |
158142c2 FB |
890 | *----------------------------------------------------------------------------*/ |
891 | ||
af39bc8c | 892 | int floatx80_is_signaling_nan(floatx80 a, float_status *status) |
158142c2 | 893 | { |
cc43c692 MF |
894 | if (no_signaling_nans(status)) { |
895 | return 0; | |
af39bc8c | 896 | } else { |
cc43c692 MF |
897 | if (snan_bit_is_one(status)) { |
898 | return ((a.high & 0x7FFF) == 0x7FFF) | |
899 | && ((a.low << 1) >= 0x8000000000000000ULL); | |
900 | } else { | |
901 | uint64_t aLow; | |
158142c2 | 902 | |
cc43c692 MF |
903 | aLow = a.low & ~UINT64_C(0x4000000000000000); |
904 | return ((a.high & 0x7FFF) == 0x7FFF) | |
905 | && (uint64_t)(aLow << 1) | |
906 | && (a.low == aLow); | |
907 | } | |
af39bc8c | 908 | } |
bca52234 | 909 | } |
158142c2 | 910 | |
d619bb98 RH |
911 | /*---------------------------------------------------------------------------- |
912 | | Returns a quiet NaN from a signalling NaN for the extended double-precision | |
913 | | floating point value `a'. | |
914 | *----------------------------------------------------------------------------*/ | |
915 | ||
916 | floatx80 floatx80_silence_nan(floatx80 a, float_status *status) | |
917 | { | |
377ed926 RH |
918 | /* None of the targets that have snan_bit_is_one use floatx80. */ |
919 | assert(!snan_bit_is_one(status)); | |
f7e81a94 | 920 | a.low |= UINT64_C(0xC000000000000000); |
377ed926 | 921 | return a; |
d619bb98 RH |
922 | } |
923 | ||
158142c2 FB |
924 | /*---------------------------------------------------------------------------- |
925 | | Returns the result of converting the extended double-precision floating- | |
926 | | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the | |
927 | | invalid exception is raised. | |
928 | *----------------------------------------------------------------------------*/ | |
929 | ||
e5a41ffa | 930 | static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) |
158142c2 | 931 | { |
af39bc8c | 932 | floatx80 dflt; |
158142c2 FB |
933 | commonNaNT z; |
934 | ||
af39bc8c | 935 | if (floatx80_is_signaling_nan(a, status)) { |
ff32e16e PM |
936 | float_raise(float_flag_invalid, status); |
937 | } | |
a59eaea6 | 938 | if (a.low >> 63) { |
e2f42204 AJ |
939 | z.sign = a.high >> 15; |
940 | z.low = 0; | |
941 | z.high = a.low << 1; | |
942 | } else { | |
af39bc8c AM |
943 | dflt = floatx80_default_nan(status); |
944 | z.sign = dflt.high >> 15; | |
e2f42204 | 945 | z.low = 0; |
af39bc8c | 946 | z.high = dflt.low << 1; |
e2f42204 | 947 | } |
158142c2 | 948 | return z; |
158142c2 FB |
949 | } |
950 | ||
951 | /*---------------------------------------------------------------------------- | |
952 | | Returns the result of converting the canonical NaN `a' to the extended | |
953 | | double-precision floating-point format. | |
954 | *----------------------------------------------------------------------------*/ | |
955 | ||
e5a41ffa | 956 | static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) |
158142c2 FB |
957 | { |
958 | floatx80 z; | |
959 | ||
a2f2d288 | 960 | if (status->default_nan_mode) { |
af39bc8c | 961 | return floatx80_default_nan(status); |
bcd4d9af CL |
962 | } |
963 | ||
e2f42204 | 964 | if (a.high >> 1) { |
f7e81a94 | 965 | z.low = UINT64_C(0x8000000000000000) | a.high >> 1; |
a59eaea6 | 966 | z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; |
e2f42204 | 967 | } else { |
af39bc8c | 968 | z = floatx80_default_nan(status); |
e2f42204 | 969 | } |
158142c2 | 970 | return z; |
158142c2 FB |
971 | } |
972 | ||
973 | /*---------------------------------------------------------------------------- | |
974 | | Takes two extended double-precision floating-point values `a' and `b', one | |
975 | | of which is a NaN, and returns the appropriate NaN result. If either `a' or | |
976 | | `b' is a signaling NaN, the invalid exception is raised. | |
977 | *----------------------------------------------------------------------------*/ | |
978 | ||
88857aca | 979 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
158142c2 | 980 | { |
c120391c | 981 | bool aIsLargerSignificand; |
4f251cfd RH |
982 | FloatClass a_cls, b_cls; |
983 | ||
984 | /* This is not complete, but is good enough for pickNaN. */ | |
985 | a_cls = (!floatx80_is_any_nan(a) | |
986 | ? float_class_normal | |
987 | : floatx80_is_signaling_nan(a, status) | |
988 | ? float_class_snan | |
989 | : float_class_qnan); | |
990 | b_cls = (!floatx80_is_any_nan(b) | |
991 | ? float_class_normal | |
992 | : floatx80_is_signaling_nan(b, status) | |
993 | ? float_class_snan | |
994 | : float_class_qnan); | |
995 | ||
996 | if (is_snan(a_cls) || is_snan(b_cls)) { | |
ff32e16e PM |
997 | float_raise(float_flag_invalid, status); |
998 | } | |
354f211b | 999 | |
a2f2d288 | 1000 | if (status->default_nan_mode) { |
af39bc8c | 1001 | return floatx80_default_nan(status); |
10201602 AJ |
1002 | } |
1003 | ||
354f211b PM |
1004 | if (a.low < b.low) { |
1005 | aIsLargerSignificand = 0; | |
1006 | } else if (b.low < a.low) { | |
1007 | aIsLargerSignificand = 1; | |
1008 | } else { | |
1009 | aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | |
158142c2 | 1010 | } |
354f211b | 1011 | |
913602e3 | 1012 | if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
4f251cfd | 1013 | if (is_snan(b_cls)) { |
4885312f RH |
1014 | return floatx80_silence_nan(b, status); |
1015 | } | |
1016 | return b; | |
354f211b | 1017 | } else { |
4f251cfd | 1018 | if (is_snan(a_cls)) { |
4885312f RH |
1019 | return floatx80_silence_nan(a, status); |
1020 | } | |
1021 | return a; | |
158142c2 | 1022 | } |
158142c2 FB |
1023 | } |
1024 | ||
158142c2 | 1025 | /*---------------------------------------------------------------------------- |
5a6932d5 TS |
1026 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet |
1027 | | NaN; otherwise returns 0. | |
158142c2 FB |
1028 | *----------------------------------------------------------------------------*/ |
1029 | ||
150c7a91 | 1030 | bool float128_is_quiet_nan(float128 a, float_status *status) |
158142c2 | 1031 | { |
cc43c692 MF |
1032 | if (no_signaling_nans(status)) { |
1033 | return float128_is_any_nan(a); | |
af39bc8c | 1034 | } else { |
cc43c692 MF |
1035 | if (snan_bit_is_one(status)) { |
1036 | return (((a.high >> 47) & 0xFFFF) == 0xFFFE) | |
1037 | && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); | |
1038 | } else { | |
1039 | return ((a.high << 1) >= 0xFFFF000000000000ULL) | |
1040 | && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); | |
1041 | } | |
af39bc8c | 1042 | } |
158142c2 FB |
1043 | } |
1044 | ||
1045 | /*---------------------------------------------------------------------------- | |
1046 | | Returns 1 if the quadruple-precision floating-point value `a' is a | |
1047 | | signaling NaN; otherwise returns 0. | |
1048 | *----------------------------------------------------------------------------*/ | |
1049 | ||
150c7a91 | 1050 | bool float128_is_signaling_nan(float128 a, float_status *status) |
158142c2 | 1051 | { |
cc43c692 MF |
1052 | if (no_signaling_nans(status)) { |
1053 | return 0; | |
af39bc8c | 1054 | } else { |
cc43c692 MF |
1055 | if (snan_bit_is_one(status)) { |
1056 | return ((a.high << 1) >= 0xFFFF000000000000ULL) | |
1057 | && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); | |
1058 | } else { | |
1059 | return (((a.high >> 47) & 0xFFFF) == 0xFFFE) | |
1060 | && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); | |
1061 | } | |
af39bc8c | 1062 | } |
bca52234 | 1063 | } |
158142c2 | 1064 | |
d619bb98 RH |
1065 | /*---------------------------------------------------------------------------- |
1066 | | Returns a quiet NaN from a signalling NaN for the quadruple-precision | |
1067 | | floating point value `a'. | |
1068 | *----------------------------------------------------------------------------*/ | |
1069 | ||
1070 | float128 float128_silence_nan(float128 a, float_status *status) | |
1071 | { | |
cc43c692 MF |
1072 | if (no_signaling_nans(status)) { |
1073 | g_assert_not_reached(); | |
d619bb98 | 1074 | } else { |
cc43c692 MF |
1075 | if (snan_bit_is_one(status)) { |
1076 | return float128_default_nan(status); | |
1077 | } else { | |
1078 | a.high |= UINT64_C(0x0000800000000000); | |
1079 | return a; | |
1080 | } | |
d619bb98 | 1081 | } |
d619bb98 RH |
1082 | } |
1083 | ||
158142c2 FB |
1084 | /*---------------------------------------------------------------------------- |
1085 | | Returns the result of converting the quadruple-precision floating-point NaN | |
1086 | | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid | |
1087 | | exception is raised. | |
1088 | *----------------------------------------------------------------------------*/ | |
1089 | ||
e5a41ffa | 1090 | static commonNaNT float128ToCommonNaN(float128 a, float_status *status) |
158142c2 FB |
1091 | { |
1092 | commonNaNT z; | |
1093 | ||
af39bc8c | 1094 | if (float128_is_signaling_nan(a, status)) { |
ff32e16e PM |
1095 | float_raise(float_flag_invalid, status); |
1096 | } | |
a59eaea6 AM |
1097 | z.sign = a.high >> 63; |
1098 | shortShift128Left(a.high, a.low, 16, &z.high, &z.low); | |
158142c2 | 1099 | return z; |
158142c2 FB |
1100 | } |
1101 | ||
1102 | /*---------------------------------------------------------------------------- | |
1103 | | Returns the result of converting the canonical NaN `a' to the quadruple- | |
1104 | | precision floating-point format. | |
1105 | *----------------------------------------------------------------------------*/ | |
1106 | ||
e5a41ffa | 1107 | static float128 commonNaNToFloat128(commonNaNT a, float_status *status) |
158142c2 FB |
1108 | { |
1109 | float128 z; | |
1110 | ||
a2f2d288 | 1111 | if (status->default_nan_mode) { |
af39bc8c | 1112 | return float128_default_nan(status); |
bcd4d9af CL |
1113 | } |
1114 | ||
a59eaea6 | 1115 | shift128Right(a.high, a.low, 16, &z.high, &z.low); |
f7e81a94 | 1116 | z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); |
158142c2 | 1117 | return z; |
158142c2 FB |
1118 | } |
1119 | ||
1120 | /*---------------------------------------------------------------------------- | |
1121 | | Takes two quadruple-precision floating-point values `a' and `b', one of | |
1122 | | which is a NaN, and returns the appropriate NaN result. If either `a' or | |
1123 | | `b' is a signaling NaN, the invalid exception is raised. | |
1124 | *----------------------------------------------------------------------------*/ | |
1125 | ||
e5a41ffa PM |
1126 | static float128 propagateFloat128NaN(float128 a, float128 b, |
1127 | float_status *status) | |
158142c2 | 1128 | { |
c120391c | 1129 | bool aIsLargerSignificand; |
4f251cfd RH |
1130 | FloatClass a_cls, b_cls; |
1131 | ||
1132 | /* This is not complete, but is good enough for pickNaN. */ | |
1133 | a_cls = (!float128_is_any_nan(a) | |
1134 | ? float_class_normal | |
1135 | : float128_is_signaling_nan(a, status) | |
1136 | ? float_class_snan | |
1137 | : float_class_qnan); | |
1138 | b_cls = (!float128_is_any_nan(b) | |
1139 | ? float_class_normal | |
1140 | : float128_is_signaling_nan(b, status) | |
1141 | ? float_class_snan | |
1142 | : float_class_qnan); | |
1143 | ||
1144 | if (is_snan(a_cls) || is_snan(b_cls)) { | |
ff32e16e PM |
1145 | float_raise(float_flag_invalid, status); |
1146 | } | |
354f211b | 1147 | |
a2f2d288 | 1148 | if (status->default_nan_mode) { |
af39bc8c | 1149 | return float128_default_nan(status); |
10201602 AJ |
1150 | } |
1151 | ||
a59eaea6 | 1152 | if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { |
354f211b | 1153 | aIsLargerSignificand = 0; |
a59eaea6 | 1154 | } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { |
354f211b PM |
1155 | aIsLargerSignificand = 1; |
1156 | } else { | |
1157 | aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | |
158142c2 | 1158 | } |
354f211b | 1159 | |
913602e3 | 1160 | if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
4f251cfd | 1161 | if (is_snan(b_cls)) { |
4885312f RH |
1162 | return float128_silence_nan(b, status); |
1163 | } | |
1164 | return b; | |
354f211b | 1165 | } else { |
4f251cfd | 1166 | if (is_snan(a_cls)) { |
4885312f RH |
1167 | return float128_silence_nan(a, status); |
1168 | } | |
1169 | return a; | |
158142c2 | 1170 | } |
158142c2 | 1171 | } |