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1 | <?xml version="1.0"?> |
2 | <!-- | |
3 | Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved. | |
4 | ||
5 | This work is licensed under the terms of the GNU GPL, version 2 or | |
6 | (at your option) any later version. See the COPYING file in the | |
7 | top-level directory. | |
8 | ||
9 | Note: this file is intended to be use with LLDB, so it contains fields | |
10 | that may be unknown to GDB. For more information on such fields, please | |
11 | see: | |
12 | https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-gdb-remote.txt#L738-L860 | |
13 | https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp#L4275-L4335 | |
14 | --> | |
15 | ||
16 | <!DOCTYPE feature SYSTEM "gdb-target.dtd"> | |
17 | <feature name="org.gnu.gdb.hexagon.hvx"> | |
18 | ||
19 | <vector id="vud" type="uint64" count="16"/> | |
20 | <vector id="vd" type="int64" count="16"/> | |
21 | <vector id="vuw" type="uint32" count="32"/> | |
22 | <vector id="vw" type="int32" count="32"/> | |
23 | <vector id="vuh" type="uint16" count="64"/> | |
24 | <vector id="vh" type="int16" count="64"/> | |
25 | <vector id="vub" type="uint8" count="128"/> | |
26 | <vector id="vb" type="int8" count="128"/> | |
27 | <union id="hex_vec"> | |
28 | <field name="ud" type="vud"/> | |
29 | <field name="d" type="vd"/> | |
30 | <field name="uw" type="vuw"/> | |
31 | <field name="w" type="vw"/> | |
32 | <field name="uh" type="vuh"/> | |
33 | <field name="h" type="vh"/> | |
34 | <field name="ub" type="vub"/> | |
35 | <field name="b" type="vb"/> | |
36 | </union> | |
37 | ||
38 | <flags id="ui2" size="1"> | |
39 | <field name="0" start="0" end="0"/> | |
40 | <field name="1" start="1" end="1"/> | |
41 | </flags> | |
42 | <flags id="ui4" size="1"> | |
43 | <field name="0" start="0" end="0"/> | |
44 | <field name="1" start="1" end="1"/> | |
45 | <field name="2" start="2" end="2"/> | |
46 | <field name="3" start="3" end="3"/> | |
47 | </flags> | |
48 | <vector id="vpd" type="uint8" count="16"/> | |
49 | <vector id="vpw" type="ui4" count="32"/> | |
50 | <vector id="vph" type="ui2" count="64"/> | |
51 | <vector id="vpb" type="bool" count="128"/> | |
52 | <union id="hex_vec_pred"> | |
53 | <field name="d" type="vpd"/> | |
54 | <field name="w" type="vpw"/> | |
55 | <field name="h" type="vph"/> | |
56 | <field name="b" type="vpb"/> | |
57 | </union> | |
58 | ||
59 | <reg name="v0" bitsize="1024" offset="256" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="88"/> | |
60 | <reg name="v1" bitsize="1024" offset="384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="89"/> | |
61 | <reg name="v2" bitsize="1024" offset="512" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="90"/> | |
62 | <reg name="v3" bitsize="1024" offset="640" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="91"/> | |
63 | <reg name="v4" bitsize="1024" offset="768" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="92"/> | |
64 | <reg name="v5" bitsize="1024" offset="896" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="93"/> | |
65 | <reg name="v6" bitsize="1024" offset="1024" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="94"/> | |
66 | <reg name="v7" bitsize="1024" offset="1152" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="95"/> | |
67 | <reg name="v8" bitsize="1024" offset="1280" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="96"/> | |
68 | <reg name="v9" bitsize="1024" offset="1408" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="97"/> | |
69 | <reg name="v10" bitsize="1024" offset="1536" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="98"/> | |
70 | <reg name="v11" bitsize="1024" offset="1664" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="99"/> | |
71 | <reg name="v12" bitsize="1024" offset="1792" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="100"/> | |
72 | <reg name="v13" bitsize="1024" offset="1920" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="101"/> | |
73 | <reg name="v14" bitsize="1024" offset="2048" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="102"/> | |
74 | <reg name="v15" bitsize="1024" offset="2176" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="103"/> | |
75 | <reg name="v16" bitsize="1024" offset="2304" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="104"/> | |
76 | <reg name="v17" bitsize="1024" offset="2432" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="105"/> | |
77 | <reg name="v18" bitsize="1024" offset="2560" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="106"/> | |
78 | <reg name="v19" bitsize="1024" offset="2688" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="107"/> | |
79 | <reg name="v20" bitsize="1024" offset="2816" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="108"/> | |
80 | <reg name="v21" bitsize="1024" offset="2944" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="109"/> | |
81 | <reg name="v22" bitsize="1024" offset="3072" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="110"/> | |
82 | <reg name="v23" bitsize="1024" offset="3200" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="111"/> | |
83 | <reg name="v24" bitsize="1024" offset="3328" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="112"/> | |
84 | <reg name="v25" bitsize="1024" offset="3456" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="113"/> | |
85 | <reg name="v26" bitsize="1024" offset="3584" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="114"/> | |
86 | <reg name="v27" bitsize="1024" offset="3712" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="115"/> | |
87 | <reg name="v28" bitsize="1024" offset="3840" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="116"/> | |
88 | <reg name="v29" bitsize="1024" offset="3968" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="117"/> | |
89 | <reg name="v30" bitsize="1024" offset="4096" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="118"/> | |
90 | <reg name="v31" bitsize="1024" offset="4224" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="119"/> | |
91 | <reg name="q0" bitsize="128" offset="4352" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="120"/> | |
92 | <reg name="q1" bitsize="128" offset="4368" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="121"/> | |
93 | <reg name="q2" bitsize="128" offset="4384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="122"/> | |
94 | <reg name="q3" bitsize="128" offset="4400" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="123"/> | |
95 | ||
96 | </feature> |