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b4608c04
FB
1/*
2 * gdb server stub
3 *
3475187d 4 * Copyright (c) 2003-2005 Fabrice Bellard
b4608c04
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
978efd6a 20#include "config.h"
1fddef4b
FB
21#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
978efd6a 28#include <fcntl.h>
1fddef4b
FB
29
30#include "qemu.h"
31#else
67b915a5 32#include "vl.h"
1fddef4b 33#endif
67b915a5 34
8f447cc7
FB
35#include "qemu_socket.h"
36#ifdef _WIN32
37/* XXX: these constants may be independent of the host ones even for Unix */
38#ifndef SIGTRAP
39#define SIGTRAP 5
40#endif
41#ifndef SIGINT
42#define SIGINT 2
43#endif
44#else
b4608c04 45#include <signal.h>
8f447cc7 46#endif
b4608c04 47
4abe615b 48//#define DEBUG_GDB
b4608c04 49
858693c6
FB
50enum RSState {
51 RS_IDLE,
52 RS_GETLINE,
53 RS_CHKSUM1,
54 RS_CHKSUM2,
55};
858693c6 56typedef struct GDBState {
6a00d601 57 CPUState *env; /* current CPU */
41625033 58 enum RSState state; /* parsing state */
858693c6
FB
59 char line_buf[4096];
60 int line_buf_index;
61 int line_csum;
4046d913
PB
62 char last_packet[4100];
63 int last_packet_len;
41625033 64#ifdef CONFIG_USER_ONLY
4046d913 65 int fd;
41625033 66 int running_state;
4046d913
PB
67#else
68 CharDriverState *chr;
41625033 69#endif
858693c6 70} GDBState;
b4608c04 71
1fddef4b 72#ifdef CONFIG_USER_ONLY
4046d913
PB
73/* XXX: This is not thread safe. Do we care? */
74static int gdbserver_fd = -1;
75
1fddef4b
FB
76/* XXX: remove this hack. */
77static GDBState gdbserver_state;
1fddef4b 78
858693c6 79static int get_char(GDBState *s)
b4608c04
FB
80{
81 uint8_t ch;
82 int ret;
83
84 for(;;) {
8f447cc7 85 ret = recv(s->fd, &ch, 1, 0);
b4608c04
FB
86 if (ret < 0) {
87 if (errno != EINTR && errno != EAGAIN)
88 return -1;
89 } else if (ret == 0) {
90 return -1;
91 } else {
92 break;
93 }
94 }
95 return ch;
96}
4046d913 97#endif
b4608c04 98
858693c6 99static void put_buffer(GDBState *s, const uint8_t *buf, int len)
b4608c04 100{
4046d913 101#ifdef CONFIG_USER_ONLY
b4608c04
FB
102 int ret;
103
104 while (len > 0) {
8f447cc7 105 ret = send(s->fd, buf, len, 0);
b4608c04
FB
106 if (ret < 0) {
107 if (errno != EINTR && errno != EAGAIN)
108 return;
109 } else {
110 buf += ret;
111 len -= ret;
112 }
113 }
4046d913
PB
114#else
115 qemu_chr_write(s->chr, buf, len);
116#endif
b4608c04
FB
117}
118
119static inline int fromhex(int v)
120{
121 if (v >= '0' && v <= '9')
122 return v - '0';
123 else if (v >= 'A' && v <= 'F')
124 return v - 'A' + 10;
125 else if (v >= 'a' && v <= 'f')
126 return v - 'a' + 10;
127 else
128 return 0;
129}
130
131static inline int tohex(int v)
132{
133 if (v < 10)
134 return v + '0';
135 else
136 return v - 10 + 'a';
137}
138
139static void memtohex(char *buf, const uint8_t *mem, int len)
140{
141 int i, c;
142 char *q;
143 q = buf;
144 for(i = 0; i < len; i++) {
145 c = mem[i];
146 *q++ = tohex(c >> 4);
147 *q++ = tohex(c & 0xf);
148 }
149 *q = '\0';
150}
151
152static void hextomem(uint8_t *mem, const char *buf, int len)
153{
154 int i;
155
156 for(i = 0; i < len; i++) {
157 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
158 buf += 2;
159 }
160}
161
b4608c04 162/* return -1 if error, 0 if OK */
858693c6 163static int put_packet(GDBState *s, char *buf)
b4608c04 164{
4046d913
PB
165 int len, csum, i;
166 char *p;
b4608c04
FB
167
168#ifdef DEBUG_GDB
169 printf("reply='%s'\n", buf);
170#endif
171
172 for(;;) {
4046d913
PB
173 p = s->last_packet;
174 *(p++) = '$';
b4608c04 175 len = strlen(buf);
4046d913
PB
176 memcpy(p, buf, len);
177 p += len;
b4608c04
FB
178 csum = 0;
179 for(i = 0; i < len; i++) {
180 csum += buf[i];
181 }
4046d913
PB
182 *(p++) = '#';
183 *(p++) = tohex((csum >> 4) & 0xf);
184 *(p++) = tohex((csum) & 0xf);
b4608c04 185
4046d913
PB
186 s->last_packet_len = p - s->last_packet;
187 put_buffer(s, s->last_packet, s->last_packet_len);
b4608c04 188
4046d913
PB
189#ifdef CONFIG_USER_ONLY
190 i = get_char(s);
191 if (i < 0)
b4608c04 192 return -1;
4046d913 193 if (i == '+')
b4608c04 194 break;
4046d913
PB
195#else
196 break;
197#endif
b4608c04
FB
198 }
199 return 0;
200}
201
6da41eaf
FB
202#if defined(TARGET_I386)
203
6da41eaf
FB
204static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
205{
e95c8d51 206 uint32_t *registers = (uint32_t *)mem_buf;
6da41eaf
FB
207 int i, fpus;
208
209 for(i = 0; i < 8; i++) {
e95c8d51 210 registers[i] = env->regs[i];
6da41eaf 211 }
e95c8d51
FB
212 registers[8] = env->eip;
213 registers[9] = env->eflags;
214 registers[10] = env->segs[R_CS].selector;
215 registers[11] = env->segs[R_SS].selector;
216 registers[12] = env->segs[R_DS].selector;
217 registers[13] = env->segs[R_ES].selector;
218 registers[14] = env->segs[R_FS].selector;
219 registers[15] = env->segs[R_GS].selector;
6da41eaf
FB
220 /* XXX: convert floats */
221 for(i = 0; i < 8; i++) {
222 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
223 }
e95c8d51 224 registers[36] = env->fpuc;
6da41eaf 225 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
e95c8d51
FB
226 registers[37] = fpus;
227 registers[38] = 0; /* XXX: convert tags */
228 registers[39] = 0; /* fiseg */
229 registers[40] = 0; /* fioff */
230 registers[41] = 0; /* foseg */
231 registers[42] = 0; /* fooff */
232 registers[43] = 0; /* fop */
233
234 for(i = 0; i < 16; i++)
235 tswapls(&registers[i]);
236 for(i = 36; i < 44; i++)
237 tswapls(&registers[i]);
6da41eaf
FB
238 return 44 * 4;
239}
240
241static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
242{
243 uint32_t *registers = (uint32_t *)mem_buf;
244 int i;
245
246 for(i = 0; i < 8; i++) {
247 env->regs[i] = tswapl(registers[i]);
248 }
e95c8d51
FB
249 env->eip = tswapl(registers[8]);
250 env->eflags = tswapl(registers[9]);
6da41eaf
FB
251#if defined(CONFIG_USER_ONLY)
252#define LOAD_SEG(index, sreg)\
253 if (tswapl(registers[index]) != env->segs[sreg].selector)\
254 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
255 LOAD_SEG(10, R_CS);
256 LOAD_SEG(11, R_SS);
257 LOAD_SEG(12, R_DS);
258 LOAD_SEG(13, R_ES);
259 LOAD_SEG(14, R_FS);
260 LOAD_SEG(15, R_GS);
261#endif
262}
263
9e62fd7f 264#elif defined (TARGET_PPC)
9e62fd7f
FB
265static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
266{
a541f297 267 uint32_t *registers = (uint32_t *)mem_buf, tmp;
9e62fd7f
FB
268 int i;
269
270 /* fill in gprs */
a541f297 271 for(i = 0; i < 32; i++) {
e95c8d51 272 registers[i] = tswapl(env->gpr[i]);
9e62fd7f
FB
273 }
274 /* fill in fprs */
275 for (i = 0; i < 32; i++) {
e95c8d51
FB
276 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
277 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
9e62fd7f
FB
278 }
279 /* nip, msr, ccr, lnk, ctr, xer, mq */
e95c8d51 280 registers[96] = tswapl(env->nip);
3fc6c082 281 registers[97] = tswapl(do_load_msr(env));
9e62fd7f
FB
282 tmp = 0;
283 for (i = 0; i < 8; i++)
a541f297 284 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
e95c8d51
FB
285 registers[98] = tswapl(tmp);
286 registers[99] = tswapl(env->lr);
287 registers[100] = tswapl(env->ctr);
3fc6c082 288 registers[101] = tswapl(do_load_xer(env));
e95c8d51 289 registers[102] = 0;
a541f297
FB
290
291 return 103 * 4;
9e62fd7f
FB
292}
293
294static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
295{
296 uint32_t *registers = (uint32_t *)mem_buf;
297 int i;
298
299 /* fill in gprs */
300 for (i = 0; i < 32; i++) {
e95c8d51 301 env->gpr[i] = tswapl(registers[i]);
9e62fd7f
FB
302 }
303 /* fill in fprs */
304 for (i = 0; i < 32; i++) {
e95c8d51
FB
305 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
306 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
9e62fd7f
FB
307 }
308 /* nip, msr, ccr, lnk, ctr, xer, mq */
e95c8d51 309 env->nip = tswapl(registers[96]);
3fc6c082 310 do_store_msr(env, tswapl(registers[97]));
e95c8d51 311 registers[98] = tswapl(registers[98]);
9e62fd7f 312 for (i = 0; i < 8; i++)
a541f297 313 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
e95c8d51
FB
314 env->lr = tswapl(registers[99]);
315 env->ctr = tswapl(registers[100]);
3fc6c082 316 do_store_xer(env, tswapl(registers[101]));
e95c8d51
FB
317}
318#elif defined (TARGET_SPARC)
319static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
320{
3475187d 321 target_ulong *registers = (target_ulong *)mem_buf;
e95c8d51
FB
322 int i;
323
324 /* fill in g0..g7 */
48b2c193 325 for(i = 0; i < 8; i++) {
e95c8d51
FB
326 registers[i] = tswapl(env->gregs[i]);
327 }
328 /* fill in register window */
329 for(i = 0; i < 24; i++) {
330 registers[i + 8] = tswapl(env->regwptr[i]);
331 }
9d9754a3 332#ifndef TARGET_SPARC64
e95c8d51
FB
333 /* fill in fprs */
334 for (i = 0; i < 32; i++) {
335 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
336 }
337 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
338 registers[64] = tswapl(env->y);
3475187d
FB
339 {
340 target_ulong tmp;
341
342 tmp = GET_PSR(env);
343 registers[65] = tswapl(tmp);
344 }
e95c8d51
FB
345 registers[66] = tswapl(env->wim);
346 registers[67] = tswapl(env->tbr);
347 registers[68] = tswapl(env->pc);
348 registers[69] = tswapl(env->npc);
349 registers[70] = tswapl(env->fsr);
350 registers[71] = 0; /* csr */
351 registers[72] = 0;
3475187d
FB
352 return 73 * sizeof(target_ulong);
353#else
9d9754a3
FB
354 /* fill in fprs */
355 for (i = 0; i < 64; i += 2) {
356 uint64_t tmp;
357
358 tmp = (uint64_t)tswap32(*((uint32_t *)&env->fpr[i])) << 32;
359 tmp |= tswap32(*((uint32_t *)&env->fpr[i + 1]));
360 registers[i/2 + 32] = tmp;
3475187d 361 }
9d9754a3
FB
362 registers[64] = tswapl(env->pc);
363 registers[65] = tswapl(env->npc);
364 registers[66] = tswapl(env->tstate[env->tl]);
365 registers[67] = tswapl(env->fsr);
366 registers[68] = tswapl(env->fprs);
367 registers[69] = tswapl(env->y);
368 return 70 * sizeof(target_ulong);
3475187d 369#endif
e95c8d51
FB
370}
371
372static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
373{
3475187d 374 target_ulong *registers = (target_ulong *)mem_buf;
e95c8d51
FB
375 int i;
376
377 /* fill in g0..g7 */
378 for(i = 0; i < 7; i++) {
379 env->gregs[i] = tswapl(registers[i]);
380 }
381 /* fill in register window */
382 for(i = 0; i < 24; i++) {
3475187d 383 env->regwptr[i] = tswapl(registers[i + 8]);
e95c8d51 384 }
9d9754a3 385#ifndef TARGET_SPARC64
e95c8d51
FB
386 /* fill in fprs */
387 for (i = 0; i < 32; i++) {
388 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
389 }
390 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
391 env->y = tswapl(registers[64]);
e80cfcfc 392 PUT_PSR(env, tswapl(registers[65]));
e95c8d51
FB
393 env->wim = tswapl(registers[66]);
394 env->tbr = tswapl(registers[67]);
395 env->pc = tswapl(registers[68]);
396 env->npc = tswapl(registers[69]);
397 env->fsr = tswapl(registers[70]);
3475187d 398#else
9d9754a3
FB
399 for (i = 0; i < 64; i += 2) {
400 *((uint32_t *)&env->fpr[i]) = tswap32(registers[i/2 + 32] >> 32);
401 *((uint32_t *)&env->fpr[i + 1]) = tswap32(registers[i/2 + 32] & 0xffffffff);
3475187d 402 }
9d9754a3
FB
403 env->pc = tswapl(registers[64]);
404 env->npc = tswapl(registers[65]);
405 env->tstate[env->tl] = tswapl(registers[66]);
406 env->fsr = tswapl(registers[67]);
407 env->fprs = tswapl(registers[68]);
408 env->y = tswapl(registers[69]);
3475187d 409#endif
9e62fd7f 410}
1fddef4b
FB
411#elif defined (TARGET_ARM)
412static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
413{
414 int i;
415 uint8_t *ptr;
416
417 ptr = mem_buf;
418 /* 16 core integer registers (4 bytes each). */
419 for (i = 0; i < 16; i++)
420 {
421 *(uint32_t *)ptr = tswapl(env->regs[i]);
422 ptr += 4;
423 }
424 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
425 Not yet implemented. */
426 memset (ptr, 0, 8 * 12 + 4);
427 ptr += 8 * 12 + 4;
428 /* CPSR (4 bytes). */
b5ff1b31 429 *(uint32_t *)ptr = tswapl (cpsr_read(env));
1fddef4b
FB
430 ptr += 4;
431
432 return ptr - mem_buf;
433}
6da41eaf 434
1fddef4b
FB
435static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
436{
437 int i;
438 uint8_t *ptr;
439
440 ptr = mem_buf;
441 /* Core integer registers. */
442 for (i = 0; i < 16; i++)
443 {
444 env->regs[i] = tswapl(*(uint32_t *)ptr);
445 ptr += 4;
446 }
447 /* Ignore FPA regs and scr. */
448 ptr += 8 * 12 + 4;
b5ff1b31 449 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
1fddef4b 450}
e6e5906b
PB
451#elif defined (TARGET_M68K)
452static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
453{
454 int i;
455 uint8_t *ptr;
456 CPU_DoubleU u;
457
458 ptr = mem_buf;
459 /* D0-D7 */
460 for (i = 0; i < 8; i++) {
461 *(uint32_t *)ptr = tswapl(env->dregs[i]);
462 ptr += 4;
463 }
464 /* A0-A7 */
465 for (i = 0; i < 8; i++) {
466 *(uint32_t *)ptr = tswapl(env->aregs[i]);
467 ptr += 4;
468 }
469 *(uint32_t *)ptr = tswapl(env->sr);
470 ptr += 4;
471 *(uint32_t *)ptr = tswapl(env->pc);
472 ptr += 4;
473 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
474 ColdFire has 8-bit double precision registers. */
475 for (i = 0; i < 8; i++) {
476 u.d = env->fregs[i];
477 *(uint32_t *)ptr = tswap32(u.l.upper);
478 *(uint32_t *)ptr = tswap32(u.l.lower);
479 }
480 /* FP control regs (not implemented). */
481 memset (ptr, 0, 3 * 4);
482 ptr += 3 * 4;
483
484 return ptr - mem_buf;
485}
486
487static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
488{
489 int i;
490 uint8_t *ptr;
491 CPU_DoubleU u;
492
493 ptr = mem_buf;
494 /* D0-D7 */
495 for (i = 0; i < 8; i++) {
496 env->dregs[i] = tswapl(*(uint32_t *)ptr);
497 ptr += 4;
498 }
499 /* A0-A7 */
500 for (i = 0; i < 8; i++) {
501 env->aregs[i] = tswapl(*(uint32_t *)ptr);
502 ptr += 4;
503 }
504 env->sr = tswapl(*(uint32_t *)ptr);
505 ptr += 4;
506 env->pc = tswapl(*(uint32_t *)ptr);
507 ptr += 4;
508 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
509 ColdFire has 8-bit double precision registers. */
510 for (i = 0; i < 8; i++) {
511 u.l.upper = tswap32(*(uint32_t *)ptr);
512 u.l.lower = tswap32(*(uint32_t *)ptr);
513 env->fregs[i] = u.d;
514 }
515 /* FP control regs (not implemented). */
516 ptr += 3 * 4;
517}
6f970bd9
FB
518#elif defined (TARGET_MIPS)
519static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
520{
521 int i;
522 uint8_t *ptr;
523
524 ptr = mem_buf;
525 for (i = 0; i < 32; i++)
526 {
527 *(uint32_t *)ptr = tswapl(env->gpr[i]);
528 ptr += 4;
529 }
530
531 *(uint32_t *)ptr = tswapl(env->CP0_Status);
532 ptr += 4;
533
534 *(uint32_t *)ptr = tswapl(env->LO);
535 ptr += 4;
536
537 *(uint32_t *)ptr = tswapl(env->HI);
538 ptr += 4;
539
540 *(uint32_t *)ptr = tswapl(env->CP0_BadVAddr);
541 ptr += 4;
542
543 *(uint32_t *)ptr = tswapl(env->CP0_Cause);
544 ptr += 4;
545
546 *(uint32_t *)ptr = tswapl(env->PC);
547 ptr += 4;
548
8e33c08c
TS
549#ifdef MIPS_USES_FPU
550 for (i = 0; i < 32; i++)
551 {
552 *(uint32_t *)ptr = tswapl(FPR_W (env, i));
553 ptr += 4;
554 }
555
556 *(uint32_t *)ptr = tswapl(env->fcr31);
557 ptr += 4;
558
559 *(uint32_t *)ptr = tswapl(env->fcr0);
560 ptr += 4;
561#endif
562
6f970bd9 563 /* 32 FP registers, fsr, fir, fp. Not yet implemented. */
8e33c08c 564 /* what's 'fp' mean here? */
6f970bd9
FB
565
566 return ptr - mem_buf;
567}
568
8e33c08c
TS
569/* convert MIPS rounding mode in FCR31 to IEEE library */
570static unsigned int ieee_rm[] =
571 {
572 float_round_nearest_even,
573 float_round_to_zero,
574 float_round_up,
575 float_round_down
576 };
577#define RESTORE_ROUNDING_MODE \
578 set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
579
6f970bd9
FB
580static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
581{
582 int i;
583 uint8_t *ptr;
584
585 ptr = mem_buf;
586 for (i = 0; i < 32; i++)
587 {
588 env->gpr[i] = tswapl(*(uint32_t *)ptr);
589 ptr += 4;
590 }
591
592 env->CP0_Status = tswapl(*(uint32_t *)ptr);
593 ptr += 4;
594
595 env->LO = tswapl(*(uint32_t *)ptr);
596 ptr += 4;
597
598 env->HI = tswapl(*(uint32_t *)ptr);
599 ptr += 4;
600
601 env->CP0_BadVAddr = tswapl(*(uint32_t *)ptr);
602 ptr += 4;
603
604 env->CP0_Cause = tswapl(*(uint32_t *)ptr);
605 ptr += 4;
606
607 env->PC = tswapl(*(uint32_t *)ptr);
608 ptr += 4;
8e33c08c
TS
609
610#ifdef MIPS_USES_FPU
611 for (i = 0; i < 32; i++)
612 {
613 FPR_W (env, i) = tswapl(*(uint32_t *)ptr);
614 ptr += 4;
615 }
616
617 env->fcr31 = tswapl(*(uint32_t *)ptr) & 0x0183FFFF;
618 ptr += 4;
619
620 env->fcr0 = tswapl(*(uint32_t *)ptr);
621 ptr += 4;
622
623 /* set rounding mode */
624 RESTORE_ROUNDING_MODE;
625
626#ifndef CONFIG_SOFTFLOAT
627 /* no floating point exception for native float */
628 SET_FP_ENABLE(env->fcr31, 0);
629#endif
630#endif
6f970bd9 631}
fdf9b3e8
FB
632#elif defined (TARGET_SH4)
633static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
634{
635 uint32_t *ptr = (uint32_t *)mem_buf;
636 int i;
637
638#define SAVE(x) *ptr++=tswapl(x)
9c2a9ea1
PB
639 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
640 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
641 } else {
642 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
643 }
644 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
fdf9b3e8
FB
645 SAVE (env->pc);
646 SAVE (env->pr);
647 SAVE (env->gbr);
648 SAVE (env->vbr);
649 SAVE (env->mach);
650 SAVE (env->macl);
651 SAVE (env->sr);
652 SAVE (0); /* TICKS */
653 SAVE (0); /* STALLS */
654 SAVE (0); /* CYCLES */
655 SAVE (0); /* INSTS */
656 SAVE (0); /* PLR */
657
658 return ((uint8_t *)ptr - mem_buf);
659}
660
661static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
662{
663 uint32_t *ptr = (uint32_t *)mem_buf;
664 int i;
665
666#define LOAD(x) (x)=*ptr++;
9c2a9ea1
PB
667 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
668 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
669 } else {
670 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
671 }
672 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
fdf9b3e8
FB
673 LOAD (env->pc);
674 LOAD (env->pr);
675 LOAD (env->gbr);
676 LOAD (env->vbr);
677 LOAD (env->mach);
678 LOAD (env->macl);
679 LOAD (env->sr);
680}
1fddef4b 681#else
6da41eaf
FB
682static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
683{
684 return 0;
685}
686
687static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
688{
689}
690
691#endif
b4608c04 692
1fddef4b 693static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
b4608c04 694{
b4608c04 695 const char *p;
858693c6 696 int ch, reg_size, type;
b4608c04
FB
697 char buf[4096];
698 uint8_t mem_buf[2000];
699 uint32_t *registers;
9d9754a3 700 target_ulong addr, len;
b4608c04 701
858693c6
FB
702#ifdef DEBUG_GDB
703 printf("command='%s'\n", line_buf);
704#endif
705 p = line_buf;
706 ch = *p++;
707 switch(ch) {
708 case '?':
1fddef4b 709 /* TODO: Make this return the correct value for user-mode. */
858693c6
FB
710 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
711 put_packet(s, buf);
712 break;
713 case 'c':
714 if (*p != '\0') {
9d9754a3 715 addr = strtoull(p, (char **)&p, 16);
4c3a88a2 716#if defined(TARGET_I386)
858693c6 717 env->eip = addr;
5be1a8e0 718#elif defined (TARGET_PPC)
858693c6 719 env->nip = addr;
8d5f07fa
FB
720#elif defined (TARGET_SPARC)
721 env->pc = addr;
722 env->npc = addr + 4;
b5ff1b31
FB
723#elif defined (TARGET_ARM)
724 env->regs[15] = addr;
fdf9b3e8
FB
725#elif defined (TARGET_SH4)
726 env->pc = addr;
4c3a88a2 727#endif
858693c6 728 }
41625033
FB
729#ifdef CONFIG_USER_ONLY
730 s->running_state = 1;
731#else
732 vm_start();
733#endif
734 return RS_IDLE;
858693c6
FB
735 case 's':
736 if (*p != '\0') {
737 addr = strtoul(p, (char **)&p, 16);
c33a346e 738#if defined(TARGET_I386)
858693c6 739 env->eip = addr;
5be1a8e0 740#elif defined (TARGET_PPC)
858693c6 741 env->nip = addr;
8d5f07fa
FB
742#elif defined (TARGET_SPARC)
743 env->pc = addr;
744 env->npc = addr + 4;
b5ff1b31
FB
745#elif defined (TARGET_ARM)
746 env->regs[15] = addr;
fdf9b3e8
FB
747#elif defined (TARGET_SH4)
748 env->pc = addr;
c33a346e 749#endif
858693c6
FB
750 }
751 cpu_single_step(env, 1);
41625033
FB
752#ifdef CONFIG_USER_ONLY
753 s->running_state = 1;
754#else
755 vm_start();
756#endif
757 return RS_IDLE;
858693c6
FB
758 case 'g':
759 reg_size = cpu_gdb_read_registers(env, mem_buf);
760 memtohex(buf, mem_buf, reg_size);
761 put_packet(s, buf);
762 break;
763 case 'G':
764 registers = (void *)mem_buf;
765 len = strlen(p) / 2;
766 hextomem((uint8_t *)registers, p, len);
767 cpu_gdb_write_registers(env, mem_buf, len);
768 put_packet(s, "OK");
769 break;
770 case 'm':
9d9754a3 771 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
772 if (*p == ',')
773 p++;
9d9754a3 774 len = strtoull(p, NULL, 16);
6f970bd9
FB
775 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
776 put_packet (s, "E14");
777 } else {
778 memtohex(buf, mem_buf, len);
779 put_packet(s, buf);
780 }
858693c6
FB
781 break;
782 case 'M':
9d9754a3 783 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
784 if (*p == ',')
785 p++;
9d9754a3 786 len = strtoull(p, (char **)&p, 16);
b328f873 787 if (*p == ':')
858693c6
FB
788 p++;
789 hextomem(mem_buf, p, len);
790 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
905f20b1 791 put_packet(s, "E14");
858693c6
FB
792 else
793 put_packet(s, "OK");
794 break;
795 case 'Z':
796 type = strtoul(p, (char **)&p, 16);
797 if (*p == ',')
798 p++;
9d9754a3 799 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
800 if (*p == ',')
801 p++;
9d9754a3 802 len = strtoull(p, (char **)&p, 16);
858693c6
FB
803 if (type == 0 || type == 1) {
804 if (cpu_breakpoint_insert(env, addr) < 0)
805 goto breakpoint_error;
806 put_packet(s, "OK");
807 } else {
808 breakpoint_error:
905f20b1 809 put_packet(s, "E22");
858693c6
FB
810 }
811 break;
812 case 'z':
813 type = strtoul(p, (char **)&p, 16);
814 if (*p == ',')
815 p++;
9d9754a3 816 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
817 if (*p == ',')
818 p++;
9d9754a3 819 len = strtoull(p, (char **)&p, 16);
858693c6
FB
820 if (type == 0 || type == 1) {
821 cpu_breakpoint_remove(env, addr);
822 put_packet(s, "OK");
823 } else {
824 goto breakpoint_error;
825 }
826 break;
831b7825 827#ifdef CONFIG_LINUX_USER
978efd6a
PB
828 case 'q':
829 if (strncmp(p, "Offsets", 7) == 0) {
830 TaskState *ts = env->opaque;
831
832 sprintf(buf, "Text=%x;Data=%x;Bss=%x", ts->info->code_offset,
833 ts->info->data_offset, ts->info->data_offset);
834 put_packet(s, buf);
835 break;
836 }
837 /* Fall through. */
838#endif
858693c6
FB
839 default:
840 // unknown_command:
841 /* put empty packet */
842 buf[0] = '\0';
843 put_packet(s, buf);
844 break;
845 }
846 return RS_IDLE;
847}
848
612458f5
FB
849extern void tb_flush(CPUState *env);
850
1fddef4b 851#ifndef CONFIG_USER_ONLY
858693c6
FB
852static void gdb_vm_stopped(void *opaque, int reason)
853{
854 GDBState *s = opaque;
855 char buf[256];
856 int ret;
857
858 /* disable single step if it was enable */
6a00d601 859 cpu_single_step(s->env, 0);
858693c6 860
e80cfcfc 861 if (reason == EXCP_DEBUG) {
6a00d601 862 tb_flush(s->env);
858693c6 863 ret = SIGTRAP;
bbeb7b5c
FB
864 } else if (reason == EXCP_INTERRUPT) {
865 ret = SIGINT;
866 } else {
858693c6 867 ret = 0;
bbeb7b5c 868 }
858693c6
FB
869 snprintf(buf, sizeof(buf), "S%02x", ret);
870 put_packet(s, buf);
871}
1fddef4b 872#endif
858693c6 873
6a00d601 874static void gdb_read_byte(GDBState *s, int ch)
858693c6 875{
6a00d601 876 CPUState *env = s->env;
858693c6
FB
877 int i, csum;
878 char reply[1];
879
1fddef4b 880#ifndef CONFIG_USER_ONLY
4046d913
PB
881 if (s->last_packet_len) {
882 /* Waiting for a response to the last packet. If we see the start
883 of a new command then abandon the previous response. */
884 if (ch == '-') {
885#ifdef DEBUG_GDB
886 printf("Got NACK, retransmitting\n");
887#endif
888 put_buffer(s, s->last_packet, s->last_packet_len);
889 }
890#ifdef DEBUG_GDB
891 else if (ch == '+')
892 printf("Got ACK\n");
893 else
894 printf("Got '%c' when expecting ACK/NACK\n", ch);
895#endif
896 if (ch == '+' || ch == '$')
897 s->last_packet_len = 0;
898 if (ch != '$')
899 return;
900 }
858693c6
FB
901 if (vm_running) {
902 /* when the CPU is running, we cannot do anything except stop
903 it when receiving a char */
904 vm_stop(EXCP_INTERRUPT);
41625033 905 } else
1fddef4b 906#endif
41625033 907 {
858693c6
FB
908 switch(s->state) {
909 case RS_IDLE:
910 if (ch == '$') {
911 s->line_buf_index = 0;
912 s->state = RS_GETLINE;
c33a346e 913 }
b4608c04 914 break;
858693c6
FB
915 case RS_GETLINE:
916 if (ch == '#') {
917 s->state = RS_CHKSUM1;
918 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
919 s->state = RS_IDLE;
4c3a88a2 920 } else {
858693c6 921 s->line_buf[s->line_buf_index++] = ch;
4c3a88a2
FB
922 }
923 break;
858693c6
FB
924 case RS_CHKSUM1:
925 s->line_buf[s->line_buf_index] = '\0';
926 s->line_csum = fromhex(ch) << 4;
927 s->state = RS_CHKSUM2;
928 break;
929 case RS_CHKSUM2:
930 s->line_csum |= fromhex(ch);
931 csum = 0;
932 for(i = 0; i < s->line_buf_index; i++) {
933 csum += s->line_buf[i];
934 }
935 if (s->line_csum != (csum & 0xff)) {
936 reply[0] = '-';
937 put_buffer(s, reply, 1);
938 s->state = RS_IDLE;
4c3a88a2 939 } else {
858693c6
FB
940 reply[0] = '+';
941 put_buffer(s, reply, 1);
1fddef4b 942 s->state = gdb_handle_packet(s, env, s->line_buf);
4c3a88a2
FB
943 }
944 break;
858693c6
FB
945 }
946 }
947}
948
1fddef4b
FB
949#ifdef CONFIG_USER_ONLY
950int
951gdb_handlesig (CPUState *env, int sig)
952{
953 GDBState *s;
954 char buf[256];
955 int n;
956
957 if (gdbserver_fd < 0)
958 return sig;
959
960 s = &gdbserver_state;
961
962 /* disable single step if it was enabled */
963 cpu_single_step(env, 0);
964 tb_flush(env);
965
966 if (sig != 0)
967 {
968 snprintf(buf, sizeof(buf), "S%02x", sig);
969 put_packet(s, buf);
970 }
971
1fddef4b
FB
972 sig = 0;
973 s->state = RS_IDLE;
41625033
FB
974 s->running_state = 0;
975 while (s->running_state == 0) {
1fddef4b
FB
976 n = read (s->fd, buf, 256);
977 if (n > 0)
978 {
979 int i;
980
981 for (i = 0; i < n; i++)
6a00d601 982 gdb_read_byte (s, buf[i]);
1fddef4b
FB
983 }
984 else if (n == 0 || errno != EAGAIN)
985 {
986 /* XXX: Connection closed. Should probably wait for annother
987 connection before continuing. */
988 return sig;
989 }
41625033 990 }
1fddef4b
FB
991 return sig;
992}
e9009676
FB
993
994/* Tell the remote gdb that the process has exited. */
995void gdb_exit(CPUState *env, int code)
996{
997 GDBState *s;
998 char buf[4];
999
1000 if (gdbserver_fd < 0)
1001 return;
1002
1003 s = &gdbserver_state;
1004
1005 snprintf(buf, sizeof(buf), "W%02x", code);
1006 put_packet(s, buf);
1007}
1008
1fddef4b 1009
7c9d8e07 1010static void gdb_accept(void *opaque)
858693c6
FB
1011{
1012 GDBState *s;
1013 struct sockaddr_in sockaddr;
1014 socklen_t len;
1015 int val, fd;
1016
1017 for(;;) {
1018 len = sizeof(sockaddr);
1019 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1020 if (fd < 0 && errno != EINTR) {
1021 perror("accept");
1022 return;
1023 } else if (fd >= 0) {
b4608c04
FB
1024 break;
1025 }
1026 }
858693c6
FB
1027
1028 /* set short latency */
1029 val = 1;
8f447cc7 1030 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
858693c6 1031
1fddef4b
FB
1032 s = &gdbserver_state;
1033 memset (s, 0, sizeof (GDBState));
6a00d601 1034 s->env = first_cpu; /* XXX: allow to change CPU */
858693c6
FB
1035 s->fd = fd;
1036
1037 fcntl(fd, F_SETFL, O_NONBLOCK);
858693c6
FB
1038}
1039
1040static int gdbserver_open(int port)
1041{
1042 struct sockaddr_in sockaddr;
1043 int fd, val, ret;
1044
1045 fd = socket(PF_INET, SOCK_STREAM, 0);
1046 if (fd < 0) {
1047 perror("socket");
1048 return -1;
1049 }
1050
1051 /* allow fast reuse */
1052 val = 1;
8f447cc7 1053 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
858693c6
FB
1054
1055 sockaddr.sin_family = AF_INET;
1056 sockaddr.sin_port = htons(port);
1057 sockaddr.sin_addr.s_addr = 0;
1058 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1059 if (ret < 0) {
1060 perror("bind");
1061 return -1;
1062 }
1063 ret = listen(fd, 0);
1064 if (ret < 0) {
1065 perror("listen");
1066 return -1;
1067 }
858693c6
FB
1068 return fd;
1069}
1070
1071int gdbserver_start(int port)
1072{
1073 gdbserver_fd = gdbserver_open(port);
1074 if (gdbserver_fd < 0)
1075 return -1;
1076 /* accept connections */
7c9d8e07 1077 gdb_accept (NULL);
4046d913
PB
1078 return 0;
1079}
1fddef4b 1080#else
4046d913
PB
1081static int gdb_chr_can_recieve(void *opaque)
1082{
1083 return 1;
1084}
1085
1086static void gdb_chr_recieve(void *opaque, const uint8_t *buf, int size)
1087{
1088 GDBState *s = opaque;
1089 int i;
1090
1091 for (i = 0; i < size; i++) {
1092 gdb_read_byte(s, buf[i]);
1093 }
1094}
1095
1096static void gdb_chr_event(void *opaque, int event)
1097{
1098 switch (event) {
1099 case CHR_EVENT_RESET:
1100 vm_stop(EXCP_INTERRUPT);
1101 break;
1102 default:
1103 break;
1104 }
1105}
1106
1107int gdbserver_start(CharDriverState *chr)
1108{
1109 GDBState *s;
1110
1111 if (!chr)
1112 return -1;
1113
1114 s = qemu_mallocz(sizeof(GDBState));
1115 if (!s) {
1116 return -1;
1117 }
1118 s->env = first_cpu; /* XXX: allow to change CPU */
1119 s->chr = chr;
1120 qemu_chr_add_handlers(chr, gdb_chr_can_recieve, gdb_chr_recieve,
1121 gdb_chr_event, s);
1122 qemu_add_vm_stop_handler(gdb_vm_stopped, s);
b4608c04
FB
1123 return 0;
1124}
4046d913 1125#endif