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81cea5e7 IM |
1 | /* |
2 | * QEMU ACPI hotplug utilities | |
3 | * | |
4 | * Copyright (C) 2013 Red Hat Inc | |
5 | * | |
6 | * Authors: | |
7 | * Igor Mammedov <imammedo@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
b6a0aa05 | 12 | #include "qemu/osdep.h" |
81cea5e7 | 13 | #include "hw/acpi/cpu_hotplug.h" |
da34e65c | 14 | #include "qapi/error.h" |
2e5b09fd | 15 | #include "hw/core/cpu.h" |
672a2872 | 16 | #include "hw/i386/pc.h" |
38e131d2 | 17 | #include "hw/pci/pci.h" |
6a91cf04 | 18 | #include "qemu/error-report.h" |
672a2872 IM |
19 | |
20 | #define CPU_EJECT_METHOD "CPEJ" | |
21 | #define CPU_MAT_METHOD "CPMA" | |
22 | #define CPU_ON_BITMAP "CPON" | |
23 | #define CPU_STATUS_METHOD "CPST" | |
24 | #define CPU_STATUS_MAP "PRS" | |
25 | #define CPU_SCAN_METHOD "PRSC" | |
81cea5e7 IM |
26 | |
27 | static uint64_t cpu_status_read(void *opaque, hwaddr addr, unsigned int size) | |
28 | { | |
29 | AcpiCpuHotplug *cpus = opaque; | |
30 | uint64_t val = cpus->sts[addr]; | |
31 | ||
32 | return val; | |
33 | } | |
34 | ||
35 | static void cpu_status_write(void *opaque, hwaddr addr, uint64_t data, | |
36 | unsigned int size) | |
37 | { | |
679dd1a9 IM |
38 | /* firmware never used to write in CPU present bitmap so use |
39 | this fact as means to switch QEMU into modern CPU hotplug | |
40 | mode by writing 0 at the beginning of legacy CPU bitmap | |
41 | */ | |
42 | if (addr == 0 && data == 0) { | |
43 | AcpiCpuHotplug *cpus = opaque; | |
5325cc34 | 44 | object_property_set_bool(cpus->device, "cpu-hotplug-legacy", false, |
679dd1a9 IM |
45 | &error_abort); |
46 | } | |
81cea5e7 IM |
47 | } |
48 | ||
49 | static const MemoryRegionOps AcpiCpuHotplug_ops = { | |
50 | .read = cpu_status_read, | |
51 | .write = cpu_status_write, | |
52 | .endianness = DEVICE_LITTLE_ENDIAN, | |
53 | .valid = { | |
54 | .min_access_size = 1, | |
55 | .max_access_size = 1, | |
56 | }, | |
57 | }; | |
58 | ||
49e3e11f | 59 | static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, CPUState *cpu) |
1be6b511 | 60 | { |
1be6b511 GZ |
61 | CPUClass *k = CPU_GET_CLASS(cpu); |
62 | int64_t cpu_id; | |
63 | ||
64 | cpu_id = k->get_arch_id(cpu); | |
65 | if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) { | |
5325cc34 | 66 | object_property_set_bool(g->device, "cpu-hotplug-legacy", false, |
f9dc175d | 67 | &error_abort); |
1be6b511 GZ |
68 | return; |
69 | } | |
70 | ||
08bba95b | 71 | g->sts[cpu_id / 8] |= (1 << (cpu_id % 8)); |
cc43364d GZ |
72 | } |
73 | ||
0058c082 | 74 | void legacy_acpi_cpu_plug_cb(HotplugHandler *hotplug_dev, |
96e3e12b | 75 | AcpiCpuHotplug *g, DeviceState *dev, Error **errp) |
cc43364d | 76 | { |
49e3e11f | 77 | acpi_set_cpu_present_bit(g, CPU(dev)); |
0058c082 | 78 | acpi_send_event(DEVICE(hotplug_dev), ACPI_CPU_HOTPLUG_STATUS); |
1be6b511 GZ |
79 | } |
80 | ||
96e3e12b IM |
81 | void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner, |
82 | AcpiCpuHotplug *gpe_cpu, uint16_t base) | |
81cea5e7 IM |
83 | { |
84 | CPUState *cpu; | |
85 | ||
81cea5e7 IM |
86 | memory_region_init_io(&gpe_cpu->io, owner, &AcpiCpuHotplug_ops, |
87 | gpe_cpu, "acpi-cpu-hotplug", ACPI_GPE_PROC_LEN); | |
88 | memory_region_add_subregion(parent, base, &gpe_cpu->io); | |
679dd1a9 | 89 | gpe_cpu->device = owner; |
f9dc175d IM |
90 | |
91 | CPU_FOREACH(cpu) { | |
49e3e11f | 92 | acpi_set_cpu_present_bit(gpe_cpu, cpu); |
f9dc175d | 93 | } |
679dd1a9 IM |
94 | } |
95 | ||
96 | void acpi_switch_to_modern_cphp(AcpiCpuHotplug *gpe_cpu, | |
97 | CPUHotplugState *cpuhp_state, | |
98 | uint16_t io_port) | |
99 | { | |
100 | MemoryRegion *parent = pci_address_space_io(PCI_DEVICE(gpe_cpu->device)); | |
101 | ||
102 | memory_region_del_subregion(parent, &gpe_cpu->io); | |
103 | cpu_hotplug_hw_init(parent, gpe_cpu->device, cpuhp_state, io_port); | |
81cea5e7 | 104 | } |
672a2872 IM |
105 | |
106 | void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine, | |
ebd8ea82 | 107 | uint16_t io_base) |
672a2872 IM |
108 | { |
109 | Aml *dev; | |
110 | Aml *crs; | |
111 | Aml *pkg; | |
112 | Aml *field; | |
113 | Aml *method; | |
114 | Aml *if_ctx; | |
115 | Aml *else_ctx; | |
116 | int i, apic_idx; | |
117 | Aml *sb_scope = aml_scope("_SB"); | |
118 | uint8_t madt_tmpl[8] = {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}; | |
76bdd24e IM |
119 | Aml *cpu_id = aml_arg(1); |
120 | Aml *apic_id = aml_arg(0); | |
672a2872 IM |
121 | Aml *cpu_on = aml_local(0); |
122 | Aml *madt = aml_local(1); | |
123 | Aml *cpus_map = aml_name(CPU_ON_BITMAP); | |
124 | Aml *zero = aml_int(0); | |
125 | Aml *one = aml_int(1); | |
126 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
80e5db30 | 127 | const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); |
f0bb276b | 128 | X86MachineState *x86ms = X86_MACHINE(machine); |
672a2872 IM |
129 | |
130 | /* | |
131 | * _MAT method - creates an madt apic buffer | |
76bdd24e IM |
132 | * apic_id = Arg0 = Local APIC ID |
133 | * cpu_id = Arg1 = Processor ID | |
672a2872 IM |
134 | * cpu_on = Local0 = CPON flag for this cpu |
135 | * madt = Local1 = Buffer (in madt apic form) to return | |
136 | */ | |
76bdd24e | 137 | method = aml_method(CPU_MAT_METHOD, 2, AML_NOTSERIALIZED); |
672a2872 | 138 | aml_append(method, |
76bdd24e | 139 | aml_store(aml_derefof(aml_index(cpus_map, apic_id)), cpu_on)); |
672a2872 IM |
140 | aml_append(method, |
141 | aml_store(aml_buffer(sizeof(madt_tmpl), madt_tmpl), madt)); | |
142 | /* Update the processor id, lapic id, and enable/disable status */ | |
143 | aml_append(method, aml_store(cpu_id, aml_index(madt, aml_int(2)))); | |
76bdd24e | 144 | aml_append(method, aml_store(apic_id, aml_index(madt, aml_int(3)))); |
672a2872 IM |
145 | aml_append(method, aml_store(cpu_on, aml_index(madt, aml_int(4)))); |
146 | aml_append(method, aml_return(madt)); | |
147 | aml_append(sb_scope, method); | |
148 | ||
149 | /* | |
150 | * _STA method - return ON status of cpu | |
76bdd24e | 151 | * apic_id = Arg0 = Local APIC ID |
672a2872 IM |
152 | * cpu_on = Local0 = CPON flag for this cpu |
153 | */ | |
154 | method = aml_method(CPU_STATUS_METHOD, 1, AML_NOTSERIALIZED); | |
155 | aml_append(method, | |
76bdd24e | 156 | aml_store(aml_derefof(aml_index(cpus_map, apic_id)), cpu_on)); |
672a2872 IM |
157 | if_ctx = aml_if(cpu_on); |
158 | { | |
159 | aml_append(if_ctx, aml_return(aml_int(0xF))); | |
160 | } | |
161 | aml_append(method, if_ctx); | |
162 | else_ctx = aml_else(); | |
163 | { | |
164 | aml_append(else_ctx, aml_return(zero)); | |
165 | } | |
166 | aml_append(method, else_ctx); | |
167 | aml_append(sb_scope, method); | |
168 | ||
169 | method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED); | |
170 | aml_append(method, aml_sleep(200)); | |
171 | aml_append(sb_scope, method); | |
172 | ||
173 | method = aml_method(CPU_SCAN_METHOD, 0, AML_NOTSERIALIZED); | |
174 | { | |
175 | Aml *while_ctx, *if_ctx2, *else_ctx2; | |
176 | Aml *bus_check_evt = aml_int(1); | |
177 | Aml *remove_evt = aml_int(3); | |
178 | Aml *status_map = aml_local(5); /* Local5 = active cpu bitmap */ | |
179 | Aml *byte = aml_local(2); /* Local2 = last read byte from bitmap */ | |
180 | Aml *idx = aml_local(0); /* Processor ID / APIC ID iterator */ | |
181 | Aml *is_cpu_on = aml_local(1); /* Local1 = CPON flag for cpu */ | |
182 | Aml *status = aml_local(3); /* Local3 = active state for cpu */ | |
183 | ||
184 | aml_append(method, aml_store(aml_name(CPU_STATUS_MAP), status_map)); | |
185 | aml_append(method, aml_store(zero, byte)); | |
186 | aml_append(method, aml_store(zero, idx)); | |
187 | ||
188 | /* While (idx < SizeOf(CPON)) */ | |
189 | while_ctx = aml_while(aml_lless(idx, aml_sizeof(cpus_map))); | |
190 | aml_append(while_ctx, | |
191 | aml_store(aml_derefof(aml_index(cpus_map, idx)), is_cpu_on)); | |
192 | ||
193 | if_ctx = aml_if(aml_and(idx, aml_int(0x07), NULL)); | |
194 | { | |
195 | /* Shift down previously read bitmap byte */ | |
196 | aml_append(if_ctx, aml_shiftright(byte, one, byte)); | |
197 | } | |
198 | aml_append(while_ctx, if_ctx); | |
199 | ||
200 | else_ctx = aml_else(); | |
201 | { | |
202 | /* Read next byte from cpu bitmap */ | |
203 | aml_append(else_ctx, aml_store(aml_derefof(aml_index(status_map, | |
204 | aml_shiftright(idx, aml_int(3), NULL))), byte)); | |
205 | } | |
206 | aml_append(while_ctx, else_ctx); | |
207 | ||
208 | aml_append(while_ctx, aml_store(aml_and(byte, one, NULL), status)); | |
209 | if_ctx = aml_if(aml_lnot(aml_equal(is_cpu_on, status))); | |
210 | { | |
211 | /* State change - update CPON with new state */ | |
212 | aml_append(if_ctx, aml_store(status, aml_index(cpus_map, idx))); | |
213 | if_ctx2 = aml_if(aml_equal(status, one)); | |
214 | { | |
215 | aml_append(if_ctx2, | |
216 | aml_call2(AML_NOTIFY_METHOD, idx, bus_check_evt)); | |
217 | } | |
218 | aml_append(if_ctx, if_ctx2); | |
219 | else_ctx2 = aml_else(); | |
220 | { | |
221 | aml_append(else_ctx2, | |
222 | aml_call2(AML_NOTIFY_METHOD, idx, remove_evt)); | |
223 | } | |
224 | } | |
225 | aml_append(if_ctx, else_ctx2); | |
226 | aml_append(while_ctx, if_ctx); | |
227 | ||
228 | aml_append(while_ctx, aml_increment(idx)); /* go to next cpu */ | |
229 | aml_append(method, while_ctx); | |
230 | } | |
231 | aml_append(sb_scope, method); | |
232 | ||
233 | /* The current AML generator can cover the APIC ID range [0..255], | |
234 | * inclusive, for VCPU hotplug. */ | |
235 | QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); | |
f0bb276b | 236 | if (x86ms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { |
6a91cf04 | 237 | error_report("max_cpus is too large. APIC ID of last CPU is %u", |
f0bb276b | 238 | x86ms->apic_id_limit - 1); |
6a91cf04 IM |
239 | exit(1); |
240 | } | |
672a2872 IM |
241 | |
242 | /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ | |
243 | dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); | |
244 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); | |
245 | aml_append(dev, | |
246 | aml_name_decl("_UID", aml_string("CPU Hotplug resources")) | |
247 | ); | |
248 | /* device present, functioning, decoding, not shown in UI */ | |
249 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
250 | crs = aml_resource_template(); | |
251 | aml_append(crs, | |
ebd8ea82 | 252 | aml_io(AML_DECODE16, io_base, io_base, 1, ACPI_GPE_PROC_LEN) |
672a2872 IM |
253 | ); |
254 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
255 | aml_append(sb_scope, dev); | |
256 | /* declare CPU hotplug MMIO region and PRS field to access it */ | |
257 | aml_append(sb_scope, aml_operation_region( | |
ebd8ea82 | 258 | "PRST", AML_SYSTEM_IO, aml_int(io_base), ACPI_GPE_PROC_LEN)); |
672a2872 IM |
259 | field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); |
260 | aml_append(field, aml_named_field("PRS", 256)); | |
261 | aml_append(sb_scope, field); | |
262 | ||
263 | /* build Processor object for each processor */ | |
264 | for (i = 0; i < apic_ids->len; i++) { | |
265 | int apic_id = apic_ids->cpus[i].arch_id; | |
266 | ||
267 | assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT); | |
268 | ||
76bdd24e | 269 | dev = aml_processor(i, 0, 0, "CP%.02X", apic_id); |
672a2872 IM |
270 | |
271 | method = aml_method("_MAT", 0, AML_NOTSERIALIZED); | |
272 | aml_append(method, | |
76bdd24e IM |
273 | aml_return(aml_call2(CPU_MAT_METHOD, aml_int(apic_id), aml_int(i)) |
274 | )); | |
672a2872 IM |
275 | aml_append(dev, method); |
276 | ||
277 | method = aml_method("_STA", 0, AML_NOTSERIALIZED); | |
278 | aml_append(method, | |
279 | aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(apic_id)))); | |
280 | aml_append(dev, method); | |
281 | ||
282 | method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); | |
283 | aml_append(method, | |
284 | aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(apic_id), | |
285 | aml_arg(0))) | |
286 | ); | |
287 | aml_append(dev, method); | |
288 | ||
289 | aml_append(sb_scope, dev); | |
290 | } | |
291 | ||
292 | /* build this code: | |
293 | * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} | |
294 | */ | |
76bdd24e | 295 | /* Arg0 = APIC ID */ |
672a2872 IM |
296 | method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); |
297 | for (i = 0; i < apic_ids->len; i++) { | |
298 | int apic_id = apic_ids->cpus[i].arch_id; | |
299 | ||
300 | if_ctx = aml_if(aml_equal(aml_arg(0), aml_int(apic_id))); | |
301 | aml_append(if_ctx, | |
302 | aml_notify(aml_name("CP%.02X", apic_id), aml_arg(1)) | |
303 | ); | |
304 | aml_append(method, if_ctx); | |
305 | } | |
306 | aml_append(sb_scope, method); | |
307 | ||
308 | /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" | |
309 | * | |
310 | * Note: The ability to create variable-sized packages was first | |
311 | * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages | |
312 | * ith up to 255 elements. Windows guests up to win2k8 fail when | |
313 | * VarPackageOp is used. | |
314 | */ | |
f0bb276b PB |
315 | pkg = x86ms->apic_id_limit <= 255 ? aml_package(x86ms->apic_id_limit) : |
316 | aml_varpackage(x86ms->apic_id_limit); | |
672a2872 IM |
317 | |
318 | for (i = 0, apic_idx = 0; i < apic_ids->len; i++) { | |
319 | int apic_id = apic_ids->cpus[i].arch_id; | |
320 | ||
321 | for (; apic_idx < apic_id; apic_idx++) { | |
322 | aml_append(pkg, aml_int(0)); | |
323 | } | |
324 | aml_append(pkg, aml_int(apic_ids->cpus[i].cpu ? 1 : 0)); | |
325 | apic_idx = apic_id + 1; | |
326 | } | |
327 | aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); | |
672a2872 IM |
328 | aml_append(ctx, sb_scope); |
329 | ||
330 | method = aml_method("\\_GPE._E02", 0, AML_NOTSERIALIZED); | |
331 | aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); | |
332 | aml_append(ctx, method); | |
333 | } |