[mirror_qemu.git] / hw / acpi / ich9.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
 *
 * This is based on acpi.c.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2.1 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qemu/timer.h"
#include "hw/core/cpu.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/tco.h"

#include "hw/i386/ich9.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"

//#define DEBUG

#ifdef DEBUG
#define ICH9_DEBUG(fmt, ...) \
do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#else
#define ICH9_DEBUG(fmt, ...)    do { } while (0)
#endif

static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
    ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
    acpi_update_sci(&pm->acpi_regs, pm->irq);
}

static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
}

static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
                            unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
    acpi_update_sci(&pm->acpi_regs, pm->irq);
}

static const MemoryRegionOps ich9_gpe_ops = {
    .read = ich9_gpe_readb,
    .write = ich9_gpe_writeb,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 1,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    switch (addr) {
    case 0:
        return pm->smi_en;
    case 4:
        return pm->smi_sts;
    default:
        return 0;
    }
}

static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
                            unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    TCOIORegs *tr = &pm->tco_regs;
    uint64_t tco_en;

    switch (addr) {
    case 0:
        tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
        /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
        if (tr->tco.cnt1 & TCO_LOCK) {
            val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en;
        }
        pm->smi_en &= ~pm->smi_en_wmask;
        pm->smi_en |= (val & pm->smi_en_wmask);
        break;
    }
}

static const MemoryRegionOps ich9_smi_ops = {
    .read = ich9_smi_readl,
    .write = ich9_smi_writel,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
{
    ICH9_DEBUG("to 0x%x\n", pm_io_base);

    assert((pm_io_base & ICH9_PMIO_MASK) == 0);

    pm->pm_io_base = pm_io_base;
    memory_region_transaction_begin();
    memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
    memory_region_set_address(&pm->io, pm->pm_io_base);
    memory_region_transaction_commit();
}

static int ich9_pm_post_load(void *opaque, int version_id)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t pm_io_base = pm->pm_io_base;
    pm->pm_io_base = 0;
    ich9_pm_iospace_update(pm, pm_io_base);
    return 0;
}

#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 {                                                                   \
     .name       = (stringify(_field)),                              \
     .version_id = 0,                                                \
     .num        = ICH9_PMIO_GPE0_LEN,                               \
     .info       = &vmstate_info_uint8,                              \
     .size       = sizeof(uint8_t),                                  \
     .flags      = VMS_ARRAY | VMS_POINTER,                          \
     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 }

static bool vmstate_test_use_memhp(void *opaque)
{
    ICH9LPCPMRegs *s = opaque;
    return s->acpi_memory_hotplug.is_enabled;
}

static const VMStateDescription vmstate_memhp_state = {
    .name = "ich9_pm/memhp",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = vmstate_test_use_memhp,
    .fields      = (VMStateField[]) {
        VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    }
};

static bool vmstate_test_use_tco(void *opaque)
{
    ICH9LPCPMRegs *s = opaque;
    return s->enable_tco;
}

static const VMStateDescription vmstate_tco_io_state = {
    .name = "ich9_pm/tco",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = vmstate_test_use_tco,
    .fields      = (VMStateField[]) {
        VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
                       TCOIORegs),
        VMSTATE_END_OF_LIST()
    }
};

static bool vmstate_test_use_cpuhp(void *opaque)
{
    ICH9LPCPMRegs *s = opaque;
    return !s->cpu_hotplug_legacy;
}

static int vmstate_cpuhp_pre_load(void *opaque)
{
    ICH9LPCPMRegs *s = opaque;
    Object *obj = OBJECT(s->gpe_cpu.device);
    object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
    return 0;
}

static const VMStateDescription vmstate_cpuhp_state = {
    .name = "ich9_pm/cpuhp",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = vmstate_test_use_cpuhp,
    .pre_load = vmstate_cpuhp_pre_load,
    .fields      = (VMStateField[]) {
        VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    }
};

static bool vmstate_test_use_pcihp(void *opaque)
{
    ICH9LPCPMRegs *s = opaque;

    return s->use_acpi_hotplug_bridge;
}

static const VMStateDescription vmstate_pcihp_state = {
    .name = "ich9_pm/pcihp",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vmstate_test_use_pcihp,
    .fields      = (VMStateField[]) {
        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug,
                            ICH9LPCPMRegs,
                            NULL, NULL),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ich9_pm = {
    .name = "ich9_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = ich9_pm_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
        VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
        VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_memhp_state,
        &vmstate_tco_io_state,
        &vmstate_cpuhp_state,
        &vmstate_pcihp_state,
        NULL
    }
};

static void pm_reset(void *opaque)
{
    ICH9LPCPMRegs *pm = opaque;
    ich9_pm_iospace_update(pm, 0);

    acpi_pm1_evt_reset(&pm->acpi_regs);
    acpi_pm1_cnt_reset(&pm->acpi_regs);
    acpi_pm_tmr_reset(&pm->acpi_regs);
    acpi_gpe_reset(&pm->acpi_regs);

    pm->smi_en = 0;
    if (!pm->smm_enabled) {
        /* Mark SMM as already inited to prevent SMM from running. */
        pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
    }
    pm->smi_en_wmask = ~0;

    if (pm->use_acpi_hotplug_bridge) {
        acpi_pcihp_reset(&pm->acpi_pci_hotplug, true);
    }

    acpi_update_sci(&pm->acpi_regs, pm->irq);
}

static void pm_powerdown_req(Notifier *n, void *opaque)
{
    ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);

    acpi_pm1_evt_power_down(&pm->acpi_regs);
}

void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
                  bool smm_enabled,
                  qemu_irq sci_irq)
{
    memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
    memory_region_set_enabled(&pm->io, false);
    memory_region_add_subregion(pci_address_space_io(lpc_pci),
                                0, &pm->io);

    acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
    acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
    acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
                      pm->s4_val, !pm->smm_compat && !smm_enabled);

    acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
    memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
                          "acpi-gpe0", ICH9_PMIO_GPE0_LEN);
    memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);

    memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
                          "acpi-smi", 8);
    memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);

    pm->smm_enabled = smm_enabled;

    pm->enable_tco = true;
    acpi_pm_tco_init(&pm->tco_regs, &pm->io);

    if (pm->use_acpi_hotplug_bridge) {
        acpi_pcihp_init(OBJECT(lpc_pci),
                        &pm->acpi_pci_hotplug,
                        pci_get_bus(lpc_pci),
                        pci_address_space_io(lpc_pci),
                        true,
                        ACPI_PCIHP_ADDR_ICH9);

        qbus_set_hotplug_handler(BUS(pci_get_bus(lpc_pci)),
                                 OBJECT(lpc_pci));
    }

    pm->irq = sci_irq;
    qemu_register_reset(pm_reset, pm);
    pm->powerdown_notifier.notify = pm_powerdown_req;
    qemu_register_powerdown_notifier(&pm->powerdown_notifier);

    legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci),
        OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);

    if (pm->acpi_memory_hotplug.is_enabled) {
        acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
                                 &pm->acpi_memory_hotplug,
                                 ACPI_MEMORY_HOTPLUG_BASE);
    }
}

static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name,
                                 void *opaque, Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;

    visit_type_uint32(v, name, &value, errp);
}

static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    return s->pm.acpi_memory_hotplug.is_enabled;
}

static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
                                               Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    s->pm.acpi_memory_hotplug.is_enabled = value;
}

static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    return s->pm.cpu_hotplug_legacy;
}

static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value,
                                           Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    assert(!value);
    if (s->pm.cpu_hotplug_legacy && value == false) {
        acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state,
                                   ICH9_CPU_HOTPLUG_IO_BASE);
    }
    s->pm.cpu_hotplug_legacy = value;
}

static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
    return s->pm.enable_tco;
}

static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
    s->pm.enable_tco = value;
}

static bool ich9_pm_get_acpi_pci_hotplug(Object *obj, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    return s->pm.use_acpi_hotplug_bridge;
}

static void ich9_pm_set_acpi_pci_hotplug(Object *obj, bool value, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    s->pm.use_acpi_hotplug_bridge = value;
}

void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
{
    static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
    pm->acpi_memory_hotplug.is_enabled = true;
    pm->cpu_hotplug_legacy = true;
    pm->disable_s3 = 0;
    pm->disable_s4 = 0;
    pm->s4_val = 2;
    pm->use_acpi_hotplug_bridge = true;

    object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
                                   &pm->pm_io_base, OBJ_PROP_FLAG_READ);
    object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
                        ich9_pm_get_gpe0_blk,
                        NULL, NULL, pm);
    object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
                                   &gpe0_len, OBJ_PROP_FLAG_READ);
    object_property_add_bool(obj, "memory-hotplug-support",
                             ich9_pm_get_memory_hotplug_support,
                             ich9_pm_set_memory_hotplug_support);
    object_property_add_bool(obj, "cpu-hotplug-legacy",
                             ich9_pm_get_cpu_hotplug_legacy,
                             ich9_pm_set_cpu_hotplug_legacy);
    object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED,
                                  &pm->disable_s3, OBJ_PROP_FLAG_READWRITE);
    object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED,
                                  &pm->disable_s4, OBJ_PROP_FLAG_READWRITE);
    object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_VAL,
                                  &pm->s4_val, OBJ_PROP_FLAG_READWRITE);
    object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
                             ich9_pm_get_enable_tco,
                             ich9_pm_set_enable_tco);
    object_property_add_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
                             ich9_pm_get_acpi_pci_hotplug,
                             ich9_pm_set_acpi_pci_hotplug);
}

void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
                                Error **errp)
{
    ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);

    if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
        acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
        return;
    }

    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
        !lpc->pm.acpi_memory_hotplug.is_enabled) {
        error_setg(errp,
                   "memory hotplug is not enabled: %s.memory-hotplug-support "
                   "is not set", object_get_typename(OBJECT(lpc)));
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
        uint64_t negotiated = lpc->smi_negotiated_features;

        if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
            !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
            error_setg(errp, "cpu hotplug with SMI wasn't enabled by firmware");
            error_append_hint(errp, "update machine type to newer than 5.1 "
                "and firmware that suppors CPU hotplug with SMM");
        }
    }
}

void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
                            Error **errp)
{
    ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);

    if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
        if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
            nvdimm_acpi_plug_cb(hotplug_dev, dev);
        } else {
            acpi_memory_plug_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug,
                                dev, errp);
        }
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
        if (lpc->pm.cpu_hotplug_legacy) {
            legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp);
        } else {
            acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp);
        }
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
        acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug,
                                  dev, errp);
    } else {
        error_setg(errp, "acpi: device plug request for not supported device"
                   " type: %s", object_get_typename(OBJECT(dev)));
    }
}

void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
                                      DeviceState *dev, Error **errp)
{
    ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);

    if (lpc->pm.acpi_memory_hotplug.is_enabled &&
        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
        acpi_memory_unplug_request_cb(hotplug_dev,
                                      &lpc->pm.acpi_memory_hotplug, dev,
                                      errp);
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
               !lpc->pm.cpu_hotplug_legacy) {
        uint64_t negotiated = lpc->smi_negotiated_features;

        if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
            !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) {
            error_setg(errp, "cpu hot-unplug with SMI wasn't enabled "
                             "by firmware");
            error_append_hint(errp, "update machine type to a version having "
                                    "x-smi-cpu-hotunplug=on and firmware that "
                                    "supports CPU hot-unplug with SMM");
            return;
        }

        acpi_cpu_unplug_request_cb(hotplug_dev, &lpc->pm.cpuhp_state,
                                   dev, errp);
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
        acpi_pcihp_device_unplug_request_cb(hotplug_dev,
                                            &lpc->pm.acpi_pci_hotplug,
                                            dev, errp);
    } else {
        error_setg(errp, "acpi: device unplug request for not supported device"
                   " type: %s", object_get_typename(OBJECT(dev)));
    }
}

void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
                              Error **errp)
{
    ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);

    if (lpc->pm.acpi_memory_hotplug.is_enabled &&
        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
        acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp);
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
               !lpc->pm.cpu_hotplug_legacy) {
        acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp);
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
        acpi_pcihp_device_unplug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug,
                                    dev, errp);
    } else {
        error_setg(errp, "acpi: device unplug for not supported device"
                   " type: %s", object_get_typename(OBJECT(dev)));
    }
}

void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(adev);

    acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
    if (!s->pm.cpu_hotplug_legacy) {
        acpi_cpu_ospm_status(&s->pm.cpuhp_state, list);
    }
}
Commit	Line	Data
e516572f JB	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
6f918e40 JB	5	* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
	6	* VA Linux Systems Japan K.K.
	7	* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
	8	*
	9	* This is based on acpi.c.
e516572f JB	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
61f3c91a	13	* License version 2.1 as published by the Free Software Foundation.
e516572f JB	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, see <http://www.gnu.org/licenses/>
e516572f	22	*
6f918e40 JB	23	* Contributions after 2012-01-13 are licensed under the terms of the
6f918e40 JB	24	* GNU GPL, version 2 or (at your option) any later version.
e516572f	25	*/
71e8a915	26
b6a0aa05	27	#include "qemu/osdep.h"
da34e65c	28	#include "qapi/error.h"
6f1426ab	29	#include "qapi/visitor.h"
83c9f4ca	30	#include "hw/pci/pci.h"
d6454270	31	#include "migration/vmstate.h"
1de7afc9	32	#include "qemu/timer.h"
2e5b09fd	33	#include "hw/core/cpu.h"
71e8a915	34	#include "sysemu/reset.h"
54d31236	35	#include "sysemu/runstate.h"
0d09e41a	36	#include "hw/acpi/acpi.h"
92055797	37	#include "hw/acpi/tco.h"
e516572f	38
0d09e41a	39	#include "hw/i386/ich9.h"
1f862184	40	#include "hw/mem/pc-dimm.h"
132a908b	41	#include "hw/mem/nvdimm.h"
e516572f JB	42
	43	//#define DEBUG
	44
	45	#ifdef DEBUG
	46	#define ICH9_DEBUG(fmt, ...) \
	47	do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
	48	#else
	49	#define ICH9_DEBUG(fmt, ...) do { } while (0)
	50	#endif
	51
e516572f JB	52	static void ich9_pm_update_sci_fn(ACPIREGS *regs)
	53	{
	54	ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
06313503	55	acpi_update_sci(&pm->acpi_regs, pm->irq);
e516572f JB	56	}
e516572f JB	57
76a7daf9 GH	58	static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
	59	{
	60	ICH9LPCPMRegs *pm = opaque;
	61	return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
	62	}
	63
	64	static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
	65	unsigned width)
	66	{
	67	ICH9LPCPMRegs *pm = opaque;
	68	acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
2c047956	69	acpi_update_sci(&pm->acpi_regs, pm->irq);
76a7daf9 GH	70	}
	71
	72	static const MemoryRegionOps ich9_gpe_ops = {
	73	.read = ich9_gpe_readb,
	74	.write = ich9_gpe_writeb,
	75	.valid.min_access_size = 1,
	76	.valid.max_access_size = 4,
	77	.impl.min_access_size = 1,
	78	.impl.max_access_size = 1,
	79	.endianness = DEVICE_LITTLE_ENDIAN,
	80	};
	81
10cc69b0 GH	82	static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
	83	{
	84	ICH9LPCPMRegs *pm = opaque;
	85	switch (addr) {
	86	case 0:
	87	return pm->smi_en;
	88	case 4:
	89	return pm->smi_sts;
	90	default:
	91	return 0;
	92	}
	93	}
	94
	95	static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
	96	unsigned width)
	97	{
	98	ICH9LPCPMRegs *pm = opaque;
92055797 PA	99	TCOIORegs *tr = &pm->tco_regs;
	100	uint64_t tco_en;
	101
10cc69b0 GH	102	switch (addr) {
10cc69b0 GH	103	case 0:
92055797 PA	104	tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN;
	105	/* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */
	106	if (tr->tco.cnt1 & TCO_LOCK) {
	107	val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) \| tco_en;
	108	}
11e66a15 GH	109	pm->smi_en &= ~pm->smi_en_wmask;
11e66a15 GH	110	pm->smi_en \|= (val & pm->smi_en_wmask);
10cc69b0 GH	111	break;
	112	}
	113	}
	114
	115	static const MemoryRegionOps ich9_smi_ops = {
	116	.read = ich9_smi_readl,
	117	.write = ich9_smi_writel,
	118	.valid.min_access_size = 4,
	119	.valid.max_access_size = 4,
	120	.endianness = DEVICE_LITTLE_ENDIAN,
	121	};
	122
e516572f JB	123	void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
	124	{
	125	ICH9_DEBUG("to 0x%x\n", pm_io_base);
	126
	127	assert((pm_io_base & ICH9_PMIO_MASK) == 0);
	128
e516572f	129	pm->pm_io_base = pm_io_base;
cacaab8b GH	130	memory_region_transaction_begin();
	131	memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
	132	memory_region_set_address(&pm->io, pm->pm_io_base);
	133	memory_region_transaction_commit();
e516572f JB	134	}
	135
	136	static int ich9_pm_post_load(void *opaque, int version_id)
	137	{
	138	ICH9LPCPMRegs *pm = opaque;
	139	uint32_t pm_io_base = pm->pm_io_base;
	140	pm->pm_io_base = 0;
	141	ich9_pm_iospace_update(pm, pm_io_base);
	142	return 0;
	143	}
	144
	145	#define VMSTATE_GPE_ARRAY(_field, _state) \
	146	{ \
	147	.name = (stringify(_field)), \
	148	.version_id = 0, \
	149	.num = ICH9_PMIO_GPE0_LEN, \
	150	.info = &vmstate_info_uint8, \
	151	.size = sizeof(uint8_t), \
	152	.flags = VMS_ARRAY \| VMS_POINTER, \
	153	.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
	154	}
	155
f816a62d IM	156	static bool vmstate_test_use_memhp(void *opaque)
	157	{
	158	ICH9LPCPMRegs *s = opaque;
	159	return s->acpi_memory_hotplug.is_enabled;
	160	}
	161
	162	static const VMStateDescription vmstate_memhp_state = {
	163	.name = "ich9_pm/memhp",
	164	.version_id = 1,
	165	.minimum_version_id = 1,
	166	.minimum_version_id_old = 1,
5cd8cada	167	.needed = vmstate_test_use_memhp,
f816a62d IM	168	.fields = (VMStateField[]) {
	169	VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
	170	VMSTATE_END_OF_LIST()
	171	}
	172	};
	173
92055797 PA	174	static bool vmstate_test_use_tco(void *opaque)
	175	{
	176	ICH9LPCPMRegs *s = opaque;
	177	return s->enable_tco;
	178	}
	179
	180	static const VMStateDescription vmstate_tco_io_state = {
	181	.name = "ich9_pm/tco",
	182	.version_id = 1,
	183	.minimum_version_id = 1,
	184	.minimum_version_id_old = 1,
	185	.needed = vmstate_test_use_tco,
	186	.fields = (VMStateField[]) {
	187	VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts,
	188	TCOIORegs),
	189	VMSTATE_END_OF_LIST()
	190	}
	191	};
	192
679dd1a9 IM	193	static bool vmstate_test_use_cpuhp(void *opaque)
	194	{
	195	ICH9LPCPMRegs *s = opaque;
	196	return !s->cpu_hotplug_legacy;
	197	}
	198
	199	static int vmstate_cpuhp_pre_load(void *opaque)
	200	{
	201	ICH9LPCPMRegs *s = opaque;
	202	Object *obj = OBJECT(s->gpe_cpu.device);
5325cc34	203	object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
679dd1a9 IM	204	return 0;
	205	}
	206
	207	static const VMStateDescription vmstate_cpuhp_state = {
	208	.name = "ich9_pm/cpuhp",
	209	.version_id = 1,
	210	.minimum_version_id = 1,
	211	.minimum_version_id_old = 1,
	212	.needed = vmstate_test_use_cpuhp,
	213	.pre_load = vmstate_cpuhp_pre_load,
	214	.fields = (VMStateField[]) {
	215	VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs),
	216	VMSTATE_END_OF_LIST()
	217	}
	218	};
	219
c0e427d6 JS	220	static bool vmstate_test_use_pcihp(void *opaque)
	221	{
	222	ICH9LPCPMRegs *s = opaque;
	223
	224	return s->use_acpi_hotplug_bridge;
	225	}
	226
	227	static const VMStateDescription vmstate_pcihp_state = {
	228	.name = "ich9_pm/pcihp",
	229	.version_id = 1,
	230	.minimum_version_id = 1,
	231	.needed = vmstate_test_use_pcihp,
	232	.fields = (VMStateField[]) {
	233	VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug,
	234	ICH9LPCPMRegs,
	235	NULL, NULL),
	236	VMSTATE_END_OF_LIST()
	237	}
	238	};
	239
e516572f JB	240	const VMStateDescription vmstate_ich9_pm = {
	241	.name = "ich9_pm",
	242	.version_id = 1,
	243	.minimum_version_id = 1,
e516572f JB	244	.post_load = ich9_pm_post_load,
	245	.fields = (VMStateField[]) {
	246	VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
	247	VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
	248	VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
e720677e	249	VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
e516572f JB	250	VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
	251	VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
	252	VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
	253	VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
	254	VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
	255	VMSTATE_END_OF_LIST()
f816a62d	256	},
5cd8cada JQ	257	.subsections = (const VMStateDescription*[]) {
5cd8cada JQ	258	&vmstate_memhp_state,
92055797	259	&vmstate_tco_io_state,
679dd1a9	260	&vmstate_cpuhp_state,
c0e427d6	261	&vmstate_pcihp_state,
92055797	262	NULL
e516572f JB	263	}
	264	};
	265
	266	static void pm_reset(void *opaque)
	267	{
	268	ICH9LPCPMRegs *pm = opaque;
	269	ich9_pm_iospace_update(pm, 0);
	270
	271	acpi_pm1_evt_reset(&pm->acpi_regs);
	272	acpi_pm1_cnt_reset(&pm->acpi_regs);
	273	acpi_pm_tmr_reset(&pm->acpi_regs);
	274	acpi_gpe_reset(&pm->acpi_regs);
	275
be66680e	276	pm->smi_en = 0;
fba72476	277	if (!pm->smm_enabled) {
f3c30aea	278	/* Mark SMM as already inited to prevent SMM from running. */
21bcfdd9 JK	279	pm->smi_en \|= ICH9_PMIO_SMI_EN_APMC_EN;
21bcfdd9 JK	280	}
11e66a15	281	pm->smi_en_wmask = ~0;
21bcfdd9	282
c0e427d6 JS	283	if (pm->use_acpi_hotplug_bridge) {
	284	acpi_pcihp_reset(&pm->acpi_pci_hotplug, true);
	285	}
	286
06313503	287	acpi_update_sci(&pm->acpi_regs, pm->irq);
e516572f JB	288	}
	289
	290	static void pm_powerdown_req(Notifier n, void opaque)
	291	{
	292	ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
	293
	294	acpi_pm1_evt_power_down(&pm->acpi_regs);
	295	}
	296
92055797	297	void ich9_pm_init(PCIDevice lpc_pci, ICH9LPCPMRegs pm,
18d6abae	298	bool smm_enabled,
a3ac6b53	299	qemu_irq sci_irq)
e516572f	300	{
64bde0f3	301	memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
cacaab8b	302	memory_region_set_enabled(&pm->io, false);
503b19fc GH	303	memory_region_add_subregion(pci_address_space_io(lpc_pci),
503b19fc GH	304	0, &pm->io);
cacaab8b	305
77d58b1e	306	acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
b5a7c024	307	acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
9a10bbb4	308	acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
6be8cf56	309	pm->s4_val, !pm->smm_compat && !smm_enabled);
76a7daf9	310
e516572f	311	acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
64bde0f3	312	memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
75902802	313	"acpi-gpe0", ICH9_PMIO_GPE0_LEN);
76a7daf9	314	memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
e516572f	315
64bde0f3	316	memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
75902802	317	"acpi-smi", 8);
10cc69b0 GH	318	memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
10cc69b0 GH	319
fba72476	320	pm->smm_enabled = smm_enabled;
92055797	321
18d6abae EH	322	pm->enable_tco = true;
18d6abae EH	323	acpi_pm_tco_init(&pm->tco_regs, &pm->io);
92055797	324
c0e427d6 JS	325	if (pm->use_acpi_hotplug_bridge) {
	326	acpi_pcihp_init(OBJECT(lpc_pci),
	327	&pm->acpi_pci_hotplug,
	328	pci_get_bus(lpc_pci),
	329	pci_address_space_io(lpc_pci),
	330	true,
	331	ACPI_PCIHP_ADDR_ICH9);
	332
	333	qbus_set_hotplug_handler(BUS(pci_get_bus(lpc_pci)),
	334	OBJECT(lpc_pci));
	335	}
	336
e516572f JB	337	pm->irq = sci_irq;
	338	qemu_register_reset(pm_reset, pm);
	339	pm->powerdown_notifier.notify = pm_powerdown_req;
	340	qemu_register_powerdown_notifier(&pm->powerdown_notifier);
d6610bc2	341
96e3e12b IM	342	legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci),
96e3e12b IM	343	OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
1f862184 IM	344
	345	if (pm->acpi_memory_hotplug.is_enabled) {
	346	acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
80db0e78 IM	347	&pm->acpi_memory_hotplug,
80db0e78 IM	348	ACPI_MEMORY_HOTPLUG_BASE);
1f862184	349	}
e516572f	350	}
6f1426ab	351
d7bce999 EB	352	static void ich9_pm_get_gpe0_blk(Object obj, Visitor v, const char *name,
d7bce999 EB	353	void opaque, Error *errp)
6f1426ab MT	354	{
	355	ICH9LPCPMRegs *pm = opaque;
	356	uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
	357
51e72bc1	358	visit_type_uint32(v, name, &value, errp);
6f1426ab MT	359	}
6f1426ab MT	360
1f862184 IM	361	static bool ich9_pm_get_memory_hotplug_support(Object obj, Error *errp)
	362	{
	363	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	364
	365	return s->pm.acpi_memory_hotplug.is_enabled;
	366	}
	367
	368	static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
	369	Error **errp)
	370	{
	371	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	372
	373	s->pm.acpi_memory_hotplug.is_enabled = value;
	374	}
	375
16bcab97 IM	376	static bool ich9_pm_get_cpu_hotplug_legacy(Object obj, Error *errp)
	377	{
	378	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	379
	380	return s->pm.cpu_hotplug_legacy;
	381	}
	382
	383	static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value,
	384	Error **errp)
	385	{
	386	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	387
679dd1a9 IM	388	assert(!value);
	389	if (s->pm.cpu_hotplug_legacy && value == false) {
	390	acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state,
	391	ICH9_CPU_HOTPLUG_IO_BASE);
	392	}
16bcab97 IM	393	s->pm.cpu_hotplug_legacy = value;
	394	}
	395
92055797 PA	396	static bool ich9_pm_get_enable_tco(Object obj, Error *errp)
	397	{
	398	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	399	return s->pm.enable_tco;
	400	}
	401
	402	static void ich9_pm_set_enable_tco(Object obj, bool value, Error *errp)
	403	{
	404	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	405	s->pm.enable_tco = value;
	406	}
	407
c0e427d6 JS	408	static bool ich9_pm_get_acpi_pci_hotplug(Object obj, Error *errp)
	409	{
	410	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	411
	412	return s->pm.use_acpi_hotplug_bridge;
	413	}
	414
	415	static void ich9_pm_set_acpi_pci_hotplug(Object obj, bool value, Error *errp)
	416	{
	417	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	418
	419	s->pm.use_acpi_hotplug_bridge = value;
	420	}
	421
40c2281c	422	void ich9_pm_add_properties(Object obj, ICH9LPCPMRegs pm)
6f1426ab MT	423	{
6f1426ab MT	424	static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
1f862184	425	pm->acpi_memory_hotplug.is_enabled = true;
16bcab97	426	pm->cpu_hotplug_legacy = true;
6ac0d8d4 AS	427	pm->disable_s3 = 0;
	428	pm->disable_s4 = 0;
	429	pm->s4_val = 2;
17858a16	430	pm->use_acpi_hotplug_bridge = true;
6f1426ab MT	431
6f1426ab MT	432	object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
d2623129	433	&pm->pm_io_base, OBJ_PROP_FLAG_READ);
6f1426ab MT	434	object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
6f1426ab MT	435	ich9_pm_get_gpe0_blk,
d2623129	436	NULL, NULL, pm);
6f1426ab	437	object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
d2623129	438	&gpe0_len, OBJ_PROP_FLAG_READ);
1f862184 IM	439	object_property_add_bool(obj, "memory-hotplug-support",
1f862184 IM	440	ich9_pm_get_memory_hotplug_support,
d2623129	441	ich9_pm_set_memory_hotplug_support);
16bcab97 IM	442	object_property_add_bool(obj, "cpu-hotplug-legacy",
16bcab97 IM	443	ich9_pm_get_cpu_hotplug_legacy,
d2623129	444	ich9_pm_set_cpu_hotplug_legacy);
64a7b8de	445	object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED,
d2623129	446	&pm->disable_s3, OBJ_PROP_FLAG_READWRITE);
64a7b8de	447	object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED,
d2623129	448	&pm->disable_s4, OBJ_PROP_FLAG_READWRITE);
64a7b8de	449	object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_VAL,
d2623129	450	&pm->s4_val, OBJ_PROP_FLAG_READWRITE);
92055797 PA	451	object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
92055797 PA	452	ich9_pm_get_enable_tco,
d2623129	453	ich9_pm_set_enable_tco);
aa29466b	454	object_property_add_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
c0e427d6 JS	455	ich9_pm_get_acpi_pci_hotplug,
c0e427d6 JS	456	ich9_pm_set_acpi_pci_hotplug);
1f862184 IM	457	}
1f862184 IM	458
9040e6df WY	459	void ich9_pm_device_pre_plug_cb(HotplugHandler hotplug_dev, DeviceState dev,
	460	Error **errp)
	461	{
	462	ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
	463
c0e427d6 JS	464	if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
	465	acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
	466	return;
	467	}
	468
9040e6df	469	if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
c5be7517	470	!lpc->pm.acpi_memory_hotplug.is_enabled) {
9040e6df WY	471	error_setg(errp,
	472	"memory hotplug is not enabled: %s.memory-hotplug-support "
	473	"is not set", object_get_typename(OBJECT(lpc)));
c5be7517 IM	474	} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
	475	uint64_t negotiated = lpc->smi_negotiated_features;
	476
	477	if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
	478	!(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
	479	error_setg(errp, "cpu hotplug with SMI wasn't enabled by firmware");
	480	error_append_hint(errp, "update machine type to newer than 5.1 "
	481	"and firmware that suppors CPU hotplug with SMM");
	482	}
	483	}
9040e6df WY	484	}
9040e6df WY	485
0058c082 IM	486	void ich9_pm_device_plug_cb(HotplugHandler hotplug_dev, DeviceState dev,
0058c082 IM	487	Error **errp)
1f862184	488	{
0058c082 IM	489	ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
0058c082 IM	490
9040e6df	491	if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
75f27498 XG	492	if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
	493	nvdimm_acpi_plug_cb(hotplug_dev, dev);
	494	} else {
	495	acpi_memory_plug_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug,
	496	dev, errp);
	497	}
5e1b5d93 IM	498	} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
	499	if (lpc->pm.cpu_hotplug_legacy) {
	500	legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp);
	501	} else {
	502	acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp);
	503	}
c0e427d6 JS	504	} else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
	505	acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug,
	506	dev, errp);
1f862184 IM	507	} else {
	508	error_setg(errp, "acpi: device plug request for not supported device"
	509	" type: %s", object_get_typename(OBJECT(dev)));
	510	}
6f1426ab	511	}
43f50410	512
0058c082 IM	513	void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
0058c082 IM	514	DeviceState dev, Error *errp)
469b8ad2	515	{
0058c082 IM	516	ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
	517
	518	if (lpc->pm.acpi_memory_hotplug.is_enabled &&
64fec58e	519	object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
0058c082 IM	520	acpi_memory_unplug_request_cb(hotplug_dev,
	521	&lpc->pm.acpi_memory_hotplug, dev,
	522	errp);
8872c25a IM	523	} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
8872c25a IM	524	!lpc->pm.cpu_hotplug_legacy) {
b48ad7c0 IM	525	uint64_t negotiated = lpc->smi_negotiated_features;
	526
	527	if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
	528	!(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) {
	529	error_setg(errp, "cpu hot-unplug with SMI wasn't enabled "
	530	"by firmware");
	531	error_append_hint(errp, "update machine type to a version having "
	532	"x-smi-cpu-hotunplug=on and firmware that "
	533	"supports CPU hot-unplug with SMM");
	534	return;
	535	}
	536
8872c25a IM	537	acpi_cpu_unplug_request_cb(hotplug_dev, &lpc->pm.cpuhp_state,
8872c25a IM	538	dev, errp);
c0e427d6 JS	539	} else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
	540	acpi_pcihp_device_unplug_request_cb(hotplug_dev,
	541	&lpc->pm.acpi_pci_hotplug,
	542	dev, errp);
64fec58e TC	543	} else {
	544	error_setg(errp, "acpi: device unplug request for not supported device"
	545	" type: %s", object_get_typename(OBJECT(dev)));
	546	}
469b8ad2 TC	547	}
469b8ad2 TC	548
0058c082	549	void ich9_pm_device_unplug_cb(HotplugHandler hotplug_dev, DeviceState dev,
91a734a6 TC	550	Error **errp)
91a734a6 TC	551	{
0058c082 IM	552	ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
	553
	554	if (lpc->pm.acpi_memory_hotplug.is_enabled &&
f7d3e29d	555	object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
0058c082	556	acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp);
8872c25a IM	557	} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
	558	!lpc->pm.cpu_hotplug_legacy) {
	559	acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp);
c0e427d6 JS	560	} else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
	561	acpi_pcihp_device_unplug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug,
	562	dev, errp);
f7d3e29d TC	563	} else {
	564	error_setg(errp, "acpi: device unplug for not supported device"
	565	" type: %s", object_get_typename(OBJECT(dev)));
	566	}
91a734a6 TC	567	}
91a734a6 TC	568
43f50410 IM	569	void ich9_pm_ospm_status(AcpiDeviceIf adev, ACPIOSTInfoList **list)
	570	{
	571	ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
	572
	573	acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
76623d00 IM	574	if (!s->pm.cpu_hotplug_legacy) {
	575	acpi_cpu_ospm_status(&s->pm.cpuhp_state, list);
	576	}
43f50410	577	}