[mirror_qemu.git] / hw / acpi / ich9.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
 *
 * This is based on acpi.c.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "hw/hw.h"
#include "qapi/visitor.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/acpi/acpi.h"
#include "sysemu/kvm.h"
#include "exec/address-spaces.h"

#include "hw/i386/ich9.h"
#include "hw/mem/pc-dimm.h"

//#define DEBUG

#ifdef DEBUG
#define ICH9_DEBUG(fmt, ...) \
do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#else
#define ICH9_DEBUG(fmt, ...)    do { } while (0)
#endif

static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
    ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
    acpi_update_sci(&pm->acpi_regs, pm->irq);
}

static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
}

static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
                            unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
    acpi_update_sci(&pm->acpi_regs, pm->irq);
}

static const MemoryRegionOps ich9_gpe_ops = {
    .read = ich9_gpe_readb,
    .write = ich9_gpe_writeb,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .impl.min_access_size = 1,
    .impl.max_access_size = 1,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    switch (addr) {
    case 0:
        return pm->smi_en;
    case 4:
        return pm->smi_sts;
    default:
        return 0;
    }
}

static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
                            unsigned width)
{
    ICH9LPCPMRegs *pm = opaque;
    switch (addr) {
    case 0:
        pm->smi_en = val;
        break;
    }
}

static const MemoryRegionOps ich9_smi_ops = {
    .read = ich9_smi_readl,
    .write = ich9_smi_writel,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
{
    ICH9_DEBUG("to 0x%x\n", pm_io_base);

    assert((pm_io_base & ICH9_PMIO_MASK) == 0);

    pm->pm_io_base = pm_io_base;
    memory_region_transaction_begin();
    memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
    memory_region_set_address(&pm->io, pm->pm_io_base);
    memory_region_transaction_commit();
}

static int ich9_pm_post_load(void *opaque, int version_id)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t pm_io_base = pm->pm_io_base;
    pm->pm_io_base = 0;
    ich9_pm_iospace_update(pm, pm_io_base);
    return 0;
}

#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 {                                                                   \
     .name       = (stringify(_field)),                              \
     .version_id = 0,                                                \
     .num        = ICH9_PMIO_GPE0_LEN,                               \
     .info       = &vmstate_info_uint8,                              \
     .size       = sizeof(uint8_t),                                  \
     .flags      = VMS_ARRAY | VMS_POINTER,                          \
     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 }

static bool vmstate_test_use_memhp(void *opaque)
{
    ICH9LPCPMRegs *s = opaque;
    return s->acpi_memory_hotplug.is_enabled;
}

static const VMStateDescription vmstate_memhp_state = {
    .name = "ich9_pm/memhp",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ich9_pm = {
    .name = "ich9_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = ich9_pm_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
        VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
        VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
        VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
        VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
        VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection[]) {
        {
            .vmsd = &vmstate_memhp_state,
            .needed = vmstate_test_use_memhp,
        },
        VMSTATE_END_OF_LIST()
    }
};

static void pm_reset(void *opaque)
{
    ICH9LPCPMRegs *pm = opaque;
    ich9_pm_iospace_update(pm, 0);

    acpi_pm1_evt_reset(&pm->acpi_regs);
    acpi_pm1_cnt_reset(&pm->acpi_regs);
    acpi_pm_tmr_reset(&pm->acpi_regs);
    acpi_gpe_reset(&pm->acpi_regs);

    if (kvm_enabled()) {
        /* Mark SMM as already inited to prevent SMM from running. KVM does not
         * support SMM mode. */
        pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
    }

    acpi_update_sci(&pm->acpi_regs, pm->irq);
}

static void pm_powerdown_req(Notifier *n, void *opaque)
{
    ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);

    acpi_pm1_evt_power_down(&pm->acpi_regs);
}

void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
                  qemu_irq sci_irq)
{
    memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
    memory_region_set_enabled(&pm->io, false);
    memory_region_add_subregion(pci_address_space_io(lpc_pci),
                                0, &pm->io);

    acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
    acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
    acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
                      pm->s4_val);

    acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
    memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
                          "acpi-gpe0", ICH9_PMIO_GPE0_LEN);
    memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);

    memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
                          "acpi-smi", 8);
    memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);

    pm->irq = sci_irq;
    qemu_register_reset(pm_reset, pm);
    pm->powerdown_notifier.notify = pm_powerdown_req;
    qemu_register_powerdown_notifier(&pm->powerdown_notifier);

    acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
                          &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);

    if (pm->acpi_memory_hotplug.is_enabled) {
        acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
                                 &pm->acpi_memory_hotplug);
    }
}

static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
                                 void *opaque, const char *name,
                                 Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;

    visit_type_uint32(v, &value, name, errp);
}

static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    return s->pm.acpi_memory_hotplug.is_enabled;
}

static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
                                               Error **errp)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(obj);

    s->pm.acpi_memory_hotplug.is_enabled = value;
}

static void ich9_pm_get_disable_s3(Object *obj, Visitor *v,
                                   void *opaque, const char *name,
                                   Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    uint8_t value = pm->disable_s3;

    visit_type_uint8(v, &value, name, errp);
}

static void ich9_pm_set_disable_s3(Object *obj, Visitor *v,
                                   void *opaque, const char *name,
                                   Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    Error *local_err = NULL;
    uint8_t value;

    visit_type_uint8(v, &value, name, &local_err);
    if (local_err) {
        goto out;
    }
    pm->disable_s3 = value;
out:
    error_propagate(errp, local_err);
}

static void ich9_pm_get_disable_s4(Object *obj, Visitor *v,
                                   void *opaque, const char *name,
                                   Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    uint8_t value = pm->disable_s4;

    visit_type_uint8(v, &value, name, errp);
}

static void ich9_pm_set_disable_s4(Object *obj, Visitor *v,
                                   void *opaque, const char *name,
                                   Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    Error *local_err = NULL;
    uint8_t value;

    visit_type_uint8(v, &value, name, &local_err);
    if (local_err) {
        goto out;
    }
    pm->disable_s4 = value;
out:
    error_propagate(errp, local_err);
}

static void ich9_pm_get_s4_val(Object *obj, Visitor *v,
                               void *opaque, const char *name,
                               Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    uint8_t value = pm->s4_val;

    visit_type_uint8(v, &value, name, errp);
}

static void ich9_pm_set_s4_val(Object *obj, Visitor *v,
                               void *opaque, const char *name,
                               Error **errp)
{
    ICH9LPCPMRegs *pm = opaque;
    Error *local_err = NULL;
    uint8_t value;

    visit_type_uint8(v, &value, name, &local_err);
    if (local_err) {
        goto out;
    }
    pm->s4_val = value;
out:
    error_propagate(errp, local_err);
}

void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
{
    static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
    pm->acpi_memory_hotplug.is_enabled = true;
    pm->disable_s3 = 0;
    pm->disable_s4 = 0;
    pm->s4_val = 2;

    object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
                                   &pm->pm_io_base, errp);
    object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
                        ich9_pm_get_gpe0_blk,
                        NULL, NULL, pm, NULL);
    object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
                                   &gpe0_len, errp);
    object_property_add_bool(obj, "memory-hotplug-support",
                             ich9_pm_get_memory_hotplug_support,
                             ich9_pm_set_memory_hotplug_support,
                             NULL);
    object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8",
                        ich9_pm_get_disable_s3,
                        ich9_pm_set_disable_s3,
                        NULL, pm, NULL);
    object_property_add(obj, ACPI_PM_PROP_S4_DISABLED, "uint8",
                        ich9_pm_get_disable_s4,
                        ich9_pm_set_disable_s4,
                        NULL, pm, NULL);
    object_property_add(obj, ACPI_PM_PROP_S4_VAL, "uint8",
                        ich9_pm_get_s4_val,
                        ich9_pm_set_s4_val,
                        NULL, pm, NULL);
}

void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp)
{
    if (pm->acpi_memory_hotplug.is_enabled &&
        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
        acpi_memory_plug_cb(&pm->acpi_regs, pm->irq, &pm->acpi_memory_hotplug,
                            dev, errp);
    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
        acpi_cpu_plug_cb(&pm->acpi_regs, pm->irq, &pm->gpe_cpu, dev, errp);
    } else {
        error_setg(errp, "acpi: device plug request for not supported device"
                   " type: %s", object_get_typename(OBJECT(dev)));
    }
}

void ich9_pm_device_unplug_request_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
                                      Error **errp)
{
    if (pm->acpi_memory_hotplug.is_enabled &&
        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
        acpi_memory_unplug_request_cb(&pm->acpi_regs, pm->irq,
                                      &pm->acpi_memory_hotplug, dev, errp);
    } else {
        error_setg(errp, "acpi: device unplug request for not supported device"
                   " type: %s", object_get_typename(OBJECT(dev)));
    }
}

void ich9_pm_device_unplug_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
                              Error **errp)
{
    if (pm->acpi_memory_hotplug.is_enabled &&
        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
        acpi_memory_unplug_cb(&pm->acpi_memory_hotplug, dev, errp);
    } else {
        error_setg(errp, "acpi: device unplug for not supported device"
                   " type: %s", object_get_typename(OBJECT(dev)));
    }
}

void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
{
    ICH9LPCState *s = ICH9_LPC_DEVICE(adev);

    acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
}
Commit	Line	Data
e516572f JB	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
6f918e40 JB	5	* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
	6	* VA Linux Systems Japan K.K.
	7	* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
	8	*
	9	* This is based on acpi.c.
e516572f JB	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License version 2 as published by the Free Software Foundation.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, see <http://www.gnu.org/licenses/>
e516572f	22	*
6f918e40 JB	23	* Contributions after 2012-01-13 are licensed under the terms of the
6f918e40 JB	24	* GNU GPL, version 2 or (at your option) any later version.
e516572f	25	*/
83c9f4ca	26	#include "hw/hw.h"
6f1426ab	27	#include "qapi/visitor.h"
0d09e41a	28	#include "hw/i386/pc.h"
83c9f4ca	29	#include "hw/pci/pci.h"
1de7afc9	30	#include "qemu/timer.h"
9c17d615	31	#include "sysemu/sysemu.h"
0d09e41a	32	#include "hw/acpi/acpi.h"
9c17d615	33	#include "sysemu/kvm.h"
022c62cb	34	#include "exec/address-spaces.h"
e516572f	35
0d09e41a	36	#include "hw/i386/ich9.h"
1f862184	37	#include "hw/mem/pc-dimm.h"
e516572f JB	38
	39	//#define DEBUG
	40
	41	#ifdef DEBUG
	42	#define ICH9_DEBUG(fmt, ...) \
	43	do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
	44	#else
	45	#define ICH9_DEBUG(fmt, ...) do { } while (0)
	46	#endif
	47
e516572f JB	48	static void ich9_pm_update_sci_fn(ACPIREGS *regs)
	49	{
	50	ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
06313503	51	acpi_update_sci(&pm->acpi_regs, pm->irq);
e516572f JB	52	}
e516572f JB	53
76a7daf9 GH	54	static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
	55	{
	56	ICH9LPCPMRegs *pm = opaque;
	57	return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
	58	}
	59
	60	static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
	61	unsigned width)
	62	{
	63	ICH9LPCPMRegs *pm = opaque;
	64	acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
2c047956	65	acpi_update_sci(&pm->acpi_regs, pm->irq);
76a7daf9 GH	66	}
	67
	68	static const MemoryRegionOps ich9_gpe_ops = {
	69	.read = ich9_gpe_readb,
	70	.write = ich9_gpe_writeb,
	71	.valid.min_access_size = 1,
	72	.valid.max_access_size = 4,
	73	.impl.min_access_size = 1,
	74	.impl.max_access_size = 1,
	75	.endianness = DEVICE_LITTLE_ENDIAN,
	76	};
	77
10cc69b0 GH	78	static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
	79	{
	80	ICH9LPCPMRegs *pm = opaque;
	81	switch (addr) {
	82	case 0:
	83	return pm->smi_en;
	84	case 4:
	85	return pm->smi_sts;
	86	default:
	87	return 0;
	88	}
	89	}
	90
	91	static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
	92	unsigned width)
	93	{
	94	ICH9LPCPMRegs *pm = opaque;
	95	switch (addr) {
	96	case 0:
	97	pm->smi_en = val;
	98	break;
	99	}
	100	}
	101
	102	static const MemoryRegionOps ich9_smi_ops = {
	103	.read = ich9_smi_readl,
	104	.write = ich9_smi_writel,
	105	.valid.min_access_size = 4,
	106	.valid.max_access_size = 4,
	107	.endianness = DEVICE_LITTLE_ENDIAN,
	108	};
	109
e516572f JB	110	void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
	111	{
	112	ICH9_DEBUG("to 0x%x\n", pm_io_base);
	113
	114	assert((pm_io_base & ICH9_PMIO_MASK) == 0);
	115
e516572f	116	pm->pm_io_base = pm_io_base;
cacaab8b GH	117	memory_region_transaction_begin();
	118	memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
	119	memory_region_set_address(&pm->io, pm->pm_io_base);
	120	memory_region_transaction_commit();
e516572f JB	121	}
	122
	123	static int ich9_pm_post_load(void *opaque, int version_id)
	124	{
	125	ICH9LPCPMRegs *pm = opaque;
	126	uint32_t pm_io_base = pm->pm_io_base;
	127	pm->pm_io_base = 0;
	128	ich9_pm_iospace_update(pm, pm_io_base);
	129	return 0;
	130	}
	131
	132	#define VMSTATE_GPE_ARRAY(_field, _state) \
	133	{ \
	134	.name = (stringify(_field)), \
	135	.version_id = 0, \
	136	.num = ICH9_PMIO_GPE0_LEN, \
	137	.info = &vmstate_info_uint8, \
	138	.size = sizeof(uint8_t), \
	139	.flags = VMS_ARRAY \| VMS_POINTER, \
	140	.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
	141	}
	142
f816a62d IM	143	static bool vmstate_test_use_memhp(void *opaque)
	144	{
	145	ICH9LPCPMRegs *s = opaque;
	146	return s->acpi_memory_hotplug.is_enabled;
	147	}
	148
	149	static const VMStateDescription vmstate_memhp_state = {
	150	.name = "ich9_pm/memhp",
	151	.version_id = 1,
	152	.minimum_version_id = 1,
	153	.minimum_version_id_old = 1,
	154	.fields = (VMStateField[]) {
	155	VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
	156	VMSTATE_END_OF_LIST()
	157	}
	158	};
	159
e516572f JB	160	const VMStateDescription vmstate_ich9_pm = {
	161	.name = "ich9_pm",
	162	.version_id = 1,
	163	.minimum_version_id = 1,
e516572f JB	164	.post_load = ich9_pm_post_load,
	165	.fields = (VMStateField[]) {
	166	VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
	167	VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
	168	VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
e720677e	169	VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
e516572f JB	170	VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
	171	VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
	172	VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
	173	VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
	174	VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
	175	VMSTATE_END_OF_LIST()
f816a62d IM	176	},
	177	.subsections = (VMStateSubsection[]) {
	178	{
	179	.vmsd = &vmstate_memhp_state,
	180	.needed = vmstate_test_use_memhp,
	181	},
	182	VMSTATE_END_OF_LIST()
e516572f JB	183	}
	184	};
	185
	186	static void pm_reset(void *opaque)
	187	{
	188	ICH9LPCPMRegs *pm = opaque;
	189	ich9_pm_iospace_update(pm, 0);
	190
	191	acpi_pm1_evt_reset(&pm->acpi_regs);
	192	acpi_pm1_cnt_reset(&pm->acpi_regs);
	193	acpi_pm_tmr_reset(&pm->acpi_regs);
	194	acpi_gpe_reset(&pm->acpi_regs);
	195
21bcfdd9 JK	196	if (kvm_enabled()) {
	197	/* Mark SMM as already inited to prevent SMM from running. KVM does not
	198	* support SMM mode. */
	199	pm->smi_en \|= ICH9_PMIO_SMI_EN_APMC_EN;
	200	}
	201
06313503	202	acpi_update_sci(&pm->acpi_regs, pm->irq);
e516572f JB	203	}
	204
	205	static void pm_powerdown_req(Notifier n, void opaque)
	206	{
	207	ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
	208
	209	acpi_pm1_evt_power_down(&pm->acpi_regs);
	210	}
	211
503b19fc	212	void ich9_pm_init(PCIDevice lpc_pci, ICH9LPCPMRegs pm,
a3ac6b53	213	qemu_irq sci_irq)
e516572f	214	{
64bde0f3	215	memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
cacaab8b	216	memory_region_set_enabled(&pm->io, false);
503b19fc GH	217	memory_region_add_subregion(pci_address_space_io(lpc_pci),
503b19fc GH	218	0, &pm->io);
cacaab8b	219
77d58b1e	220	acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
b5a7c024	221	acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
9a10bbb4 LE	222	acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
9a10bbb4 LE	223	pm->s4_val);
76a7daf9	224
e516572f	225	acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
64bde0f3	226	memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
75902802	227	"acpi-gpe0", ICH9_PMIO_GPE0_LEN);
76a7daf9	228	memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
e516572f	229
64bde0f3	230	memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
75902802	231	"acpi-smi", 8);
10cc69b0 GH	232	memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
10cc69b0 GH	233
e516572f JB	234	pm->irq = sci_irq;
	235	qemu_register_reset(pm_reset, pm);
	236	pm->powerdown_notifier.notify = pm_powerdown_req;
	237	qemu_register_powerdown_notifier(&pm->powerdown_notifier);
d6610bc2	238
411b5db8 GZ	239	acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
411b5db8 GZ	240	&pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
1f862184 IM	241
	242	if (pm->acpi_memory_hotplug.is_enabled) {
	243	acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
	244	&pm->acpi_memory_hotplug);
	245	}
e516572f	246	}
6f1426ab MT	247
	248	static void ich9_pm_get_gpe0_blk(Object obj, Visitor v,
	249	void opaque, const char name,
	250	Error **errp)
	251	{
	252	ICH9LPCPMRegs *pm = opaque;
	253	uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
	254
	255	visit_type_uint32(v, &value, name, errp);
	256	}
	257
1f862184 IM	258	static bool ich9_pm_get_memory_hotplug_support(Object obj, Error *errp)
	259	{
	260	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	261
	262	return s->pm.acpi_memory_hotplug.is_enabled;
	263	}
	264
	265	static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
	266	Error **errp)
	267	{
	268	ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
	269
	270	s->pm.acpi_memory_hotplug.is_enabled = value;
	271	}
	272
6ac0d8d4 AS	273	static void ich9_pm_get_disable_s3(Object obj, Visitor v,
	274	void opaque, const char name,
	275	Error **errp)
	276	{
	277	ICH9LPCPMRegs *pm = opaque;
	278	uint8_t value = pm->disable_s3;
	279
	280	visit_type_uint8(v, &value, name, errp);
	281	}
	282
	283	static void ich9_pm_set_disable_s3(Object obj, Visitor v,
	284	void opaque, const char name,
	285	Error **errp)
	286	{
	287	ICH9LPCPMRegs *pm = opaque;
	288	Error *local_err = NULL;
	289	uint8_t value;
	290
	291	visit_type_uint8(v, &value, name, &local_err);
	292	if (local_err) {
	293	goto out;
	294	}
	295	pm->disable_s3 = value;
	296	out:
	297	error_propagate(errp, local_err);
	298	}
	299
	300	static void ich9_pm_get_disable_s4(Object obj, Visitor v,
	301	void opaque, const char name,
	302	Error **errp)
	303	{
	304	ICH9LPCPMRegs *pm = opaque;
	305	uint8_t value = pm->disable_s4;
	306
	307	visit_type_uint8(v, &value, name, errp);
	308	}
	309
	310	static void ich9_pm_set_disable_s4(Object obj, Visitor v,
	311	void opaque, const char name,
	312	Error **errp)
	313	{
	314	ICH9LPCPMRegs *pm = opaque;
	315	Error *local_err = NULL;
	316	uint8_t value;
	317
	318	visit_type_uint8(v, &value, name, &local_err);
	319	if (local_err) {
	320	goto out;
	321	}
	322	pm->disable_s4 = value;
	323	out:
	324	error_propagate(errp, local_err);
	325	}
	326
	327	static void ich9_pm_get_s4_val(Object obj, Visitor v,
	328	void opaque, const char name,
	329	Error **errp)
	330	{
	331	ICH9LPCPMRegs *pm = opaque;
	332	uint8_t value = pm->s4_val;
	333
	334	visit_type_uint8(v, &value, name, errp);
	335	}
	336
337	static void ich9_pm_set_s4_val(Object obj, Visitor v,
338	void opaque, const char name,
339	Error **errp)
340	{
341	ICH9LPCPMRegs *pm = opaque;
342	Error *local_err = NULL;
343	uint8_t value;
344
345	visit_type_uint8(v, &value, name, &local_err);
346	if (local_err) {
347	goto out;
348	}
349	pm->s4_val = value;
350	out:
351	error_propagate(errp, local_err);
352	}
353
6f1426ab MT	354	void ich9_pm_add_properties(Object obj, ICH9LPCPMRegs pm, Error **errp)
	355	{
	356	static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
1f862184	357	pm->acpi_memory_hotplug.is_enabled = true;
6ac0d8d4 AS	358	pm->disable_s3 = 0;
	359	pm->disable_s4 = 0;
	360	pm->s4_val = 2;
6f1426ab MT	361
	362	object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
	363	&pm->pm_io_base, errp);
	364	object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
	365	ich9_pm_get_gpe0_blk,
	366	NULL, NULL, pm, NULL);
	367	object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
	368	&gpe0_len, errp);
1f862184 IM	369	object_property_add_bool(obj, "memory-hotplug-support",
	370	ich9_pm_get_memory_hotplug_support,
	371	ich9_pm_set_memory_hotplug_support,
	372	NULL);
6ac0d8d4 AS	373	object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8",
	374	ich9_pm_get_disable_s3,
	375	ich9_pm_set_disable_s3,
	376	NULL, pm, NULL);
	377	object_property_add(obj, ACPI_PM_PROP_S4_DISABLED, "uint8",
	378	ich9_pm_get_disable_s4,
	379	ich9_pm_set_disable_s4,
	380	NULL, pm, NULL);
	381	object_property_add(obj, ACPI_PM_PROP_S4_VAL, "uint8",
	382	ich9_pm_get_s4_val,
	383	ich9_pm_set_s4_val,
	384	NULL, pm, NULL);
1f862184 IM	385	}
	386
	387	void ich9_pm_device_plug_cb(ICH9LPCPMRegs pm, DeviceState dev, Error **errp)
	388	{
	389	if (pm->acpi_memory_hotplug.is_enabled &&
	390	object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
	391	acpi_memory_plug_cb(&pm->acpi_regs, pm->irq, &pm->acpi_memory_hotplug,
	392	dev, errp);
c5171ed0 GZ	393	} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
c5171ed0 GZ	394	acpi_cpu_plug_cb(&pm->acpi_regs, pm->irq, &pm->gpe_cpu, dev, errp);
1f862184 IM	395	} else {
	396	error_setg(errp, "acpi: device plug request for not supported device"
	397	" type: %s", object_get_typename(OBJECT(dev)));
	398	}
6f1426ab	399	}
43f50410	400
469b8ad2 TC	401	void ich9_pm_device_unplug_request_cb(ICH9LPCPMRegs pm, DeviceState dev,
	402	Error **errp)
	403	{
64fec58e TC	404	if (pm->acpi_memory_hotplug.is_enabled &&
	405	object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
	406	acpi_memory_unplug_request_cb(&pm->acpi_regs, pm->irq,
	407	&pm->acpi_memory_hotplug, dev, errp);
	408	} else {
	409	error_setg(errp, "acpi: device unplug request for not supported device"
	410	" type: %s", object_get_typename(OBJECT(dev)));
	411	}
469b8ad2 TC	412	}
469b8ad2 TC	413
91a734a6 TC	414	void ich9_pm_device_unplug_cb(ICH9LPCPMRegs pm, DeviceState dev,
	415	Error **errp)
	416	{
f7d3e29d TC	417	if (pm->acpi_memory_hotplug.is_enabled &&
	418	object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
	419	acpi_memory_unplug_cb(&pm->acpi_memory_hotplug, dev, errp);
	420	} else {
	421	error_setg(errp, "acpi: device unplug for not supported device"
	422	" type: %s", object_get_typename(OBJECT(dev)));
	423	}
91a734a6 TC	424	}
91a734a6 TC	425
43f50410 IM	426	void ich9_pm_ospm_status(AcpiDeviceIf adev, ACPIOSTInfoList **list)
	427	{
	428	ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
	429
	430	acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list);
	431	}