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e516572f JB |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
6f918e40 JB |
5 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> |
6 | * VA Linux Systems Japan K.K. | |
7 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
8 | * | |
9 | * This is based on acpi.c. | |
e516572f JB |
10 | * |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
61f3c91a | 13 | * License version 2.1 as published by the Free Software Foundation. |
e516572f JB |
14 | * |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
e516572f | 22 | * |
6f918e40 JB |
23 | * Contributions after 2012-01-13 are licensed under the terms of the |
24 | * GNU GPL, version 2 or (at your option) any later version. | |
e516572f | 25 | */ |
71e8a915 | 26 | |
b6a0aa05 | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
6f1426ab | 29 | #include "qapi/visitor.h" |
83c9f4ca | 30 | #include "hw/pci/pci.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
1de7afc9 | 32 | #include "qemu/timer.h" |
2e5b09fd | 33 | #include "hw/core/cpu.h" |
71e8a915 | 34 | #include "sysemu/reset.h" |
54d31236 | 35 | #include "sysemu/runstate.h" |
0d09e41a | 36 | #include "hw/acpi/acpi.h" |
fbae27e8 | 37 | #include "hw/acpi/ich9_tco.h" |
e516572f | 38 | |
1a6981bb | 39 | #include "hw/southbridge/ich9.h" |
1f862184 | 40 | #include "hw/mem/pc-dimm.h" |
132a908b | 41 | #include "hw/mem/nvdimm.h" |
e516572f JB |
42 | |
43 | //#define DEBUG | |
44 | ||
45 | #ifdef DEBUG | |
46 | #define ICH9_DEBUG(fmt, ...) \ | |
47 | do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) | |
48 | #else | |
49 | #define ICH9_DEBUG(fmt, ...) do { } while (0) | |
50 | #endif | |
51 | ||
e516572f JB |
52 | static void ich9_pm_update_sci_fn(ACPIREGS *regs) |
53 | { | |
54 | ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); | |
06313503 | 55 | acpi_update_sci(&pm->acpi_regs, pm->irq); |
e516572f JB |
56 | } |
57 | ||
76a7daf9 GH |
58 | static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) |
59 | { | |
60 | ICH9LPCPMRegs *pm = opaque; | |
61 | return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); | |
62 | } | |
63 | ||
64 | static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val, | |
65 | unsigned width) | |
66 | { | |
67 | ICH9LPCPMRegs *pm = opaque; | |
68 | acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); | |
2c047956 | 69 | acpi_update_sci(&pm->acpi_regs, pm->irq); |
76a7daf9 GH |
70 | } |
71 | ||
72 | static const MemoryRegionOps ich9_gpe_ops = { | |
73 | .read = ich9_gpe_readb, | |
74 | .write = ich9_gpe_writeb, | |
75 | .valid.min_access_size = 1, | |
76 | .valid.max_access_size = 4, | |
77 | .impl.min_access_size = 1, | |
78 | .impl.max_access_size = 1, | |
79 | .endianness = DEVICE_LITTLE_ENDIAN, | |
80 | }; | |
81 | ||
10cc69b0 GH |
82 | static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) |
83 | { | |
84 | ICH9LPCPMRegs *pm = opaque; | |
85 | switch (addr) { | |
86 | case 0: | |
87 | return pm->smi_en; | |
88 | case 4: | |
89 | return pm->smi_sts; | |
90 | default: | |
91 | return 0; | |
92 | } | |
93 | } | |
94 | ||
95 | static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val, | |
96 | unsigned width) | |
97 | { | |
98 | ICH9LPCPMRegs *pm = opaque; | |
92055797 PA |
99 | TCOIORegs *tr = &pm->tco_regs; |
100 | uint64_t tco_en; | |
101 | ||
10cc69b0 GH |
102 | switch (addr) { |
103 | case 0: | |
92055797 PA |
104 | tco_en = pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN; |
105 | /* once TCO_LOCK bit is set, TCO_EN bit cannot be overwritten */ | |
106 | if (tr->tco.cnt1 & TCO_LOCK) { | |
107 | val = (val & ~ICH9_PMIO_SMI_EN_TCO_EN) | tco_en; | |
108 | } | |
11e66a15 GH |
109 | pm->smi_en &= ~pm->smi_en_wmask; |
110 | pm->smi_en |= (val & pm->smi_en_wmask); | |
10cc69b0 GH |
111 | break; |
112 | } | |
113 | } | |
114 | ||
115 | static const MemoryRegionOps ich9_smi_ops = { | |
116 | .read = ich9_smi_readl, | |
117 | .write = ich9_smi_writel, | |
118 | .valid.min_access_size = 4, | |
119 | .valid.max_access_size = 4, | |
120 | .endianness = DEVICE_LITTLE_ENDIAN, | |
121 | }; | |
122 | ||
e516572f JB |
123 | void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) |
124 | { | |
125 | ICH9_DEBUG("to 0x%x\n", pm_io_base); | |
126 | ||
127 | assert((pm_io_base & ICH9_PMIO_MASK) == 0); | |
128 | ||
e516572f | 129 | pm->pm_io_base = pm_io_base; |
cacaab8b GH |
130 | memory_region_transaction_begin(); |
131 | memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); | |
132 | memory_region_set_address(&pm->io, pm->pm_io_base); | |
133 | memory_region_transaction_commit(); | |
e516572f JB |
134 | } |
135 | ||
136 | static int ich9_pm_post_load(void *opaque, int version_id) | |
137 | { | |
138 | ICH9LPCPMRegs *pm = opaque; | |
139 | uint32_t pm_io_base = pm->pm_io_base; | |
140 | pm->pm_io_base = 0; | |
141 | ich9_pm_iospace_update(pm, pm_io_base); | |
142 | return 0; | |
143 | } | |
144 | ||
145 | #define VMSTATE_GPE_ARRAY(_field, _state) \ | |
146 | { \ | |
147 | .name = (stringify(_field)), \ | |
148 | .version_id = 0, \ | |
149 | .num = ICH9_PMIO_GPE0_LEN, \ | |
150 | .info = &vmstate_info_uint8, \ | |
151 | .size = sizeof(uint8_t), \ | |
152 | .flags = VMS_ARRAY | VMS_POINTER, \ | |
153 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ | |
154 | } | |
155 | ||
f816a62d IM |
156 | static bool vmstate_test_use_memhp(void *opaque) |
157 | { | |
158 | ICH9LPCPMRegs *s = opaque; | |
159 | return s->acpi_memory_hotplug.is_enabled; | |
160 | } | |
161 | ||
162 | static const VMStateDescription vmstate_memhp_state = { | |
163 | .name = "ich9_pm/memhp", | |
164 | .version_id = 1, | |
165 | .minimum_version_id = 1, | |
5cd8cada | 166 | .needed = vmstate_test_use_memhp, |
c559ba57 | 167 | .fields = (const VMStateField[]) { |
f816a62d IM |
168 | VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs), |
169 | VMSTATE_END_OF_LIST() | |
170 | } | |
171 | }; | |
172 | ||
92055797 PA |
173 | static bool vmstate_test_use_tco(void *opaque) |
174 | { | |
175 | ICH9LPCPMRegs *s = opaque; | |
176 | return s->enable_tco; | |
177 | } | |
178 | ||
179 | static const VMStateDescription vmstate_tco_io_state = { | |
180 | .name = "ich9_pm/tco", | |
181 | .version_id = 1, | |
182 | .minimum_version_id = 1, | |
92055797 | 183 | .needed = vmstate_test_use_tco, |
c559ba57 | 184 | .fields = (const VMStateField[]) { |
92055797 PA |
185 | VMSTATE_STRUCT(tco_regs, ICH9LPCPMRegs, 1, vmstate_tco_io_sts, |
186 | TCOIORegs), | |
187 | VMSTATE_END_OF_LIST() | |
188 | } | |
189 | }; | |
190 | ||
679dd1a9 IM |
191 | static bool vmstate_test_use_cpuhp(void *opaque) |
192 | { | |
193 | ICH9LPCPMRegs *s = opaque; | |
194 | return !s->cpu_hotplug_legacy; | |
195 | } | |
196 | ||
197 | static int vmstate_cpuhp_pre_load(void *opaque) | |
198 | { | |
199 | ICH9LPCPMRegs *s = opaque; | |
200 | Object *obj = OBJECT(s->gpe_cpu.device); | |
5325cc34 | 201 | object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); |
679dd1a9 IM |
202 | return 0; |
203 | } | |
204 | ||
205 | static const VMStateDescription vmstate_cpuhp_state = { | |
206 | .name = "ich9_pm/cpuhp", | |
207 | .version_id = 1, | |
208 | .minimum_version_id = 1, | |
679dd1a9 IM |
209 | .needed = vmstate_test_use_cpuhp, |
210 | .pre_load = vmstate_cpuhp_pre_load, | |
c559ba57 | 211 | .fields = (const VMStateField[]) { |
679dd1a9 IM |
212 | VMSTATE_CPU_HOTPLUG(cpuhp_state, ICH9LPCPMRegs), |
213 | VMSTATE_END_OF_LIST() | |
214 | } | |
215 | }; | |
216 | ||
c0e427d6 JS |
217 | static bool vmstate_test_use_pcihp(void *opaque) |
218 | { | |
219 | ICH9LPCPMRegs *s = opaque; | |
220 | ||
6536e427 | 221 | return s->acpi_pci_hotplug.use_acpi_hotplug_bridge; |
c0e427d6 JS |
222 | } |
223 | ||
224 | static const VMStateDescription vmstate_pcihp_state = { | |
225 | .name = "ich9_pm/pcihp", | |
226 | .version_id = 1, | |
227 | .minimum_version_id = 1, | |
228 | .needed = vmstate_test_use_pcihp, | |
c559ba57 | 229 | .fields = (const VMStateField[]) { |
c0e427d6 JS |
230 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, |
231 | ICH9LPCPMRegs, | |
232 | NULL, NULL), | |
233 | VMSTATE_END_OF_LIST() | |
234 | } | |
235 | }; | |
236 | ||
e516572f JB |
237 | const VMStateDescription vmstate_ich9_pm = { |
238 | .name = "ich9_pm", | |
239 | .version_id = 1, | |
240 | .minimum_version_id = 1, | |
e516572f | 241 | .post_load = ich9_pm_post_load, |
c559ba57 | 242 | .fields = (const VMStateField[]) { |
e516572f JB |
243 | VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), |
244 | VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), | |
245 | VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), | |
e720677e | 246 | VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs), |
e516572f JB |
247 | VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), |
248 | VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), | |
249 | VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), | |
250 | VMSTATE_UINT32(smi_en, ICH9LPCPMRegs), | |
251 | VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs), | |
252 | VMSTATE_END_OF_LIST() | |
f816a62d | 253 | }, |
c559ba57 | 254 | .subsections = (const VMStateDescription * const []) { |
5cd8cada | 255 | &vmstate_memhp_state, |
92055797 | 256 | &vmstate_tco_io_state, |
679dd1a9 | 257 | &vmstate_cpuhp_state, |
c0e427d6 | 258 | &vmstate_pcihp_state, |
92055797 | 259 | NULL |
e516572f JB |
260 | } |
261 | }; | |
262 | ||
263 | static void pm_reset(void *opaque) | |
264 | { | |
265 | ICH9LPCPMRegs *pm = opaque; | |
266 | ich9_pm_iospace_update(pm, 0); | |
267 | ||
268 | acpi_pm1_evt_reset(&pm->acpi_regs); | |
269 | acpi_pm1_cnt_reset(&pm->acpi_regs); | |
270 | acpi_pm_tmr_reset(&pm->acpi_regs); | |
271 | acpi_gpe_reset(&pm->acpi_regs); | |
272 | ||
be66680e | 273 | pm->smi_en = 0; |
fba72476 | 274 | if (!pm->smm_enabled) { |
f3c30aea | 275 | /* Mark SMM as already inited to prevent SMM from running. */ |
21bcfdd9 JK |
276 | pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN; |
277 | } | |
11e66a15 | 278 | pm->smi_en_wmask = ~0; |
21bcfdd9 | 279 | |
6536e427 IM |
280 | if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) { |
281 | acpi_pcihp_reset(&pm->acpi_pci_hotplug); | |
c0e427d6 JS |
282 | } |
283 | ||
06313503 | 284 | acpi_update_sci(&pm->acpi_regs, pm->irq); |
e516572f JB |
285 | } |
286 | ||
287 | static void pm_powerdown_req(Notifier *n, void *opaque) | |
288 | { | |
289 | ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier); | |
290 | ||
291 | acpi_pm1_evt_power_down(&pm->acpi_regs); | |
292 | } | |
293 | ||
20fe3af2 | 294 | void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq) |
e516572f | 295 | { |
64bde0f3 | 296 | memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE); |
cacaab8b | 297 | memory_region_set_enabled(&pm->io, false); |
503b19fc GH |
298 | memory_region_add_subregion(pci_address_space_io(lpc_pci), |
299 | 0, &pm->io); | |
cacaab8b | 300 | |
77d58b1e | 301 | acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); |
b5a7c024 | 302 | acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); |
9a10bbb4 | 303 | acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4, |
20fe3af2 | 304 | pm->s4_val, !pm->smm_compat && !pm->smm_enabled); |
76a7daf9 | 305 | |
e516572f | 306 | acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); |
64bde0f3 | 307 | memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, |
75902802 | 308 | "acpi-gpe0", ICH9_PMIO_GPE0_LEN); |
76a7daf9 | 309 | memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe); |
e516572f | 310 | |
64bde0f3 | 311 | memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm, |
75902802 | 312 | "acpi-smi", 8); |
10cc69b0 GH |
313 | memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); |
314 | ||
ee1c08bd DB |
315 | if (pm->enable_tco) { |
316 | acpi_pm_tco_init(&pm->tco_regs, &pm->io); | |
317 | } | |
92055797 | 318 | |
6536e427 | 319 | if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) { |
c0e427d6 JS |
320 | acpi_pcihp_init(OBJECT(lpc_pci), |
321 | &pm->acpi_pci_hotplug, | |
322 | pci_get_bus(lpc_pci), | |
323 | pci_address_space_io(lpc_pci), | |
c0e427d6 JS |
324 | ACPI_PCIHP_ADDR_ICH9); |
325 | ||
326 | qbus_set_hotplug_handler(BUS(pci_get_bus(lpc_pci)), | |
327 | OBJECT(lpc_pci)); | |
328 | } | |
329 | ||
e516572f JB |
330 | pm->irq = sci_irq; |
331 | qemu_register_reset(pm_reset, pm); | |
332 | pm->powerdown_notifier.notify = pm_powerdown_req; | |
333 | qemu_register_powerdown_notifier(&pm->powerdown_notifier); | |
d6610bc2 | 334 | |
96e3e12b IM |
335 | legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), |
336 | OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE); | |
1f862184 IM |
337 | |
338 | if (pm->acpi_memory_hotplug.is_enabled) { | |
339 | acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), | |
80db0e78 IM |
340 | &pm->acpi_memory_hotplug, |
341 | ACPI_MEMORY_HOTPLUG_BASE); | |
1f862184 | 342 | } |
e516572f | 343 | } |
6f1426ab | 344 | |
d7bce999 EB |
345 | static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name, |
346 | void *opaque, Error **errp) | |
6f1426ab MT |
347 | { |
348 | ICH9LPCPMRegs *pm = opaque; | |
349 | uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; | |
350 | ||
51e72bc1 | 351 | visit_type_uint32(v, name, &value, errp); |
6f1426ab MT |
352 | } |
353 | ||
1f862184 IM |
354 | static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp) |
355 | { | |
356 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
357 | ||
358 | return s->pm.acpi_memory_hotplug.is_enabled; | |
359 | } | |
360 | ||
361 | static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value, | |
362 | Error **errp) | |
363 | { | |
364 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
365 | ||
366 | s->pm.acpi_memory_hotplug.is_enabled = value; | |
367 | } | |
368 | ||
16bcab97 IM |
369 | static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp) |
370 | { | |
371 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
372 | ||
373 | return s->pm.cpu_hotplug_legacy; | |
374 | } | |
375 | ||
376 | static void ich9_pm_set_cpu_hotplug_legacy(Object *obj, bool value, | |
377 | Error **errp) | |
378 | { | |
379 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
380 | ||
679dd1a9 IM |
381 | assert(!value); |
382 | if (s->pm.cpu_hotplug_legacy && value == false) { | |
383 | acpi_switch_to_modern_cphp(&s->pm.gpe_cpu, &s->pm.cpuhp_state, | |
384 | ICH9_CPU_HOTPLUG_IO_BASE); | |
385 | } | |
16bcab97 IM |
386 | s->pm.cpu_hotplug_legacy = value; |
387 | } | |
388 | ||
92055797 PA |
389 | static bool ich9_pm_get_enable_tco(Object *obj, Error **errp) |
390 | { | |
391 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
392 | return s->pm.enable_tco; | |
393 | } | |
394 | ||
395 | static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp) | |
396 | { | |
397 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
398 | s->pm.enable_tco = value; | |
399 | } | |
400 | ||
c0e427d6 JS |
401 | static bool ich9_pm_get_acpi_pci_hotplug(Object *obj, Error **errp) |
402 | { | |
403 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
404 | ||
6536e427 | 405 | return s->pm.acpi_pci_hotplug.use_acpi_hotplug_bridge; |
c0e427d6 JS |
406 | } |
407 | ||
408 | static void ich9_pm_set_acpi_pci_hotplug(Object *obj, bool value, Error **errp) | |
409 | { | |
410 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
411 | ||
6536e427 | 412 | s->pm.acpi_pci_hotplug.use_acpi_hotplug_bridge = value; |
c0e427d6 JS |
413 | } |
414 | ||
c318bef7 JS |
415 | static bool ich9_pm_get_keep_pci_slot_hpc(Object *obj, Error **errp) |
416 | { | |
417 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
418 | ||
419 | return s->pm.keep_pci_slot_hpc; | |
420 | } | |
421 | ||
422 | static void ich9_pm_set_keep_pci_slot_hpc(Object *obj, bool value, Error **errp) | |
423 | { | |
424 | ICH9LPCState *s = ICH9_LPC_DEVICE(obj); | |
425 | ||
426 | s->pm.keep_pci_slot_hpc = value; | |
427 | } | |
428 | ||
40c2281c | 429 | void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm) |
6f1426ab MT |
430 | { |
431 | static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; | |
1f862184 | 432 | pm->acpi_memory_hotplug.is_enabled = true; |
16bcab97 | 433 | pm->cpu_hotplug_legacy = true; |
6ac0d8d4 AS |
434 | pm->disable_s3 = 0; |
435 | pm->disable_s4 = 0; | |
436 | pm->s4_val = 2; | |
6536e427 | 437 | pm->acpi_pci_hotplug.use_acpi_hotplug_bridge = true; |
c318bef7 | 438 | pm->keep_pci_slot_hpc = true; |
ee1c08bd | 439 | pm->enable_tco = true; |
6f1426ab MT |
440 | |
441 | object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE, | |
d2623129 | 442 | &pm->pm_io_base, OBJ_PROP_FLAG_READ); |
6f1426ab MT |
443 | object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32", |
444 | ich9_pm_get_gpe0_blk, | |
d2623129 | 445 | NULL, NULL, pm); |
6f1426ab | 446 | object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN, |
d2623129 | 447 | &gpe0_len, OBJ_PROP_FLAG_READ); |
1f862184 IM |
448 | object_property_add_bool(obj, "memory-hotplug-support", |
449 | ich9_pm_get_memory_hotplug_support, | |
d2623129 | 450 | ich9_pm_set_memory_hotplug_support); |
16bcab97 IM |
451 | object_property_add_bool(obj, "cpu-hotplug-legacy", |
452 | ich9_pm_get_cpu_hotplug_legacy, | |
d2623129 | 453 | ich9_pm_set_cpu_hotplug_legacy); |
64a7b8de | 454 | object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED, |
d2623129 | 455 | &pm->disable_s3, OBJ_PROP_FLAG_READWRITE); |
64a7b8de | 456 | object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED, |
d2623129 | 457 | &pm->disable_s4, OBJ_PROP_FLAG_READWRITE); |
64a7b8de | 458 | object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_VAL, |
d2623129 | 459 | &pm->s4_val, OBJ_PROP_FLAG_READWRITE); |
92055797 PA |
460 | object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED, |
461 | ich9_pm_get_enable_tco, | |
d2623129 | 462 | ich9_pm_set_enable_tco); |
aa29466b | 463 | object_property_add_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, |
c0e427d6 JS |
464 | ich9_pm_get_acpi_pci_hotplug, |
465 | ich9_pm_set_acpi_pci_hotplug); | |
c318bef7 JS |
466 | object_property_add_bool(obj, "x-keep-pci-slot-hpc", |
467 | ich9_pm_get_keep_pci_slot_hpc, | |
468 | ich9_pm_set_keep_pci_slot_hpc); | |
1f862184 IM |
469 | } |
470 | ||
9040e6df WY |
471 | void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
472 | Error **errp) | |
473 | { | |
474 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); | |
475 | ||
c0e427d6 JS |
476 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
477 | acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); | |
478 | return; | |
479 | } | |
480 | ||
9040e6df | 481 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && |
c5be7517 | 482 | !lpc->pm.acpi_memory_hotplug.is_enabled) { |
9040e6df WY |
483 | error_setg(errp, |
484 | "memory hotplug is not enabled: %s.memory-hotplug-support " | |
485 | "is not set", object_get_typename(OBJECT(lpc))); | |
c5be7517 IM |
486 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
487 | uint64_t negotiated = lpc->smi_negotiated_features; | |
488 | ||
489 | if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) && | |
490 | !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) { | |
491 | error_setg(errp, "cpu hotplug with SMI wasn't enabled by firmware"); | |
492 | error_append_hint(errp, "update machine type to newer than 5.1 " | |
493 | "and firmware that suppors CPU hotplug with SMM"); | |
494 | } | |
495 | } | |
9040e6df WY |
496 | } |
497 | ||
0058c082 IM |
498 | void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
499 | Error **errp) | |
1f862184 | 500 | { |
0058c082 IM |
501 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); |
502 | ||
9040e6df | 503 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
75f27498 XG |
504 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
505 | nvdimm_acpi_plug_cb(hotplug_dev, dev); | |
506 | } else { | |
507 | acpi_memory_plug_cb(hotplug_dev, &lpc->pm.acpi_memory_hotplug, | |
508 | dev, errp); | |
509 | } | |
5e1b5d93 IM |
510 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
511 | if (lpc->pm.cpu_hotplug_legacy) { | |
512 | legacy_acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.gpe_cpu, dev, errp); | |
513 | } else { | |
514 | acpi_cpu_plug_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); | |
515 | } | |
c0e427d6 JS |
516 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
517 | acpi_pcihp_device_plug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, | |
518 | dev, errp); | |
1f862184 IM |
519 | } else { |
520 | error_setg(errp, "acpi: device plug request for not supported device" | |
521 | " type: %s", object_get_typename(OBJECT(dev))); | |
522 | } | |
6f1426ab | 523 | } |
43f50410 | 524 | |
0058c082 IM |
525 | void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
526 | DeviceState *dev, Error **errp) | |
469b8ad2 | 527 | { |
0058c082 IM |
528 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); |
529 | ||
530 | if (lpc->pm.acpi_memory_hotplug.is_enabled && | |
64fec58e | 531 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
0058c082 IM |
532 | acpi_memory_unplug_request_cb(hotplug_dev, |
533 | &lpc->pm.acpi_memory_hotplug, dev, | |
534 | errp); | |
8872c25a IM |
535 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
536 | !lpc->pm.cpu_hotplug_legacy) { | |
b48ad7c0 IM |
537 | uint64_t negotiated = lpc->smi_negotiated_features; |
538 | ||
539 | if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) && | |
540 | !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) { | |
541 | error_setg(errp, "cpu hot-unplug with SMI wasn't enabled " | |
542 | "by firmware"); | |
543 | error_append_hint(errp, "update machine type to a version having " | |
544 | "x-smi-cpu-hotunplug=on and firmware that " | |
545 | "supports CPU hot-unplug with SMM"); | |
546 | return; | |
547 | } | |
548 | ||
8872c25a IM |
549 | acpi_cpu_unplug_request_cb(hotplug_dev, &lpc->pm.cpuhp_state, |
550 | dev, errp); | |
c0e427d6 JS |
551 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
552 | acpi_pcihp_device_unplug_request_cb(hotplug_dev, | |
553 | &lpc->pm.acpi_pci_hotplug, | |
554 | dev, errp); | |
64fec58e TC |
555 | } else { |
556 | error_setg(errp, "acpi: device unplug request for not supported device" | |
557 | " type: %s", object_get_typename(OBJECT(dev))); | |
558 | } | |
469b8ad2 TC |
559 | } |
560 | ||
0058c082 | 561 | void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
91a734a6 TC |
562 | Error **errp) |
563 | { | |
0058c082 IM |
564 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); |
565 | ||
566 | if (lpc->pm.acpi_memory_hotplug.is_enabled && | |
f7d3e29d | 567 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
0058c082 | 568 | acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp); |
8872c25a IM |
569 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
570 | !lpc->pm.cpu_hotplug_legacy) { | |
571 | acpi_cpu_unplug_cb(&lpc->pm.cpuhp_state, dev, errp); | |
c0e427d6 JS |
572 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
573 | acpi_pcihp_device_unplug_cb(hotplug_dev, &lpc->pm.acpi_pci_hotplug, | |
574 | dev, errp); | |
f7d3e29d TC |
575 | } else { |
576 | error_setg(errp, "acpi: device unplug for not supported device" | |
577 | " type: %s", object_get_typename(OBJECT(dev))); | |
578 | } | |
91a734a6 TC |
579 | } |
580 | ||
f18e29fc IM |
581 | bool ich9_pm_is_hotpluggable_bus(HotplugHandler *hotplug_dev, BusState *bus) |
582 | { | |
583 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); | |
584 | return acpi_pcihp_is_hotpluggbale_bus(&lpc->pm.acpi_pci_hotplug, bus); | |
585 | } | |
586 | ||
43f50410 IM |
587 | void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) |
588 | { | |
589 | ICH9LPCState *s = ICH9_LPC_DEVICE(adev); | |
590 | ||
591 | acpi_memory_ospm_status(&s->pm.acpi_memory_hotplug, list); | |
76623d00 IM |
592 | if (!s->pm.cpu_hotplug_legacy) { |
593 | acpi_cpu_ospm_status(&s->pm.cpuhp_state, list); | |
594 | } | |
43f50410 | 595 | } |