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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
83c9f4ca | 21 | #include "hw/hw.h" |
0d09e41a PB |
22 | #include "hw/i386/pc.h" |
23 | #include "hw/isa/apm.h" | |
24 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 25 | #include "hw/pci/pci.h" |
0d09e41a | 26 | #include "hw/acpi/acpi.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
1de7afc9 | 28 | #include "qemu/range.h" |
022c62cb | 29 | #include "exec/ioport.h" |
0d09e41a | 30 | #include "hw/nvram/fw_cfg.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
277e9340 | 32 | #include "hw/acpi/piix4.h" |
9e047b98 | 33 | #include "hw/acpi/pcihp.h" |
81cea5e7 | 34 | #include "hw/acpi/cpu_hotplug.h" |
93d89f63 IY |
35 | |
36 | //#define DEBUG | |
37 | ||
50d8ff8b IY |
38 | #ifdef DEBUG |
39 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
40 | #else | |
41 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
42 | #endif | |
43 | ||
ac404095 | 44 | #define GPE_BASE 0xafe0 |
23910d3f | 45 | #define GPE_LEN 4 |
c177684c | 46 | |
4441a287 GN |
47 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
48 | ||
ac404095 | 49 | struct pci_status { |
7faa8075 | 50 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
51 | uint32_t down; |
52 | }; | |
53 | ||
93d89f63 | 54 | typedef struct PIIX4PMState { |
6a6b5580 AF |
55 | /*< private >*/ |
56 | PCIDevice parent_obj; | |
57 | /*< public >*/ | |
56e5b2a1 | 58 | |
af11110b | 59 | MemoryRegion io; |
277e9340 MT |
60 | uint32_t io_base; |
61 | ||
b65b93f2 | 62 | MemoryRegion io_gpe; |
355bf2e5 | 63 | ACPIREGS ar; |
93d89f63 IY |
64 | |
65 | APMState apm; | |
66 | ||
93d89f63 | 67 | PMSMBus smb; |
e8ec0571 | 68 | uint32_t smb_io_base; |
93d89f63 IY |
69 | |
70 | qemu_irq irq; | |
93d89f63 IY |
71 | qemu_irq smi_irq; |
72 | int kvm_enabled; | |
6141dbfe | 73 | Notifier machine_ready; |
d010f91c | 74 | Notifier powerdown_notifier; |
ac404095 | 75 | |
9e047b98 MT |
76 | AcpiPciHpState acpi_pci_hotplug; |
77 | bool use_acpi_pci_hotplug; | |
78 | ||
459ae5ea GN |
79 | uint8_t disable_s3; |
80 | uint8_t disable_s4; | |
81 | uint8_t s4_val; | |
b8622725 | 82 | |
81cea5e7 | 83 | AcpiCpuHotplug gpe_cpu; |
b8622725 | 84 | Notifier cpu_added_notifier; |
93d89f63 IY |
85 | } PIIX4PMState; |
86 | ||
74e445f6 PC |
87 | #define TYPE_PIIX4_PM "PIIX4_PM" |
88 | ||
89 | #define PIIX4_PM(obj) \ | |
90 | OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) | |
91 | ||
56e5b2a1 GH |
92 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
93 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 94 | |
93d89f63 IY |
95 | #define ACPI_ENABLE 0xf1 |
96 | #define ACPI_DISABLE 0xf0 | |
97 | ||
355bf2e5 | 98 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 99 | { |
355bf2e5 | 100 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
06313503 | 101 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
102 | } |
103 | ||
93d89f63 IY |
104 | static void apm_ctrl_changed(uint32_t val, void *arg) |
105 | { | |
106 | PIIX4PMState *s = arg; | |
6a6b5580 | 107 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
108 | |
109 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 110 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 | 111 | |
6a6b5580 | 112 | if (d->config[0x5b] & (1 << 1)) { |
93d89f63 IY |
113 | if (s->smi_irq) { |
114 | qemu_irq_raise(s->smi_irq); | |
115 | } | |
116 | } | |
117 | } | |
118 | ||
93d89f63 IY |
119 | static void pm_io_space_update(PIIX4PMState *s) |
120 | { | |
6a6b5580 | 121 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 | 122 | |
277e9340 MT |
123 | s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
124 | s->io_base &= 0xffc0; | |
93d89f63 | 125 | |
af11110b | 126 | memory_region_transaction_begin(); |
6a6b5580 | 127 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
277e9340 | 128 | memory_region_set_address(&s->io, s->io_base); |
af11110b | 129 | memory_region_transaction_commit(); |
93d89f63 IY |
130 | } |
131 | ||
24fe083d GH |
132 | static void smbus_io_space_update(PIIX4PMState *s) |
133 | { | |
6a6b5580 AF |
134 | PCIDevice *d = PCI_DEVICE(s); |
135 | ||
136 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); | |
24fe083d GH |
137 | s->smb_io_base &= 0xffc0; |
138 | ||
139 | memory_region_transaction_begin(); | |
6a6b5580 | 140 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
24fe083d GH |
141 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
142 | memory_region_transaction_commit(); | |
93d89f63 IY |
143 | } |
144 | ||
145 | static void pm_write_config(PCIDevice *d, | |
146 | uint32_t address, uint32_t val, int len) | |
147 | { | |
148 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
149 | if (range_covers_byte(address, len, 0x80) || |
150 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 151 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
152 | } |
153 | if (range_covers_byte(address, len, 0xd2) || | |
154 | ranges_overlap(address, len, 0x90, 4)) { | |
155 | smbus_io_space_update((PIIX4PMState *)d); | |
156 | } | |
93d89f63 IY |
157 | } |
158 | ||
159 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
160 | { | |
161 | PIIX4PMState *s = opaque; | |
162 | ||
163 | pm_io_space_update(s); | |
164 | return 0; | |
165 | } | |
166 | ||
23910d3f IY |
167 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
168 | { \ | |
169 | .name = (stringify(_field)), \ | |
170 | .version_id = 0, \ | |
23910d3f IY |
171 | .info = &vmstate_info_uint16, \ |
172 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 173 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
174 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
175 | } | |
176 | ||
4cf3e6f3 AW |
177 | static const VMStateDescription vmstate_gpe = { |
178 | .name = "gpe", | |
179 | .version_id = 1, | |
180 | .minimum_version_id = 1, | |
181 | .minimum_version_id_old = 1, | |
182 | .fields = (VMStateField []) { | |
23910d3f IY |
183 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
184 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
185 | VMSTATE_END_OF_LIST() |
186 | } | |
187 | }; | |
188 | ||
189 | static const VMStateDescription vmstate_pci_status = { | |
190 | .name = "pci_status", | |
191 | .version_id = 1, | |
192 | .minimum_version_id = 1, | |
193 | .minimum_version_id_old = 1, | |
194 | .fields = (VMStateField []) { | |
e358edc8 IM |
195 | VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), |
196 | VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), | |
4cf3e6f3 AW |
197 | VMSTATE_END_OF_LIST() |
198 | } | |
199 | }; | |
200 | ||
b0b873a0 MT |
201 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
202 | { | |
203 | PIIX4PMState *s = opaque; | |
204 | int ret, i; | |
205 | uint16_t temp; | |
206 | ||
6a6b5580 | 207 | ret = pci_device_load(PCI_DEVICE(s), f); |
b0b873a0 MT |
208 | if (ret < 0) { |
209 | return ret; | |
210 | } | |
211 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
212 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
213 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
214 | ||
ded67782 | 215 | ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); |
b0b873a0 MT |
216 | if (ret) { |
217 | return ret; | |
218 | } | |
219 | ||
40daca54 | 220 | timer_get(f, s->ar.tmr.timer); |
b0b873a0 MT |
221 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); |
222 | ||
223 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
224 | for (i = 0; i < 3; i++) { | |
225 | qemu_get_be16s(f, &temp); | |
226 | } | |
227 | ||
228 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
229 | for (i = 0; i < 3; i++) { | |
230 | qemu_get_be16s(f, &temp); | |
231 | } | |
232 | ||
e358edc8 IM |
233 | ret = vmstate_load_state(f, &vmstate_pci_status, |
234 | &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); | |
b0b873a0 MT |
235 | return ret; |
236 | } | |
237 | ||
9e047b98 MT |
238 | static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) |
239 | { | |
240 | PIIX4PMState *s = opaque; | |
241 | return s->use_acpi_pci_hotplug; | |
242 | } | |
243 | ||
244 | static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) | |
245 | { | |
246 | PIIX4PMState *s = opaque; | |
247 | return !s->use_acpi_pci_hotplug; | |
248 | } | |
249 | ||
b0b873a0 MT |
250 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 |
251 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
252 | * and minimum_version_id to 2 below (which breaks migration from | |
253 | * qemu 1.2). | |
254 | * | |
255 | */ | |
93d89f63 IY |
256 | static const VMStateDescription vmstate_acpi = { |
257 | .name = "piix4_pm", | |
b0b873a0 MT |
258 | .version_id = 3, |
259 | .minimum_version_id = 3, | |
93d89f63 | 260 | .minimum_version_id_old = 1, |
b0b873a0 | 261 | .load_state_old = acpi_load_old, |
93d89f63 IY |
262 | .post_load = vmstate_acpi_post_load, |
263 | .fields = (VMStateField []) { | |
6a6b5580 | 264 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
355bf2e5 GH |
265 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
266 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
267 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 268 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
269 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
270 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
271 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
e358edc8 IM |
272 | VMSTATE_STRUCT_TEST( |
273 | acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], | |
274 | PIIX4PMState, | |
275 | vmstate_test_no_use_acpi_pci_hotplug, | |
276 | 2, vmstate_pci_status, | |
277 | struct AcpiPciHpPciStatus), | |
9e047b98 MT |
278 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, |
279 | vmstate_test_use_acpi_pci_hotplug), | |
93d89f63 IY |
280 | VMSTATE_END_OF_LIST() |
281 | } | |
282 | }; | |
283 | ||
284 | static void piix4_reset(void *opaque) | |
285 | { | |
286 | PIIX4PMState *s = opaque; | |
6a6b5580 AF |
287 | PCIDevice *d = PCI_DEVICE(s); |
288 | uint8_t *pci_conf = d->config; | |
93d89f63 IY |
289 | |
290 | pci_conf[0x58] = 0; | |
291 | pci_conf[0x59] = 0; | |
292 | pci_conf[0x5a] = 0; | |
293 | pci_conf[0x5b] = 0; | |
294 | ||
4d09d37c GN |
295 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
296 | pci_conf[0x80] = 0; | |
297 | ||
93d89f63 IY |
298 | if (s->kvm_enabled) { |
299 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
300 | pci_conf[0x5B] = 0x02; | |
301 | } | |
c046e8c4 | 302 | pm_io_space_update(s); |
e358edc8 | 303 | acpi_pcihp_reset(&s->acpi_pci_hotplug); |
93d89f63 IY |
304 | } |
305 | ||
d010f91c | 306 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 307 | { |
d010f91c | 308 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 309 | |
355bf2e5 GH |
310 | assert(s != NULL); |
311 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
312 | } |
313 | ||
9e047b98 MT |
314 | static int piix4_acpi_pci_hotplug(DeviceState *qdev, PCIDevice *dev, |
315 | PCIHotplugState state) | |
316 | { | |
317 | PIIX4PMState *s = PIIX4_PM(qdev); | |
318 | int ret = acpi_pcihp_device_hotplug(&s->acpi_pci_hotplug, dev, state); | |
319 | if (ret < 0) { | |
320 | return ret; | |
321 | } | |
322 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; | |
323 | ||
324 | acpi_update_sci(&s->ar, s->irq); | |
325 | return 0; | |
326 | } | |
327 | ||
328 | static void piix4_update_bus_hotplug(PCIBus *bus, void *opaque) | |
329 | { | |
330 | PIIX4PMState *s = opaque; | |
331 | pci_bus_hotplug(bus, piix4_acpi_pci_hotplug, DEVICE(s)); | |
332 | } | |
333 | ||
9e8dd451 | 334 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
335 | { |
336 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
6a6b5580 AF |
337 | PCIDevice *d = PCI_DEVICE(s); |
338 | MemoryRegion *io_as = pci_address_space_io(d); | |
6141dbfe PB |
339 | uint8_t *pci_conf; |
340 | ||
6a6b5580 | 341 | pci_conf = d->config; |
b6f32962 | 342 | pci_conf[0x5f] = 0x10 | |
3ce10901 | 343 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
6141dbfe | 344 | pci_conf[0x63] = 0x60; |
3ce10901 PB |
345 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
346 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); | |
9e047b98 MT |
347 | |
348 | if (s->use_acpi_pci_hotplug) { | |
349 | pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); | |
e358edc8 IM |
350 | } else { |
351 | piix4_update_bus_hotplug(d->bus, s); | |
9e047b98 | 352 | } |
6141dbfe PB |
353 | } |
354 | ||
277e9340 MT |
355 | static void piix4_pm_add_propeties(PIIX4PMState *s) |
356 | { | |
357 | static const uint8_t acpi_enable_cmd = ACPI_ENABLE; | |
358 | static const uint8_t acpi_disable_cmd = ACPI_DISABLE; | |
359 | static const uint32_t gpe0_blk = GPE_BASE; | |
360 | static const uint32_t gpe0_blk_len = GPE_LEN; | |
361 | static const uint16_t sci_int = 9; | |
362 | ||
363 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
364 | &acpi_enable_cmd, NULL); | |
365 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
366 | &acpi_disable_cmd, NULL); | |
367 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, | |
368 | &gpe0_blk, NULL); | |
369 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, | |
370 | &gpe0_blk_len, NULL); | |
371 | object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, | |
372 | &sci_int, NULL); | |
373 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, | |
374 | &s->io_base, NULL); | |
375 | } | |
376 | ||
e8ec0571 | 377 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 378 | { |
74e445f6 | 379 | PIIX4PMState *s = PIIX4_PM(dev); |
93d89f63 IY |
380 | uint8_t *pci_conf; |
381 | ||
6a6b5580 | 382 | pci_conf = dev->config; |
93d89f63 IY |
383 | pci_conf[0x06] = 0x80; |
384 | pci_conf[0x07] = 0x02; | |
93d89f63 | 385 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
386 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
387 | ||
93d89f63 | 388 | /* APM */ |
42d8a3cf | 389 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 390 | |
93d89f63 IY |
391 | if (s->kvm_enabled) { |
392 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
393 | * support SMM mode. */ | |
394 | pci_conf[0x5B] = 0x02; | |
395 | } | |
396 | ||
397 | /* XXX: which specification is used ? The i82731AB has different | |
398 | mappings */ | |
e8ec0571 IY |
399 | pci_conf[0x90] = s->smb_io_base | 1; |
400 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 401 | pci_conf[0xd2] = 0x09; |
74e445f6 | 402 | pm_smbus_init(DEVICE(dev), &s->smb); |
24fe083d | 403 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
404 | memory_region_add_subregion(pci_address_space_io(dev), |
405 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 406 | |
64bde0f3 | 407 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
af11110b | 408 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
409 | memory_region_add_subregion(pci_address_space_io(dev), |
410 | 0, &s->io); | |
93d89f63 | 411 | |
77d58b1e | 412 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 413 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
560e6396 | 414 | acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val); |
355bf2e5 | 415 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 416 | |
d010f91c IM |
417 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
418 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 419 | |
6141dbfe PB |
420 | s->machine_ready.notify = piix4_pm_machine_ready; |
421 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 422 | qemu_register_reset(piix4_reset, s); |
56e5b2a1 GH |
423 | |
424 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); | |
e8ec0571 | 425 | |
277e9340 | 426 | piix4_pm_add_propeties(s); |
e8ec0571 IY |
427 | return 0; |
428 | } | |
429 | ||
277e9340 MT |
430 | Object *piix4_pm_find(void) |
431 | { | |
432 | bool ambig; | |
433 | Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); | |
434 | ||
435 | if (ambig || !o) { | |
436 | return NULL; | |
437 | } | |
438 | return o; | |
439 | } | |
440 | ||
e8ec0571 | 441 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
da98c8eb | 442 | qemu_irq sci_irq, qemu_irq smi_irq, |
a88b362c | 443 | int kvm_enabled, FWCfgState *fw_cfg) |
e8ec0571 | 444 | { |
74e445f6 | 445 | DeviceState *dev; |
e8ec0571 IY |
446 | PIIX4PMState *s; |
447 | ||
74e445f6 PC |
448 | dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); |
449 | qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); | |
93d89f63 | 450 | |
74e445f6 | 451 | s = PIIX4_PM(dev); |
93d89f63 | 452 | s->irq = sci_irq; |
93d89f63 | 453 | s->smi_irq = smi_irq; |
e8ec0571 IY |
454 | s->kvm_enabled = kvm_enabled; |
455 | ||
74e445f6 | 456 | qdev_init_nofail(dev); |
93d89f63 | 457 | |
459ae5ea GN |
458 | if (fw_cfg) { |
459 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
460 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
461 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
462 | ||
463 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
464 | } | |
465 | ||
93d89f63 IY |
466 | return s->smb.smbus; |
467 | } | |
468 | ||
b65b93f2 | 469 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 470 | { |
633aa0ac | 471 | PIIX4PMState *s = opaque; |
355bf2e5 | 472 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 473 | |
ba275adb | 474 | PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); |
93d89f63 IY |
475 | return val; |
476 | } | |
477 | ||
b65b93f2 GH |
478 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
479 | unsigned width) | |
93d89f63 | 480 | { |
633aa0ac | 481 | PIIX4PMState *s = opaque; |
633aa0ac | 482 | |
355bf2e5 | 483 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
06313503 | 484 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 | 485 | |
ba275adb | 486 | PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); |
93d89f63 IY |
487 | } |
488 | ||
b65b93f2 GH |
489 | static const MemoryRegionOps piix4_gpe_ops = { |
490 | .read = gpe_readb, | |
491 | .write = gpe_writeb, | |
492 | .valid.min_access_size = 1, | |
493 | .valid.max_access_size = 4, | |
494 | .impl.min_access_size = 1, | |
495 | .impl.max_access_size = 1, | |
496 | .endianness = DEVICE_LITTLE_ENDIAN, | |
497 | }; | |
498 | ||
b8622725 IM |
499 | static void piix4_cpu_added_req(Notifier *n, void *opaque) |
500 | { | |
501 | PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier); | |
502 | ||
81cea5e7 IM |
503 | assert(s != NULL); |
504 | AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque)); | |
505 | acpi_update_sci(&s->ar, s->irq); | |
b8622725 IM |
506 | } |
507 | ||
56e5b2a1 GH |
508 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
509 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 510 | { |
64bde0f3 PB |
511 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
512 | "acpi-gpe0", GPE_LEN); | |
56e5b2a1 | 513 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 514 | |
e358edc8 IM |
515 | acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent, |
516 | s->use_acpi_pci_hotplug); | |
b8622725 | 517 | |
e4cf8ed0 IM |
518 | AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu, |
519 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
b8622725 IM |
520 | s->cpu_added_notifier.notify = piix4_cpu_added_req; |
521 | qemu_register_cpu_added_notifier(&s->cpu_added_notifier); | |
93d89f63 | 522 | } |
5fdae20c IM |
523 | |
524 | static Property piix4_pm_properties[] = { | |
525 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
526 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), | |
527 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), | |
528 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), | |
529 | DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, | |
530 | use_acpi_pci_hotplug, true), | |
531 | DEFINE_PROP_END_OF_LIST(), | |
532 | }; | |
533 | ||
534 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
535 | { | |
536 | DeviceClass *dc = DEVICE_CLASS(klass); | |
537 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
538 | ||
539 | k->no_hotplug = 1; | |
540 | k->init = piix4_pm_initfn; | |
541 | k->config_write = pm_write_config; | |
542 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
543 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
544 | k->revision = 0x03; | |
545 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
546 | dc->desc = "PM"; | |
547 | dc->vmsd = &vmstate_acpi; | |
548 | dc->props = piix4_pm_properties; | |
549 | /* | |
550 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
551 | * e.g. by mips_malta_init() | |
552 | */ | |
553 | dc->cannot_instantiate_with_device_add_yet = true; | |
554 | } | |
555 | ||
556 | static const TypeInfo piix4_pm_info = { | |
557 | .name = TYPE_PIIX4_PM, | |
558 | .parent = TYPE_PCI_DEVICE, | |
559 | .instance_size = sizeof(PIIX4PMState), | |
560 | .class_init = piix4_pm_class_init, | |
561 | }; | |
562 | ||
563 | static void piix4_pm_register_types(void) | |
564 | { | |
565 | type_register_static(&piix4_pm_info); | |
566 | } | |
567 | ||
568 | type_init(piix4_pm_register_types) |