]>
Commit | Line | Data |
---|---|---|
93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
b6a0aa05 | 21 | #include "qemu/osdep.h" |
83c9f4ca | 22 | #include "hw/hw.h" |
0d09e41a PB |
23 | #include "hw/i386/pc.h" |
24 | #include "hw/isa/apm.h" | |
25 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 26 | #include "hw/pci/pci.h" |
0d09e41a | 27 | #include "hw/acpi/acpi.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
da34e65c | 29 | #include "qapi/error.h" |
1de7afc9 | 30 | #include "qemu/range.h" |
022c62cb | 31 | #include "exec/ioport.h" |
0d09e41a | 32 | #include "hw/nvram/fw_cfg.h" |
022c62cb | 33 | #include "exec/address-spaces.h" |
277e9340 | 34 | #include "hw/acpi/piix4.h" |
9e047b98 | 35 | #include "hw/acpi/pcihp.h" |
81cea5e7 | 36 | #include "hw/acpi/cpu_hotplug.h" |
c24d5e0b | 37 | #include "hw/hotplug.h" |
34774320 IM |
38 | #include "hw/mem/pc-dimm.h" |
39 | #include "hw/acpi/memory_hotplug.h" | |
43f50410 | 40 | #include "hw/acpi/acpi_dev_interface.h" |
91ab2ed7 | 41 | #include "hw/xen/xen.h" |
93d89f63 IY |
42 | |
43 | //#define DEBUG | |
44 | ||
50d8ff8b IY |
45 | #ifdef DEBUG |
46 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
47 | #else | |
48 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
49 | #endif | |
50 | ||
ac404095 | 51 | #define GPE_BASE 0xafe0 |
23910d3f | 52 | #define GPE_LEN 4 |
c177684c | 53 | |
ac404095 | 54 | struct pci_status { |
7faa8075 | 55 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
56 | uint32_t down; |
57 | }; | |
58 | ||
93d89f63 | 59 | typedef struct PIIX4PMState { |
6a6b5580 AF |
60 | /*< private >*/ |
61 | PCIDevice parent_obj; | |
62 | /*< public >*/ | |
56e5b2a1 | 63 | |
af11110b | 64 | MemoryRegion io; |
277e9340 MT |
65 | uint32_t io_base; |
66 | ||
b65b93f2 | 67 | MemoryRegion io_gpe; |
355bf2e5 | 68 | ACPIREGS ar; |
93d89f63 IY |
69 | |
70 | APMState apm; | |
71 | ||
93d89f63 | 72 | PMSMBus smb; |
e8ec0571 | 73 | uint32_t smb_io_base; |
93d89f63 IY |
74 | |
75 | qemu_irq irq; | |
93d89f63 | 76 | qemu_irq smi_irq; |
61e66c62 | 77 | int smm_enabled; |
6141dbfe | 78 | Notifier machine_ready; |
d010f91c | 79 | Notifier powerdown_notifier; |
ac404095 | 80 | |
9e047b98 MT |
81 | AcpiPciHpState acpi_pci_hotplug; |
82 | bool use_acpi_pci_hotplug; | |
83 | ||
459ae5ea GN |
84 | uint8_t disable_s3; |
85 | uint8_t disable_s4; | |
86 | uint8_t s4_val; | |
b8622725 | 87 | |
81cea5e7 | 88 | AcpiCpuHotplug gpe_cpu; |
34774320 IM |
89 | |
90 | MemHotplugState acpi_memory_hotplug; | |
93d89f63 IY |
91 | } PIIX4PMState; |
92 | ||
74e445f6 PC |
93 | #define TYPE_PIIX4_PM "PIIX4_PM" |
94 | ||
95 | #define PIIX4_PM(obj) \ | |
96 | OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) | |
97 | ||
56e5b2a1 GH |
98 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
99 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 100 | |
93d89f63 IY |
101 | #define ACPI_ENABLE 0xf1 |
102 | #define ACPI_DISABLE 0xf0 | |
103 | ||
355bf2e5 | 104 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 105 | { |
355bf2e5 | 106 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
06313503 | 107 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
108 | } |
109 | ||
93d89f63 IY |
110 | static void apm_ctrl_changed(uint32_t val, void *arg) |
111 | { | |
112 | PIIX4PMState *s = arg; | |
6a6b5580 | 113 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
114 | |
115 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 116 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
afd6895b PB |
117 | if (val == ACPI_ENABLE || val == ACPI_DISABLE) { |
118 | return; | |
119 | } | |
93d89f63 | 120 | |
6a6b5580 | 121 | if (d->config[0x5b] & (1 << 1)) { |
93d89f63 IY |
122 | if (s->smi_irq) { |
123 | qemu_irq_raise(s->smi_irq); | |
124 | } | |
125 | } | |
126 | } | |
127 | ||
93d89f63 IY |
128 | static void pm_io_space_update(PIIX4PMState *s) |
129 | { | |
6a6b5580 | 130 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 | 131 | |
277e9340 MT |
132 | s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
133 | s->io_base &= 0xffc0; | |
93d89f63 | 134 | |
af11110b | 135 | memory_region_transaction_begin(); |
6a6b5580 | 136 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
277e9340 | 137 | memory_region_set_address(&s->io, s->io_base); |
af11110b | 138 | memory_region_transaction_commit(); |
93d89f63 IY |
139 | } |
140 | ||
24fe083d GH |
141 | static void smbus_io_space_update(PIIX4PMState *s) |
142 | { | |
6a6b5580 AF |
143 | PCIDevice *d = PCI_DEVICE(s); |
144 | ||
145 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); | |
24fe083d GH |
146 | s->smb_io_base &= 0xffc0; |
147 | ||
148 | memory_region_transaction_begin(); | |
6a6b5580 | 149 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
24fe083d GH |
150 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
151 | memory_region_transaction_commit(); | |
93d89f63 IY |
152 | } |
153 | ||
154 | static void pm_write_config(PCIDevice *d, | |
155 | uint32_t address, uint32_t val, int len) | |
156 | { | |
157 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
158 | if (range_covers_byte(address, len, 0x80) || |
159 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 160 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
161 | } |
162 | if (range_covers_byte(address, len, 0xd2) || | |
163 | ranges_overlap(address, len, 0x90, 4)) { | |
164 | smbus_io_space_update((PIIX4PMState *)d); | |
165 | } | |
93d89f63 IY |
166 | } |
167 | ||
168 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
169 | { | |
170 | PIIX4PMState *s = opaque; | |
171 | ||
172 | pm_io_space_update(s); | |
173 | return 0; | |
174 | } | |
175 | ||
23910d3f IY |
176 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
177 | { \ | |
178 | .name = (stringify(_field)), \ | |
179 | .version_id = 0, \ | |
23910d3f IY |
180 | .info = &vmstate_info_uint16, \ |
181 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 182 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
183 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
184 | } | |
185 | ||
4cf3e6f3 AW |
186 | static const VMStateDescription vmstate_gpe = { |
187 | .name = "gpe", | |
188 | .version_id = 1, | |
189 | .minimum_version_id = 1, | |
d49805ae | 190 | .fields = (VMStateField[]) { |
23910d3f IY |
191 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
192 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
193 | VMSTATE_END_OF_LIST() |
194 | } | |
195 | }; | |
196 | ||
197 | static const VMStateDescription vmstate_pci_status = { | |
198 | .name = "pci_status", | |
199 | .version_id = 1, | |
200 | .minimum_version_id = 1, | |
d49805ae | 201 | .fields = (VMStateField[]) { |
e358edc8 IM |
202 | VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), |
203 | VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), | |
4cf3e6f3 AW |
204 | VMSTATE_END_OF_LIST() |
205 | } | |
206 | }; | |
207 | ||
b0b873a0 MT |
208 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
209 | { | |
210 | PIIX4PMState *s = opaque; | |
211 | int ret, i; | |
212 | uint16_t temp; | |
213 | ||
6a6b5580 | 214 | ret = pci_device_load(PCI_DEVICE(s), f); |
b0b873a0 MT |
215 | if (ret < 0) { |
216 | return ret; | |
217 | } | |
218 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
219 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
220 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
221 | ||
ded67782 | 222 | ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); |
b0b873a0 MT |
223 | if (ret) { |
224 | return ret; | |
225 | } | |
226 | ||
40daca54 | 227 | timer_get(f, s->ar.tmr.timer); |
b0b873a0 MT |
228 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); |
229 | ||
230 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
231 | for (i = 0; i < 3; i++) { | |
232 | qemu_get_be16s(f, &temp); | |
233 | } | |
234 | ||
235 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
236 | for (i = 0; i < 3; i++) { | |
237 | qemu_get_be16s(f, &temp); | |
238 | } | |
239 | ||
e358edc8 IM |
240 | ret = vmstate_load_state(f, &vmstate_pci_status, |
241 | &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); | |
b0b873a0 MT |
242 | return ret; |
243 | } | |
244 | ||
9e047b98 MT |
245 | static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) |
246 | { | |
247 | PIIX4PMState *s = opaque; | |
248 | return s->use_acpi_pci_hotplug; | |
249 | } | |
250 | ||
251 | static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) | |
252 | { | |
253 | PIIX4PMState *s = opaque; | |
254 | return !s->use_acpi_pci_hotplug; | |
255 | } | |
256 | ||
f816a62d IM |
257 | static bool vmstate_test_use_memhp(void *opaque) |
258 | { | |
259 | PIIX4PMState *s = opaque; | |
260 | return s->acpi_memory_hotplug.is_enabled; | |
261 | } | |
262 | ||
263 | static const VMStateDescription vmstate_memhp_state = { | |
264 | .name = "piix4_pm/memhp", | |
265 | .version_id = 1, | |
266 | .minimum_version_id = 1, | |
267 | .minimum_version_id_old = 1, | |
5cd8cada | 268 | .needed = vmstate_test_use_memhp, |
f816a62d IM |
269 | .fields = (VMStateField[]) { |
270 | VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), | |
271 | VMSTATE_END_OF_LIST() | |
272 | } | |
273 | }; | |
274 | ||
b0b873a0 MT |
275 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 |
276 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
277 | * and minimum_version_id to 2 below (which breaks migration from | |
278 | * qemu 1.2). | |
279 | * | |
280 | */ | |
93d89f63 IY |
281 | static const VMStateDescription vmstate_acpi = { |
282 | .name = "piix4_pm", | |
b0b873a0 MT |
283 | .version_id = 3, |
284 | .minimum_version_id = 3, | |
93d89f63 | 285 | .minimum_version_id_old = 1, |
b0b873a0 | 286 | .load_state_old = acpi_load_old, |
93d89f63 | 287 | .post_load = vmstate_acpi_post_load, |
d49805ae | 288 | .fields = (VMStateField[]) { |
6a6b5580 | 289 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
355bf2e5 GH |
290 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
291 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
292 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 293 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
e720677e | 294 | VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), |
355bf2e5 GH |
295 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
296 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
e358edc8 IM |
297 | VMSTATE_STRUCT_TEST( |
298 | acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], | |
299 | PIIX4PMState, | |
300 | vmstate_test_no_use_acpi_pci_hotplug, | |
301 | 2, vmstate_pci_status, | |
302 | struct AcpiPciHpPciStatus), | |
9e047b98 MT |
303 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, |
304 | vmstate_test_use_acpi_pci_hotplug), | |
93d89f63 | 305 | VMSTATE_END_OF_LIST() |
f816a62d | 306 | }, |
5cd8cada JQ |
307 | .subsections = (const VMStateDescription*[]) { |
308 | &vmstate_memhp_state, | |
309 | NULL | |
93d89f63 IY |
310 | } |
311 | }; | |
312 | ||
313 | static void piix4_reset(void *opaque) | |
314 | { | |
315 | PIIX4PMState *s = opaque; | |
6a6b5580 AF |
316 | PCIDevice *d = PCI_DEVICE(s); |
317 | uint8_t *pci_conf = d->config; | |
93d89f63 IY |
318 | |
319 | pci_conf[0x58] = 0; | |
320 | pci_conf[0x59] = 0; | |
321 | pci_conf[0x5a] = 0; | |
322 | pci_conf[0x5b] = 0; | |
323 | ||
4d09d37c GN |
324 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
325 | pci_conf[0x80] = 0; | |
326 | ||
61e66c62 | 327 | if (!s->smm_enabled) { |
93d89f63 IY |
328 | /* Mark SMM as already inited (until KVM supports SMM). */ |
329 | pci_conf[0x5B] = 0x02; | |
330 | } | |
c046e8c4 | 331 | pm_io_space_update(s); |
e358edc8 | 332 | acpi_pcihp_reset(&s->acpi_pci_hotplug); |
93d89f63 IY |
333 | } |
334 | ||
d010f91c | 335 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 336 | { |
d010f91c | 337 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 338 | |
355bf2e5 GH |
339 | assert(s != NULL); |
340 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
341 | } |
342 | ||
f1adc360 IM |
343 | static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, |
344 | DeviceState *dev, Error **errp) | |
9e047b98 | 345 | { |
c24d5e0b | 346 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
f1adc360 | 347 | |
34774320 IM |
348 | if (s->acpi_memory_hotplug.is_enabled && |
349 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
350 | acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp); | |
351 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { | |
f1adc360 IM |
352 | acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, |
353 | errp); | |
08bba95b GZ |
354 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
355 | acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp); | |
f1adc360 IM |
356 | } else { |
357 | error_setg(errp, "acpi: device plug request for not supported device" | |
358 | " type: %s", object_get_typename(OBJECT(dev))); | |
359 | } | |
c24d5e0b | 360 | } |
9e047b98 | 361 | |
14d5a28f IM |
362 | static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
363 | DeviceState *dev, Error **errp) | |
c24d5e0b IM |
364 | { |
365 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); | |
f1adc360 | 366 | |
64fec58e TC |
367 | if (s->acpi_memory_hotplug.is_enabled && |
368 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
369 | acpi_memory_unplug_request_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, | |
370 | dev, errp); | |
371 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { | |
f1adc360 IM |
372 | acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, |
373 | errp); | |
374 | } else { | |
375 | error_setg(errp, "acpi: device unplug request for not supported device" | |
376 | " type: %s", object_get_typename(OBJECT(dev))); | |
377 | } | |
9e047b98 MT |
378 | } |
379 | ||
c0e57a60 TC |
380 | static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, |
381 | DeviceState *dev, Error **errp) | |
382 | { | |
f7d3e29d TC |
383 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
384 | ||
385 | if (s->acpi_memory_hotplug.is_enabled && | |
386 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
387 | acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); | |
388 | } else { | |
389 | error_setg(errp, "acpi: device unplug for not supported device" | |
390 | " type: %s", object_get_typename(OBJECT(dev))); | |
391 | } | |
c0e57a60 TC |
392 | } |
393 | ||
c24d5e0b | 394 | static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque) |
9e047b98 MT |
395 | { |
396 | PIIX4PMState *s = opaque; | |
c24d5e0b IM |
397 | |
398 | qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort); | |
9e047b98 MT |
399 | } |
400 | ||
9e8dd451 | 401 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
402 | { |
403 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
6a6b5580 AF |
404 | PCIDevice *d = PCI_DEVICE(s); |
405 | MemoryRegion *io_as = pci_address_space_io(d); | |
6141dbfe PB |
406 | uint8_t *pci_conf; |
407 | ||
6a6b5580 | 408 | pci_conf = d->config; |
b6f32962 | 409 | pci_conf[0x5f] = 0x10 | |
3ce10901 | 410 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
6141dbfe | 411 | pci_conf[0x63] = 0x60; |
3ce10901 PB |
412 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
413 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); | |
9e047b98 MT |
414 | |
415 | if (s->use_acpi_pci_hotplug) { | |
416 | pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s); | |
e358edc8 IM |
417 | } else { |
418 | piix4_update_bus_hotplug(d->bus, s); | |
9e047b98 | 419 | } |
6141dbfe PB |
420 | } |
421 | ||
277e9340 MT |
422 | static void piix4_pm_add_propeties(PIIX4PMState *s) |
423 | { | |
424 | static const uint8_t acpi_enable_cmd = ACPI_ENABLE; | |
425 | static const uint8_t acpi_disable_cmd = ACPI_DISABLE; | |
426 | static const uint32_t gpe0_blk = GPE_BASE; | |
427 | static const uint32_t gpe0_blk_len = GPE_LEN; | |
428 | static const uint16_t sci_int = 9; | |
429 | ||
430 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
431 | &acpi_enable_cmd, NULL); | |
432 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
433 | &acpi_disable_cmd, NULL); | |
434 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, | |
435 | &gpe0_blk, NULL); | |
436 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, | |
437 | &gpe0_blk_len, NULL); | |
438 | object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, | |
439 | &sci_int, NULL); | |
440 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, | |
441 | &s->io_base, NULL); | |
442 | } | |
443 | ||
9af21dbe | 444 | static void piix4_pm_realize(PCIDevice *dev, Error **errp) |
93d89f63 | 445 | { |
74e445f6 | 446 | PIIX4PMState *s = PIIX4_PM(dev); |
93d89f63 IY |
447 | uint8_t *pci_conf; |
448 | ||
6a6b5580 | 449 | pci_conf = dev->config; |
93d89f63 IY |
450 | pci_conf[0x06] = 0x80; |
451 | pci_conf[0x07] = 0x02; | |
93d89f63 | 452 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
453 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
454 | ||
93d89f63 | 455 | /* APM */ |
42d8a3cf | 456 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 457 | |
61e66c62 | 458 | if (!s->smm_enabled) { |
93d89f63 IY |
459 | /* Mark SMM as already inited to prevent SMM from running. KVM does not |
460 | * support SMM mode. */ | |
461 | pci_conf[0x5B] = 0x02; | |
462 | } | |
463 | ||
464 | /* XXX: which specification is used ? The i82731AB has different | |
465 | mappings */ | |
e8ec0571 IY |
466 | pci_conf[0x90] = s->smb_io_base | 1; |
467 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 468 | pci_conf[0xd2] = 0x09; |
74e445f6 | 469 | pm_smbus_init(DEVICE(dev), &s->smb); |
24fe083d | 470 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
471 | memory_region_add_subregion(pci_address_space_io(dev), |
472 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 473 | |
64bde0f3 | 474 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
af11110b | 475 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
476 | memory_region_add_subregion(pci_address_space_io(dev), |
477 | 0, &s->io); | |
93d89f63 | 478 | |
77d58b1e | 479 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 480 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 481 | acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); |
355bf2e5 | 482 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 483 | |
d010f91c IM |
484 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
485 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 486 | |
6141dbfe PB |
487 | s->machine_ready.notify = piix4_pm_machine_ready; |
488 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 489 | qemu_register_reset(piix4_reset, s); |
56e5b2a1 GH |
490 | |
491 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s); | |
e8ec0571 | 492 | |
277e9340 | 493 | piix4_pm_add_propeties(s); |
e8ec0571 IY |
494 | } |
495 | ||
277e9340 MT |
496 | Object *piix4_pm_find(void) |
497 | { | |
498 | bool ambig; | |
499 | Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig); | |
500 | ||
501 | if (ambig || !o) { | |
502 | return NULL; | |
503 | } | |
504 | return o; | |
505 | } | |
506 | ||
a5c82852 AF |
507 | I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
508 | qemu_irq sci_irq, qemu_irq smi_irq, | |
61e66c62 | 509 | int smm_enabled, DeviceState **piix4_pm) |
e8ec0571 | 510 | { |
74e445f6 | 511 | DeviceState *dev; |
e8ec0571 IY |
512 | PIIX4PMState *s; |
513 | ||
74e445f6 PC |
514 | dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); |
515 | qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); | |
781bbd6b IM |
516 | if (piix4_pm) { |
517 | *piix4_pm = dev; | |
518 | } | |
93d89f63 | 519 | |
74e445f6 | 520 | s = PIIX4_PM(dev); |
93d89f63 | 521 | s->irq = sci_irq; |
93d89f63 | 522 | s->smi_irq = smi_irq; |
61e66c62 | 523 | s->smm_enabled = smm_enabled; |
91ab2ed7 IM |
524 | if (xen_enabled()) { |
525 | s->use_acpi_pci_hotplug = false; | |
526 | } | |
e8ec0571 | 527 | |
74e445f6 | 528 | qdev_init_nofail(dev); |
93d89f63 IY |
529 | |
530 | return s->smb.smbus; | |
531 | } | |
532 | ||
b65b93f2 | 533 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 534 | { |
633aa0ac | 535 | PIIX4PMState *s = opaque; |
355bf2e5 | 536 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 537 | |
ba275adb | 538 | PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); |
93d89f63 IY |
539 | return val; |
540 | } | |
541 | ||
b65b93f2 GH |
542 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
543 | unsigned width) | |
93d89f63 | 544 | { |
633aa0ac | 545 | PIIX4PMState *s = opaque; |
633aa0ac | 546 | |
355bf2e5 | 547 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
06313503 | 548 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 | 549 | |
ba275adb | 550 | PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); |
93d89f63 IY |
551 | } |
552 | ||
b65b93f2 GH |
553 | static const MemoryRegionOps piix4_gpe_ops = { |
554 | .read = gpe_readb, | |
555 | .write = gpe_writeb, | |
556 | .valid.min_access_size = 1, | |
557 | .valid.max_access_size = 4, | |
558 | .impl.min_access_size = 1, | |
559 | .impl.max_access_size = 1, | |
560 | .endianness = DEVICE_LITTLE_ENDIAN, | |
561 | }; | |
562 | ||
56e5b2a1 GH |
563 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
564 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 565 | { |
64bde0f3 PB |
566 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
567 | "acpi-gpe0", GPE_LEN); | |
56e5b2a1 | 568 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 569 | |
78c2d872 | 570 | acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, |
e358edc8 | 571 | s->use_acpi_pci_hotplug); |
b8622725 | 572 | |
411b5db8 GZ |
573 | acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, |
574 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
34774320 IM |
575 | |
576 | if (s->acpi_memory_hotplug.is_enabled) { | |
577 | acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug); | |
578 | } | |
93d89f63 | 579 | } |
5fdae20c | 580 | |
43f50410 IM |
581 | static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) |
582 | { | |
583 | PIIX4PMState *s = PIIX4_PM(adev); | |
584 | ||
585 | acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); | |
586 | } | |
587 | ||
5fdae20c IM |
588 | static Property piix4_pm_properties[] = { |
589 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
590 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), | |
591 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), | |
592 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), | |
593 | DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, | |
594 | use_acpi_pci_hotplug, true), | |
34774320 IM |
595 | DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, |
596 | acpi_memory_hotplug.is_enabled, true), | |
5fdae20c IM |
597 | DEFINE_PROP_END_OF_LIST(), |
598 | }; | |
599 | ||
600 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
601 | { | |
602 | DeviceClass *dc = DEVICE_CLASS(klass); | |
603 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
c24d5e0b | 604 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
43f50410 | 605 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
5fdae20c | 606 | |
9af21dbe | 607 | k->realize = piix4_pm_realize; |
5fdae20c IM |
608 | k->config_write = pm_write_config; |
609 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
610 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
611 | k->revision = 0x03; | |
612 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
613 | dc->desc = "PM"; | |
614 | dc->vmsd = &vmstate_acpi; | |
615 | dc->props = piix4_pm_properties; | |
616 | /* | |
617 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
618 | * e.g. by mips_malta_init() | |
619 | */ | |
620 | dc->cannot_instantiate_with_device_add_yet = true; | |
2897ae02 | 621 | dc->hotpluggable = false; |
f1adc360 | 622 | hc->plug = piix4_device_plug_cb; |
14d5a28f | 623 | hc->unplug_request = piix4_device_unplug_request_cb; |
c0e57a60 | 624 | hc->unplug = piix4_device_unplug_cb; |
43f50410 | 625 | adevc->ospm_status = piix4_ospm_status; |
5fdae20c IM |
626 | } |
627 | ||
628 | static const TypeInfo piix4_pm_info = { | |
629 | .name = TYPE_PIIX4_PM, | |
630 | .parent = TYPE_PCI_DEVICE, | |
631 | .instance_size = sizeof(PIIX4PMState), | |
632 | .class_init = piix4_pm_class_init, | |
c24d5e0b IM |
633 | .interfaces = (InterfaceInfo[]) { |
634 | { TYPE_HOTPLUG_HANDLER }, | |
43f50410 | 635 | { TYPE_ACPI_DEVICE_IF }, |
c24d5e0b IM |
636 | { } |
637 | } | |
5fdae20c IM |
638 | }; |
639 | ||
640 | static void piix4_pm_register_types(void) | |
641 | { | |
642 | type_register_static(&piix4_pm_info); | |
643 | } | |
644 | ||
645 | type_init(piix4_pm_register_types) |