[mirror_qemu.git] / hw / acpi.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "vl.h"

//#define DEBUG

/* i82731AB (PIIX4) compatible power management function */
#define PM_FREQ 3579545

#define ACPI_DBG_IO_ADDR  0xb044

typedef struct PIIX4PMState {
    PCIDevice dev;
    uint16_t pmsts;
    uint16_t pmen;
    uint16_t pmcntrl;
    uint8_t apmc;
    uint8_t apms;
    QEMUTimer *tmr_timer;
    int64_t tmr_overflow_time;
    i2c_bus *smbus;
    uint8_t smb_stat;
    uint8_t smb_ctl;
    uint8_t smb_cmd;
    uint8_t smb_addr;
    uint8_t smb_data0;
    uint8_t smb_data1;
    uint8_t smb_data[32];
    uint8_t smb_index;
} PIIX4PMState;

#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)

#define SCI_EN (1 << 0)

#define SUS_EN (1 << 13)

#define ACPI_ENABLE 0xf1
#define ACPI_DISABLE 0xf0

#define SMBHSTSTS 0x00
#define SMBHSTCNT 0x02
#define SMBHSTCMD 0x03
#define SMBHSTADD 0x04
#define SMBHSTDAT0 0x05
#define SMBHSTDAT1 0x06
#define SMBBLKDAT 0x07

static uint32_t get_pmtmr(PIIX4PMState *s)
{
    uint32_t d;
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
    return d & 0xffffff;
}

static int get_pmsts(PIIX4PMState *s)
{
    int64_t d;
    int pmsts;
    pmsts = s->pmsts;
    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
    if (d >= s->tmr_overflow_time)
        s->pmsts |= TMROF_EN;
    return pmsts;
}

static void pm_update_sci(PIIX4PMState *s)
{
    int sci_level, pmsts;
    int64_t expire_time;
   
    pmsts = get_pmsts(s);
    sci_level = (((pmsts & s->pmen) &
                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
    qemu_set_irq(s->dev.irq[0], sci_level);
    /* schedule a timer interruption if needed */
    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
        expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
        qemu_mod_timer(s->tmr_timer, expire_time);
    } else {
        qemu_del_timer(s->tmr_timer);
    }
}

static void pm_tmr_timer(void *opaque)
{
    PIIX4PMState *s = opaque;
    pm_update_sci(s);
}

static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        {
            int64_t d;
            int pmsts;
            pmsts = get_pmsts(s);
            if (pmsts & val & TMROF_EN) {
                /* if TMRSTS is reset, then compute the new overflow time */
                d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
            }
            s->pmsts &= ~val;
            pm_update_sci(s);
        }
        break;
    case 0x02:
        s->pmen = val;
        pm_update_sci(s);
        break;
    case 0x04:
        {
            int sus_typ;
            s->pmcntrl = val & ~(SUS_EN);
            if (val & SUS_EN) {
                /* change suspend type */
                sus_typ = (val >> 10) & 3;
                switch(sus_typ) {
                case 0: /* soft power off */
                    qemu_system_shutdown_request();
                    break;
                default:
                    break;
                }
            }
        }
        break;
    default:
        break;
    }
#ifdef DEBUG
    printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
#endif
}

static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x00:
        val = get_pmsts(s);
        break;
    case 0x02:
        val = s->pmen;
        break;
    case 0x04:
        val = s->pmcntrl;
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
#endif
    return val;
}

static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
    //    PIIX4PMState *s = opaque;
    addr &= 0x3f;
#ifdef DEBUG
    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
#endif
}

static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case 0x08:
        val = get_pmtmr(s);
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
#endif
    return val;
}

static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 1;
#ifdef DEBUG
    printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
#endif
    if (addr == 0) {
        s->apmc = val;

        /* ACPI specs 3.0, 4.7.2.5 */
        if (val == ACPI_ENABLE) {
            s->pmcntrl |= SCI_EN;
        } else if (val == ACPI_DISABLE) {
            s->pmcntrl &= ~SCI_EN;
        }

        if (s->dev.config[0x5b] & (1 << 1)) {
            cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
        }
    } else {
        s->apms = val;
    }
}

static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;
   
    addr &= 1;
    if (addr == 0) {
        val = s->apmc;
    } else {
        val = s->apms;
    }
#ifdef DEBUG
    printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
#endif
    return val;
}

static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
{
#if defined(DEBUG)
    printf("ACPI: DBG: 0x%08x\n", val);
#endif
}

static void smb_transaction(PIIX4PMState *s)
{
    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
    uint8_t read = s->smb_addr & 0x01;
    uint8_t cmd = s->smb_cmd;
    uint8_t addr = s->smb_addr >> 1;
    i2c_bus *bus = s->smbus;

#ifdef DEBUG
    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
#endif
    switch(prot) {
    case 0x0:
        smbus_quick_command(bus, addr, read);
        break;
    case 0x1:
        if (read) {
            s->smb_data0 = smbus_receive_byte(bus, addr);
        } else {
            smbus_send_byte(bus, addr, cmd);
        }
        break;
    case 0x2:
        if (read) {
            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
        } else {
            smbus_write_byte(bus, addr, cmd, s->smb_data0);
        }
        break;
    case 0x3:
        if (read) {
            uint16_t val;
            val = smbus_read_word(bus, addr, cmd);
            s->smb_data0 = val;
            s->smb_data1 = val >> 8;
        } else {
            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
        }
        break;
    case 0x5:
        if (read) {
            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
        } else {
            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
        }
        break;
    default:
        goto error;
    }
    return;

  error:
    s->smb_stat |= 0x04;
}

static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    addr &= 0x3f;
#ifdef DEBUG
    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
#endif
    switch(addr) {
    case SMBHSTSTS:
        s->smb_stat = 0;
        s->smb_index = 0;
        break;
    case SMBHSTCNT:
        s->smb_ctl = val;
        if (val & 0x40)
            smb_transaction(s);
        break;
    case SMBHSTCMD:
        s->smb_cmd = val;
        break;
    case SMBHSTADD:
        s->smb_addr = val;
        break;
    case SMBHSTDAT0:
        s->smb_data0 = val;
        break;
    case SMBHSTDAT1:
        s->smb_data1 = val;
        break;
    case SMBBLKDAT:
        s->smb_data[s->smb_index++] = val;
        if (s->smb_index > 31)
            s->smb_index = 0;
        break;
    default:
        break;
    }
}

static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;
    uint32_t val;

    addr &= 0x3f;
    switch(addr) {
    case SMBHSTSTS:
        val = s->smb_stat;
        break;
    case SMBHSTCNT:
        s->smb_index = 0;
        val = s->smb_ctl & 0x1f;
        break;
    case SMBHSTCMD:
        val = s->smb_cmd;
        break;
    case SMBHSTADD:
        val = s->smb_addr;
        break;
    case SMBHSTDAT0:
        val = s->smb_data0;
        break;
    case SMBHSTDAT1:
        val = s->smb_data1;
        break;
    case SMBBLKDAT:
        val = s->smb_data[s->smb_index++];
        if (s->smb_index > 31)
            s->smb_index = 0;
        break;
    default:
        val = 0;
        break;
    }
#ifdef DEBUG
    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
#endif
    return val;
}

static void pm_io_space_update(PIIX4PMState *s)
{
    uint32_t pm_io_base;

    if (s->dev.config[0x80] & 1) {
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
        pm_io_base &= 0xfffe;

        /* XXX: need to improve memory and ioport allocation */
#if defined(DEBUG)
        printf("PM: mapping to 0x%x\n", pm_io_base);
#endif
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
    }
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
    if (address == 0x80)
        pm_io_space_update((PIIX4PMState *)d);
}

static void pm_save(QEMUFile* f,void *opaque)
{
    PIIX4PMState *s = opaque;

    pci_device_save(&s->dev, f);

    qemu_put_be16s(f, &s->pmsts);
    qemu_put_be16s(f, &s->pmen);
    qemu_put_be16s(f, &s->pmcntrl);
    qemu_put_8s(f, &s->apmc);
    qemu_put_8s(f, &s->apms);
    qemu_put_timer(f, s->tmr_timer);
    qemu_put_be64s(f, &s->tmr_overflow_time);
}

static int pm_load(QEMUFile* f,void* opaque,int version_id)
{
    PIIX4PMState *s = opaque;
    int ret;

    if (version_id > 1)
        return -EINVAL;

    ret = pci_device_load(&s->dev, f);
    if (ret < 0)
        return ret;

    qemu_get_be16s(f, &s->pmsts);
    qemu_get_be16s(f, &s->pmen);
    qemu_get_be16s(f, &s->pmcntrl);
    qemu_get_8s(f, &s->apmc);
    qemu_get_8s(f, &s->apms);
    qemu_get_timer(f, s->tmr_timer);
    qemu_get_be64s(f, &s->tmr_overflow_time);

    pm_io_space_update(s);

    return 0;
}

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
    PIIX4PMState *s;
    uint8_t *pci_conf;

    s = (PIIX4PMState *)pci_register_device(bus,
                                         "PM", sizeof(PIIX4PMState),
                                         devfn, NULL, pm_write_config);
    pci_conf = s->dev.config;
    pci_conf[0x00] = 0x86;
    pci_conf[0x01] = 0x80;
    pci_conf[0x02] = 0x13;
    pci_conf[0x03] = 0x71;
    pci_conf[0x08] = 0x00; // revision number
    pci_conf[0x09] = 0x00;
    pci_conf[0x0a] = 0x80; // other bridge device
    pci_conf[0x0b] = 0x06; // bridge device
    pci_conf[0x0e] = 0x00; // header_type
    pci_conf[0x3d] = 0x01; // interrupt pin 1
   
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
   
    register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
    register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);

    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);

    /* XXX: which specification is used ? The i82731AB has different
       mappings */
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
    pci_conf[0x63] = 0x60;
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
	(serial_hds[1] != NULL ? 0x90 : 0);

    pci_conf[0x90] = smb_io_base | 1;
    pci_conf[0x91] = smb_io_base >> 8;
    pci_conf[0xd2] = 0x09;
    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);

    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);

    register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);

    s->smbus = i2c_init_bus();
    return s->smbus;
}
Commit	Line	Data
6515b203 FB	1	/*
6515b203 FB	2	* ACPI implementation
5fafdf24	3	*
6515b203	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
6515b203 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19	#include "vl.h"
	20
	21	//#define DEBUG
	22
	23	/* i82731AB (PIIX4) compatible power management function */
	24	#define PM_FREQ 3579545
	25
6515b203 FB	26	#define ACPI_DBG_IO_ADDR 0xb044
	27
	28	typedef struct PIIX4PMState {
	29	PCIDevice dev;
	30	uint16_t pmsts;
	31	uint16_t pmen;
	32	uint16_t pmcntrl;
ab1e34ad FB	33	uint8_t apmc;
ab1e34ad FB	34	uint8_t apms;
6515b203 FB	35	QEMUTimer *tmr_timer;
6515b203 FB	36	int64_t tmr_overflow_time;
0ff596d0	37	i2c_bus *smbus;
3fffc223 TS	38	uint8_t smb_stat;
	39	uint8_t smb_ctl;
	40	uint8_t smb_cmd;
	41	uint8_t smb_addr;
	42	uint8_t smb_data0;
	43	uint8_t smb_data1;
	44	uint8_t smb_data[32];
	45	uint8_t smb_index;
6515b203 FB	46	} PIIX4PMState;
	47
	48	#define RTC_EN (1 << 10)
	49	#define PWRBTN_EN (1 << 8)
	50	#define GBL_EN (1 << 5)
	51	#define TMROF_EN (1 << 0)
	52
	53	#define SCI_EN (1 << 0)
	54
	55	#define SUS_EN (1 << 13)
	56
24bc1cbc TS	57	#define ACPI_ENABLE 0xf1
	58	#define ACPI_DISABLE 0xf0
	59
3fffc223 TS	60	#define SMBHSTSTS 0x00
	61	#define SMBHSTCNT 0x02
	62	#define SMBHSTCMD 0x03
	63	#define SMBHSTADD 0x04
	64	#define SMBHSTDAT0 0x05
	65	#define SMBHSTDAT1 0x06
	66	#define SMBBLKDAT 0x07
	67
6515b203 FB	68	static uint32_t get_pmtmr(PIIX4PMState *s)
	69	{
	70	uint32_t d;
	71	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	72	return d & 0xffffff;
	73	}
	74
	75	static int get_pmsts(PIIX4PMState *s)
	76	{
	77	int64_t d;
	78	int pmsts;
	79	pmsts = s->pmsts;
	80	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	81	if (d >= s->tmr_overflow_time)
	82	s->pmsts \|= TMROF_EN;
	83	return pmsts;
	84	}
	85
	86	static void pm_update_sci(PIIX4PMState *s)
	87	{
	88	int sci_level, pmsts;
	89	int64_t expire_time;
5fafdf24	90
6515b203	91	pmsts = get_pmsts(s);
5fafdf24	92	sci_level = (((pmsts & s->pmen) &
6515b203	93	(RTC_EN \| PWRBTN_EN \| GBL_EN \| TMROF_EN)) != 0);
d537cf6c	94	qemu_set_irq(s->dev.irq[0], sci_level);
6515b203 FB	95	/* schedule a timer interruption if needed */
	96	if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
	97	expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
	98	qemu_mod_timer(s->tmr_timer, expire_time);
	99	} else {
	100	qemu_del_timer(s->tmr_timer);
	101	}
	102	}
	103
	104	static void pm_tmr_timer(void *opaque)
	105	{
	106	PIIX4PMState *s = opaque;
	107	pm_update_sci(s);
	108	}
	109
	110	static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	111	{
	112	PIIX4PMState *s = opaque;
	113	addr &= 0x3f;
	114	switch(addr) {
	115	case 0x00:
	116	{
	117	int64_t d;
	118	int pmsts;
	119	pmsts = get_pmsts(s);
	120	if (pmsts & val & TMROF_EN) {
	121	/* if TMRSTS is reset, then compute the new overflow time */
	122	d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
	123	s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
	124	}
	125	s->pmsts &= ~val;
	126	pm_update_sci(s);
	127	}
	128	break;
	129	case 0x02:
	130	s->pmen = val;
	131	pm_update_sci(s);
	132	break;
	133	case 0x04:
	134	{
	135	int sus_typ;
	136	s->pmcntrl = val & ~(SUS_EN);
	137	if (val & SUS_EN) {
	138	/* change suspend type */
	139	sus_typ = (val >> 10) & 3;
	140	switch(sus_typ) {
	141	case 0: /* soft power off */
	142	qemu_system_shutdown_request();
	143	break;
	144	default:
	145	break;
	146	}
	147	}
	148	}
	149	break;
	150	default:
	151	break;
	152	}
	153	#ifdef DEBUG
	154	printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
	155	#endif
	156	}
	157
	158	static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
159	{
160	PIIX4PMState *s = opaque;
161	uint32_t val;
162
163	addr &= 0x3f;
164	switch(addr) {
165	case 0x00:
166	val = get_pmsts(s);
167	break;
168	case 0x02:
169	val = s->pmen;
170	break;
171	case 0x04:
172	val = s->pmcntrl;
173	break;
174	default:
175	val = 0;
176	break;
177	}
178	#ifdef DEBUG
179	printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
180	#endif
181	return val;
182	}
183
184	static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
185	{
186	// PIIX4PMState *s = opaque;
187	addr &= 0x3f;
188	#ifdef DEBUG
189	printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
190	#endif
191	}
192
193	static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
194	{
195	PIIX4PMState *s = opaque;
196	uint32_t val;
197
198	addr &= 0x3f;
199	switch(addr) {
200	case 0x08:
201	val = get_pmtmr(s);
202	break;
203	default:
204	val = 0;
205	break;
206	}
207	#ifdef DEBUG
208	printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
209	#endif
210	return val;
211	}
212
ab1e34ad	213	static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
6515b203 FB	214	{
6515b203 FB	215	PIIX4PMState *s = opaque;
ab1e34ad	216	addr &= 1;
6515b203	217	#ifdef DEBUG
ab1e34ad	218	printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
6515b203	219	#endif
ab1e34ad FB	220	if (addr == 0) {
ab1e34ad FB	221	s->apmc = val;
24bc1cbc TS	222
	223	/* ACPI specs 3.0, 4.7.2.5 */
	224	if (val == ACPI_ENABLE) {
	225	s->pmcntrl \|= SCI_EN;
	226	} else if (val == ACPI_DISABLE) {
	227	s->pmcntrl &= ~SCI_EN;
	228	}
	229
47d02f6d FB	230	if (s->dev.config[0x5b] & (1 << 1)) {
47d02f6d FB	231	cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
ab1e34ad	232	}
ab1e34ad FB	233	} else {
ab1e34ad FB	234	s->apms = val;
6515b203 FB	235	}
	236	}
	237
ab1e34ad FB	238	static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
	239	{
	240	PIIX4PMState *s = opaque;
	241	uint32_t val;
5fafdf24	242
ab1e34ad FB	243	addr &= 1;
	244	if (addr == 0) {
	245	val = s->apmc;
	246	} else {
	247	val = s->apms;
	248	}
	249	#ifdef DEBUG
	250	printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
	251	#endif
	252	return val;
	253	}
	254
6515b203 FB	255	static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
	256	{
	257	#if defined(DEBUG)
	258	printf("ACPI: DBG: 0x%08x\n", val);
	259	#endif
	260	}
	261
3fffc223 TS	262	static void smb_transaction(PIIX4PMState *s)
	263	{
	264	uint8_t prot = (s->smb_ctl >> 2) & 0x07;
	265	uint8_t read = s->smb_addr & 0x01;
	266	uint8_t cmd = s->smb_cmd;
	267	uint8_t addr = s->smb_addr >> 1;
0ff596d0	268	i2c_bus *bus = s->smbus;
3fffc223 TS	269
	270	#ifdef DEBUG
	271	printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
	272	#endif
3fffc223 TS	273	switch(prot) {
3fffc223 TS	274	case 0x0:
0ff596d0	275	smbus_quick_command(bus, addr, read);
3fffc223 TS	276	break;
	277	case 0x1:
	278	if (read) {
0ff596d0 PB	279	s->smb_data0 = smbus_receive_byte(bus, addr);
	280	} else {
	281	smbus_send_byte(bus, addr, cmd);
3fffc223 TS	282	}
	283	break;
	284	case 0x2:
	285	if (read) {
0ff596d0 PB	286	s->smb_data0 = smbus_read_byte(bus, addr, cmd);
	287	} else {
	288	smbus_write_byte(bus, addr, cmd, s->smb_data0);
3fffc223 TS	289	}
	290	break;
	291	case 0x3:
	292	if (read) {
	293	uint16_t val;
0ff596d0	294	val = smbus_read_word(bus, addr, cmd);
3fffc223 TS	295	s->smb_data0 = val;
3fffc223 TS	296	s->smb_data1 = val >> 8;
0ff596d0 PB	297	} else {
0ff596d0 PB	298	smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) \| s->smb_data0);
3fffc223 TS	299	}
	300	break;
	301	case 0x5:
	302	if (read) {
0ff596d0 PB	303	s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
	304	} else {
	305	smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
3fffc223 TS	306	}
	307	break;
	308	default:
	309	goto error;
	310	}
	311	return;
	312
	313	error:
	314	s->smb_stat \|= 0x04;
	315	}
	316
	317	static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	318	{
	319	PIIX4PMState *s = opaque;
	320	addr &= 0x3f;
	321	#ifdef DEBUG
	322	printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
	323	#endif
	324	switch(addr) {
	325	case SMBHSTSTS:
	326	s->smb_stat = 0;
	327	s->smb_index = 0;
	328	break;
	329	case SMBHSTCNT:
	330	s->smb_ctl = val;
	331	if (val & 0x40)
	332	smb_transaction(s);
	333	break;
	334	case SMBHSTCMD:
	335	s->smb_cmd = val;
	336	break;
	337	case SMBHSTADD:
	338	s->smb_addr = val;
	339	break;
	340	case SMBHSTDAT0:
	341	s->smb_data0 = val;
	342	break;
	343	case SMBHSTDAT1:
	344	s->smb_data1 = val;
	345	break;
	346	case SMBBLKDAT:
	347	s->smb_data[s->smb_index++] = val;
	348	if (s->smb_index > 31)
	349	s->smb_index = 0;
	350	break;
	351	default:
	352	break;
	353	}
	354	}
	355
	356	static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
	357	{
	358	PIIX4PMState *s = opaque;
	359	uint32_t val;
	360
	361	addr &= 0x3f;
	362	switch(addr) {
	363	case SMBHSTSTS:
	364	val = s->smb_stat;
	365	break;
	366	case SMBHSTCNT:
	367	s->smb_index = 0;
	368	val = s->smb_ctl & 0x1f;
	369	break;
370	case SMBHSTCMD:
371	val = s->smb_cmd;
372	break;
373	case SMBHSTADD:
374	val = s->smb_addr;
375	break;
376	case SMBHSTDAT0:
377	val = s->smb_data0;
378	break;
379	case SMBHSTDAT1:
380	val = s->smb_data1;
381	break;
382	case SMBBLKDAT:
383	val = s->smb_data[s->smb_index++];
384	if (s->smb_index > 31)
385	s->smb_index = 0;
386	break;
387	default:
388	val = 0;
389	break;
390	}
391	#ifdef DEBUG
392	printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
393	#endif
394	return val;
395	}
396
ab1e34ad FB	397	static void pm_io_space_update(PIIX4PMState *s)
	398	{
	399	uint32_t pm_io_base;
	400
	401	if (s->dev.config[0x80] & 1) {
	402	pm_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x40));
	403	pm_io_base &= 0xfffe;
	404
	405	/* XXX: need to improve memory and ioport allocation */
	406	#if defined(DEBUG)
	407	printf("PM: mapping to 0x%x\n", pm_io_base);
	408	#endif
	409	register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
	410	register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
	411	register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
	412	register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
	413	}
	414	}
	415
5fafdf24	416	static void pm_write_config(PCIDevice *d,
ab1e34ad FB	417	uint32_t address, uint32_t val, int len)
	418	{
	419	pci_default_write_config(d, address, val, len);
	420	if (address == 0x80)
	421	pm_io_space_update((PIIX4PMState *)d);
	422	}
	423
	424	static void pm_save(QEMUFile* f,void *opaque)
	425	{
	426	PIIX4PMState *s = opaque;
	427
	428	pci_device_save(&s->dev, f);
	429
	430	qemu_put_be16s(f, &s->pmsts);
	431	qemu_put_be16s(f, &s->pmen);
	432	qemu_put_be16s(f, &s->pmcntrl);
	433	qemu_put_8s(f, &s->apmc);
	434	qemu_put_8s(f, &s->apms);
	435	qemu_put_timer(f, s->tmr_timer);
	436	qemu_put_be64s(f, &s->tmr_overflow_time);
	437	}
	438
	439	static int pm_load(QEMUFile* f,void* opaque,int version_id)
	440	{
	441	PIIX4PMState *s = opaque;
	442	int ret;
	443
	444	if (version_id > 1)
	445	return -EINVAL;
	446
	447	ret = pci_device_load(&s->dev, f);
	448	if (ret < 0)
	449	return ret;
	450
	451	qemu_get_be16s(f, &s->pmsts);
	452	qemu_get_be16s(f, &s->pmen);
	453	qemu_get_be16s(f, &s->pmcntrl);
	454	qemu_get_8s(f, &s->apmc);
	455	qemu_get_8s(f, &s->apms);
	456	qemu_get_timer(f, s->tmr_timer);
	457	qemu_get_be64s(f, &s->tmr_overflow_time);
	458
	459	pm_io_space_update(s);
	460
	461	return 0;
	462	}
	463
7b717336	464	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base)
6515b203 FB	465	{
	466	PIIX4PMState *s;
	467	uint8_t *pci_conf;
6515b203 FB	468
	469	s = (PIIX4PMState *)pci_register_device(bus,
	470	"PM", sizeof(PIIX4PMState),
ab1e34ad	471	devfn, NULL, pm_write_config);
6515b203 FB	472	pci_conf = s->dev.config;
	473	pci_conf[0x00] = 0x86;
	474	pci_conf[0x01] = 0x80;
	475	pci_conf[0x02] = 0x13;
7ef4da1c	476	pci_conf[0x03] = 0x71;
6515b203 FB	477	pci_conf[0x08] = 0x00; // revision number
	478	pci_conf[0x09] = 0x00;
	479	pci_conf[0x0a] = 0x80; // other bridge device
	480	pci_conf[0x0b] = 0x06; // bridge device
	481	pci_conf[0x0e] = 0x00; // header_type
	482	pci_conf[0x3d] = 0x01; // interrupt pin 1
5fafdf24	483
ab1e34ad	484	pci_conf[0x40] = 0x01; /* PM io base read only bit */
5fafdf24	485
ab1e34ad FB	486	register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
	487	register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
	488
6515b203 FB	489	register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
6515b203 FB	490
1ce549ab FB	491	/* XXX: which specification is used ? The i82731AB has different
	492	mappings */
	493	pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) \| 0x10;
	494	pci_conf[0x63] = 0x60;
	495	pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) \|
	496	(serial_hds[1] != NULL ? 0x90 : 0);
	497
3fffc223 TS	498	pci_conf[0x90] = smb_io_base \| 1;
	499	pci_conf[0x91] = smb_io_base >> 8;
	500	pci_conf[0xd2] = 0x09;
	501	register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
	502	register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
	503
6515b203	504	s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
6515b203	505
ab1e34ad	506	register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
3fffc223	507
0ff596d0 PB	508	s->smbus = i2c_init_bus();
0ff596d0 PB	509	return s->smbus;
6515b203	510	}