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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "pci.h" | |
93d89f63 | 26 | #include "acpi.h" |
666daa68 | 27 | #include "sysemu.h" |
bf1b0071 | 28 | #include "range.h" |
6141dbfe | 29 | #include "ioport.h" |
459ae5ea | 30 | #include "fw_cfg.h" |
93d89f63 IY |
31 | |
32 | //#define DEBUG | |
33 | ||
50d8ff8b IY |
34 | #ifdef DEBUG |
35 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
36 | #else | |
37 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
38 | #endif | |
39 | ||
93d89f63 IY |
40 | #define ACPI_DBG_IO_ADDR 0xb044 |
41 | ||
ac404095 | 42 | #define GPE_BASE 0xafe0 |
23910d3f | 43 | #define GPE_LEN 4 |
ba737541 AW |
44 | #define PCI_UP_BASE 0xae00 |
45 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 46 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 47 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 48 | |
4441a287 GN |
49 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
50 | ||
ac404095 | 51 | struct pci_status { |
7faa8075 | 52 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
53 | uint32_t down; |
54 | }; | |
55 | ||
93d89f63 IY |
56 | typedef struct PIIX4PMState { |
57 | PCIDevice dev; | |
2871a3f6 | 58 | IORange ioport; |
355bf2e5 | 59 | ACPIREGS ar; |
93d89f63 IY |
60 | |
61 | APMState apm; | |
62 | ||
93d89f63 | 63 | PMSMBus smb; |
e8ec0571 | 64 | uint32_t smb_io_base; |
93d89f63 IY |
65 | |
66 | qemu_irq irq; | |
93d89f63 IY |
67 | qemu_irq smi_irq; |
68 | int kvm_enabled; | |
6141dbfe | 69 | Notifier machine_ready; |
ac404095 IY |
70 | |
71 | /* for pci hotplug */ | |
ac404095 | 72 | struct pci_status pci0_status; |
668643b0 | 73 | uint32_t pci0_hotplug_enable; |
7faa8075 | 74 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
75 | |
76 | uint8_t disable_s3; | |
77 | uint8_t disable_s4; | |
78 | uint8_t s4_val; | |
93d89f63 IY |
79 | } PIIX4PMState; |
80 | ||
ac404095 IY |
81 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
82 | ||
93d89f63 IY |
83 | #define ACPI_ENABLE 0xf1 |
84 | #define ACPI_DISABLE 0xf0 | |
85 | ||
93d89f63 IY |
86 | static void pm_update_sci(PIIX4PMState *s) |
87 | { | |
88 | int sci_level, pmsts; | |
93d89f63 | 89 | |
2886be1b | 90 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 91 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
92 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
93 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
94 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 95 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
96 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
97 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 98 | |
93d89f63 IY |
99 | qemu_set_irq(s->irq, sci_level); |
100 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 101 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 102 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
103 | } |
104 | ||
355bf2e5 | 105 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 106 | { |
355bf2e5 | 107 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
108 | pm_update_sci(s); |
109 | } | |
110 | ||
2871a3f6 AK |
111 | static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
112 | uint64_t val) | |
93d89f63 | 113 | { |
2871a3f6 AK |
114 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
115 | ||
116 | if (width != 2) { | |
117 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
118 | (unsigned)addr, width, (unsigned)val); | |
119 | } | |
120 | ||
93d89f63 IY |
121 | switch(addr) { |
122 | case 0x00: | |
355bf2e5 | 123 | acpi_pm1_evt_write_sts(&s->ar, val); |
04dc308f | 124 | pm_update_sci(s); |
93d89f63 IY |
125 | break; |
126 | case 0x02: | |
8283c4f5 | 127 | acpi_pm1_evt_write_en(&s->ar, val); |
93d89f63 IY |
128 | pm_update_sci(s); |
129 | break; | |
130 | case 0x04: | |
459ae5ea | 131 | acpi_pm1_cnt_write(&s->ar, val, s->s4_val); |
93d89f63 IY |
132 | break; |
133 | default: | |
134 | break; | |
135 | } | |
59df4c11 WC |
136 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
137 | (unsigned int)val); | |
93d89f63 IY |
138 | } |
139 | ||
2871a3f6 AK |
140 | static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
141 | uint64_t *data) | |
93d89f63 | 142 | { |
2871a3f6 | 143 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
93d89f63 IY |
144 | uint32_t val; |
145 | ||
93d89f63 IY |
146 | switch(addr) { |
147 | case 0x00: | |
2886be1b | 148 | val = acpi_pm1_evt_get_sts(&s->ar); |
93d89f63 IY |
149 | break; |
150 | case 0x02: | |
355bf2e5 | 151 | val = s->ar.pm1.evt.en; |
93d89f63 IY |
152 | break; |
153 | case 0x04: | |
355bf2e5 | 154 | val = s->ar.pm1.cnt.cnt; |
93d89f63 | 155 | break; |
93d89f63 | 156 | case 0x08: |
355bf2e5 | 157 | val = acpi_pm_tmr_get(&s->ar); |
93d89f63 IY |
158 | break; |
159 | default: | |
160 | val = 0; | |
161 | break; | |
162 | } | |
59df4c11 | 163 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
2871a3f6 | 164 | *data = val; |
93d89f63 IY |
165 | } |
166 | ||
2871a3f6 AK |
167 | static const IORangeOps pm_iorange_ops = { |
168 | .read = pm_ioport_read, | |
169 | .write = pm_ioport_write, | |
170 | }; | |
171 | ||
93d89f63 IY |
172 | static void apm_ctrl_changed(uint32_t val, void *arg) |
173 | { | |
174 | PIIX4PMState *s = arg; | |
175 | ||
176 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 177 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
178 | |
179 | if (s->dev.config[0x5b] & (1 << 1)) { | |
180 | if (s->smi_irq) { | |
181 | qemu_irq_raise(s->smi_irq); | |
182 | } | |
183 | } | |
184 | } | |
185 | ||
186 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
187 | { | |
50d8ff8b | 188 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
189 | } |
190 | ||
191 | static void pm_io_space_update(PIIX4PMState *s) | |
192 | { | |
193 | uint32_t pm_io_base; | |
194 | ||
195 | if (s->dev.config[0x80] & 1) { | |
196 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); | |
197 | pm_io_base &= 0xffc0; | |
198 | ||
199 | /* XXX: need to improve memory and ioport allocation */ | |
50d8ff8b | 200 | PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
2871a3f6 AK |
201 | iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); |
202 | ioport_register(&s->ioport); | |
93d89f63 IY |
203 | } |
204 | } | |
205 | ||
206 | static void pm_write_config(PCIDevice *d, | |
207 | uint32_t address, uint32_t val, int len) | |
208 | { | |
209 | pci_default_write_config(d, address, val, len); | |
210 | if (range_covers_byte(address, len, 0x80)) | |
211 | pm_io_space_update((PIIX4PMState *)d); | |
212 | } | |
213 | ||
7faa8075 AW |
214 | static void vmstate_pci_status_pre_save(void *opaque) |
215 | { | |
216 | struct pci_status *pci0_status = opaque; | |
217 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
218 | ||
219 | /* We no longer track up, so build a safe value for migrating | |
220 | * to a version that still does... of course these might get lost | |
221 | * by an old buggy implementation, but we try. */ | |
222 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
223 | } | |
224 | ||
93d89f63 IY |
225 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
226 | { | |
227 | PIIX4PMState *s = opaque; | |
228 | ||
229 | pm_io_space_update(s); | |
230 | return 0; | |
231 | } | |
232 | ||
23910d3f IY |
233 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
234 | { \ | |
235 | .name = (stringify(_field)), \ | |
236 | .version_id = 0, \ | |
237 | .num = GPE_LEN, \ | |
238 | .info = &vmstate_info_uint16, \ | |
239 | .size = sizeof(uint16_t), \ | |
240 | .flags = VMS_ARRAY | VMS_POINTER, \ | |
241 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ | |
242 | } | |
243 | ||
4cf3e6f3 AW |
244 | static const VMStateDescription vmstate_gpe = { |
245 | .name = "gpe", | |
246 | .version_id = 1, | |
247 | .minimum_version_id = 1, | |
248 | .minimum_version_id_old = 1, | |
249 | .fields = (VMStateField []) { | |
23910d3f IY |
250 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
251 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
252 | VMSTATE_END_OF_LIST() |
253 | } | |
254 | }; | |
255 | ||
256 | static const VMStateDescription vmstate_pci_status = { | |
257 | .name = "pci_status", | |
258 | .version_id = 1, | |
259 | .minimum_version_id = 1, | |
260 | .minimum_version_id_old = 1, | |
7faa8075 | 261 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
262 | .fields = (VMStateField []) { |
263 | VMSTATE_UINT32(up, struct pci_status), | |
264 | VMSTATE_UINT32(down, struct pci_status), | |
265 | VMSTATE_END_OF_LIST() | |
266 | } | |
267 | }; | |
268 | ||
93d89f63 IY |
269 | static const VMStateDescription vmstate_acpi = { |
270 | .name = "piix4_pm", | |
4cf3e6f3 | 271 | .version_id = 2, |
93d89f63 IY |
272 | .minimum_version_id = 1, |
273 | .minimum_version_id_old = 1, | |
274 | .post_load = vmstate_acpi_post_load, | |
275 | .fields = (VMStateField []) { | |
276 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
277 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
278 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
279 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 280 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
281 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
282 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
283 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
284 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
285 | struct pci_status), | |
93d89f63 IY |
286 | VMSTATE_END_OF_LIST() |
287 | } | |
288 | }; | |
289 | ||
7faa8075 AW |
290 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
291 | { | |
0866aca1 | 292 | BusChild *kid, *next; |
7faa8075 AW |
293 | BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
294 | int slot = ffs(slots) - 1; | |
54bfa546 | 295 | bool slot_free = true; |
7faa8075 AW |
296 | |
297 | /* Mark request as complete */ | |
298 | s->pci0_status.down &= ~(1U << slot); | |
299 | ||
0866aca1 AL |
300 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
301 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
302 | PCIDevice *dev = PCI_DEVICE(qdev); |
303 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
304 | if (PCI_SLOT(dev->devfn) == slot) { |
305 | if (pc->no_hotplug) { | |
306 | slot_free = false; | |
307 | } else { | |
308 | qdev_free(qdev); | |
309 | } | |
7faa8075 AW |
310 | } |
311 | } | |
54bfa546 MT |
312 | if (slot_free) { |
313 | s->pci0_slot_device_present &= ~(1U << slot); | |
314 | } | |
7faa8075 AW |
315 | } |
316 | ||
668643b0 MT |
317 | static void piix4_update_hotplug(PIIX4PMState *s) |
318 | { | |
319 | PCIDevice *dev = &s->dev; | |
320 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
0866aca1 | 321 | BusChild *kid, *next; |
668643b0 | 322 | |
7faa8075 AW |
323 | /* Execute any pending removes during reset */ |
324 | while (s->pci0_status.down) { | |
325 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
326 | } | |
327 | ||
668643b0 | 328 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 329 | s->pci0_slot_device_present = 0; |
668643b0 | 330 | |
0866aca1 AL |
331 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
332 | DeviceState *qdev = kid->child; | |
40021f08 AL |
333 | PCIDevice *pdev = PCI_DEVICE(qdev); |
334 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
335 | int slot = PCI_SLOT(pdev->devfn); |
336 | ||
40021f08 | 337 | if (pc->no_hotplug) { |
7faa8075 | 338 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 339 | } |
7faa8075 AW |
340 | |
341 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
342 | } |
343 | } | |
344 | ||
93d89f63 IY |
345 | static void piix4_reset(void *opaque) |
346 | { | |
347 | PIIX4PMState *s = opaque; | |
348 | uint8_t *pci_conf = s->dev.config; | |
349 | ||
350 | pci_conf[0x58] = 0; | |
351 | pci_conf[0x59] = 0; | |
352 | pci_conf[0x5a] = 0; | |
353 | pci_conf[0x5b] = 0; | |
354 | ||
4d09d37c GN |
355 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
356 | pci_conf[0x80] = 0; | |
357 | ||
93d89f63 IY |
358 | if (s->kvm_enabled) { |
359 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
360 | pci_conf[0x5B] = 0x02; | |
361 | } | |
668643b0 | 362 | piix4_update_hotplug(s); |
93d89f63 IY |
363 | } |
364 | ||
365 | static void piix4_powerdown(void *opaque, int irq, int power_failing) | |
366 | { | |
367 | PIIX4PMState *s = opaque; | |
368 | ||
355bf2e5 GH |
369 | assert(s != NULL); |
370 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
371 | } |
372 | ||
9e8dd451 | 373 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
374 | { |
375 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
376 | uint8_t *pci_conf; | |
377 | ||
378 | pci_conf = s->dev.config; | |
379 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
380 | pci_conf[0x63] = 0x60; | |
381 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
382 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
383 | ||
384 | } | |
385 | ||
e8ec0571 | 386 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 387 | { |
e8ec0571 | 388 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
389 | uint8_t *pci_conf; |
390 | ||
93d89f63 | 391 | pci_conf = s->dev.config; |
93d89f63 IY |
392 | pci_conf[0x06] = 0x80; |
393 | pci_conf[0x07] = 0x02; | |
93d89f63 | 394 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
395 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
396 | ||
93d89f63 IY |
397 | /* APM */ |
398 | apm_init(&s->apm, apm_ctrl_changed, s); | |
399 | ||
400 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
401 | ||
93d89f63 IY |
402 | if (s->kvm_enabled) { |
403 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
404 | * support SMM mode. */ | |
405 | pci_conf[0x5B] = 0x02; | |
406 | } | |
407 | ||
408 | /* XXX: which specification is used ? The i82731AB has different | |
409 | mappings */ | |
e8ec0571 IY |
410 | pci_conf[0x90] = s->smb_io_base | 1; |
411 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 412 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
413 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
414 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 415 | |
355bf2e5 GH |
416 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer); |
417 | acpi_gpe_init(&s->ar, GPE_LEN); | |
93d89f63 IY |
418 | |
419 | qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); | |
420 | ||
e8ec0571 | 421 | pm_smbus_init(&s->dev.qdev, &s->smb); |
6141dbfe PB |
422 | s->machine_ready.notify = piix4_pm_machine_ready; |
423 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 424 | qemu_register_reset(piix4_reset, s); |
ac404095 | 425 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
426 | |
427 | return 0; | |
428 | } | |
429 | ||
430 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 431 | qemu_irq sci_irq, qemu_irq smi_irq, |
459ae5ea | 432 | int kvm_enabled, void *fw_cfg) |
e8ec0571 IY |
433 | { |
434 | PCIDevice *dev; | |
435 | PIIX4PMState *s; | |
436 | ||
437 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
438 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 439 | |
e8ec0571 | 440 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 441 | s->irq = sci_irq; |
da98c8eb | 442 | acpi_pm1_cnt_init(&s->ar); |
93d89f63 | 443 | s->smi_irq = smi_irq; |
e8ec0571 IY |
444 | s->kvm_enabled = kvm_enabled; |
445 | ||
446 | qdev_init_nofail(&dev->qdev); | |
93d89f63 | 447 | |
459ae5ea GN |
448 | if (fw_cfg) { |
449 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
450 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
451 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
452 | ||
453 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
454 | } | |
455 | ||
93d89f63 IY |
456 | return s->smb.smbus; |
457 | } | |
458 | ||
40021f08 AL |
459 | static Property piix4_pm_properties[] = { |
460 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
461 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
462 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
463 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
464 | DEFINE_PROP_END_OF_LIST(), |
465 | }; | |
466 | ||
467 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
468 | { | |
39bffca2 | 469 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
470 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
471 | ||
472 | k->no_hotplug = 1; | |
473 | k->init = piix4_pm_initfn; | |
474 | k->config_write = pm_write_config; | |
475 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
476 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
477 | k->revision = 0x03; | |
478 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
479 | dc->desc = "PM"; |
480 | dc->no_user = 1; | |
481 | dc->vmsd = &vmstate_acpi; | |
482 | dc->props = piix4_pm_properties; | |
40021f08 AL |
483 | } |
484 | ||
39bffca2 AL |
485 | static TypeInfo piix4_pm_info = { |
486 | .name = "PIIX4_PM", | |
487 | .parent = TYPE_PCI_DEVICE, | |
488 | .instance_size = sizeof(PIIX4PMState), | |
489 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
490 | }; |
491 | ||
83f7d43a | 492 | static void piix4_pm_register_types(void) |
e8ec0571 | 493 | { |
39bffca2 | 494 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
495 | } |
496 | ||
83f7d43a | 497 | type_init(piix4_pm_register_types) |
e8ec0571 | 498 | |
93d89f63 IY |
499 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
500 | { | |
633aa0ac | 501 | PIIX4PMState *s = opaque; |
355bf2e5 | 502 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 503 | |
50d8ff8b | 504 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
505 | return val; |
506 | } | |
507 | ||
93d89f63 IY |
508 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
509 | { | |
633aa0ac | 510 | PIIX4PMState *s = opaque; |
633aa0ac | 511 | |
355bf2e5 | 512 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 513 | pm_update_sci(s); |
93d89f63 | 514 | |
50d8ff8b | 515 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
516 | } |
517 | ||
ba737541 | 518 | static uint32_t pci_up_read(void *opaque, uint32_t addr) |
93d89f63 | 519 | { |
ba737541 | 520 | PIIX4PMState *s = opaque; |
7faa8075 AW |
521 | uint32_t val; |
522 | ||
523 | /* Manufacture an "up" value to cause a device check on any hotplug | |
524 | * slot with a device. Extra device checks are harmless. */ | |
525 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
93d89f63 | 526 | |
ba737541 | 527 | PIIX4_DPRINTF("pci_up_read %x\n", val); |
93d89f63 IY |
528 | return val; |
529 | } | |
530 | ||
ba737541 | 531 | static uint32_t pci_down_read(void *opaque, uint32_t addr) |
93d89f63 | 532 | { |
ba737541 AW |
533 | PIIX4PMState *s = opaque; |
534 | uint32_t val = s->pci0_status.down; | |
535 | ||
536 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
537 | return val; | |
93d89f63 IY |
538 | } |
539 | ||
9290f364 | 540 | static uint32_t pci_features_read(void *opaque, uint32_t addr) |
93d89f63 | 541 | { |
9290f364 AW |
542 | /* No feature defined yet */ |
543 | PIIX4_DPRINTF("pci_features_read %x\n", 0); | |
93d89f63 IY |
544 | return 0; |
545 | } | |
546 | ||
547 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
548 | { | |
7faa8075 | 549 | acpi_piix_eject_slot(opaque, val); |
93d89f63 | 550 | |
50d8ff8b | 551 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
552 | } |
553 | ||
668643b0 MT |
554 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
555 | { | |
556 | PIIX4PMState *s = opaque; | |
557 | ||
558 | return s->pci0_hotplug_enable; | |
559 | } | |
560 | ||
4cff0a59 MT |
561 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
562 | PCIHotplugState state); | |
93d89f63 | 563 | |
ac404095 | 564 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 565 | { |
93d89f63 | 566 | |
23910d3f IY |
567 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
568 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
355bf2e5 | 569 | acpi_gpe_blk(&s->ar, GPE_BASE); |
ac404095 | 570 | |
ba737541 AW |
571 | register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); |
572 | register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); | |
93d89f63 | 573 | |
7faa8075 | 574 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); |
9290f364 | 575 | register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); |
93d89f63 | 576 | |
668643b0 MT |
577 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); |
578 | ||
ac404095 | 579 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
580 | } |
581 | ||
ac404095 | 582 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 583 | { |
355bf2e5 | 584 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 585 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
586 | } |
587 | ||
ac404095 | 588 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 589 | { |
355bf2e5 | 590 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 591 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
592 | } |
593 | ||
4cff0a59 MT |
594 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
595 | PCIHotplugState state) | |
93d89f63 IY |
596 | { |
597 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 598 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 599 | PCI_DEVICE(qdev)); |
93d89f63 | 600 | |
4cff0a59 MT |
601 | /* Don't send event when device is enabled during qemu machine creation: |
602 | * it is present on boot, no hotplug event is necessary. We do send an | |
603 | * event when the device is disabled later. */ | |
604 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 605 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 606 | return 0; |
4cff0a59 | 607 | } |
5beb8ad5 | 608 | |
4cff0a59 | 609 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
610 | enable_device(s, slot); |
611 | } else { | |
612 | disable_device(s, slot); | |
613 | } | |
633aa0ac GN |
614 | |
615 | pm_update_sci(s); | |
616 | ||
93d89f63 IY |
617 | return 0; |
618 | } |