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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "pci.h" | |
93d89f63 | 26 | #include "acpi.h" |
666daa68 | 27 | #include "sysemu.h" |
bf1b0071 | 28 | #include "range.h" |
6141dbfe | 29 | #include "ioport.h" |
93d89f63 IY |
30 | |
31 | //#define DEBUG | |
32 | ||
50d8ff8b IY |
33 | #ifdef DEBUG |
34 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
35 | #else | |
36 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
37 | #endif | |
38 | ||
93d89f63 IY |
39 | #define ACPI_DBG_IO_ADDR 0xb044 |
40 | ||
ac404095 | 41 | #define GPE_BASE 0xafe0 |
23910d3f | 42 | #define GPE_LEN 4 |
ac404095 IY |
43 | #define PCI_BASE 0xae00 |
44 | #define PCI_EJ_BASE 0xae08 | |
668643b0 | 45 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 46 | |
4441a287 GN |
47 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
48 | ||
ac404095 IY |
49 | struct pci_status { |
50 | uint32_t up; | |
51 | uint32_t down; | |
52 | }; | |
53 | ||
93d89f63 IY |
54 | typedef struct PIIX4PMState { |
55 | PCIDevice dev; | |
2871a3f6 | 56 | IORange ioport; |
355bf2e5 | 57 | ACPIREGS ar; |
93d89f63 IY |
58 | |
59 | APMState apm; | |
60 | ||
93d89f63 | 61 | PMSMBus smb; |
e8ec0571 | 62 | uint32_t smb_io_base; |
93d89f63 IY |
63 | |
64 | qemu_irq irq; | |
93d89f63 IY |
65 | qemu_irq smi_irq; |
66 | int kvm_enabled; | |
6141dbfe | 67 | Notifier machine_ready; |
ac404095 IY |
68 | |
69 | /* for pci hotplug */ | |
ac404095 | 70 | struct pci_status pci0_status; |
668643b0 | 71 | uint32_t pci0_hotplug_enable; |
93d89f63 IY |
72 | } PIIX4PMState; |
73 | ||
ac404095 IY |
74 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
75 | ||
93d89f63 IY |
76 | #define ACPI_ENABLE 0xf1 |
77 | #define ACPI_DISABLE 0xf0 | |
78 | ||
93d89f63 IY |
79 | static void pm_update_sci(PIIX4PMState *s) |
80 | { | |
81 | int sci_level, pmsts; | |
93d89f63 | 82 | |
355bf2e5 GH |
83 | pmsts = acpi_pm1_evt_get_sts(&s->ar, s->ar.tmr.overflow_time); |
84 | sci_level = (((pmsts & s->ar.pm1.evt.en) & | |
93d89f63 IY |
85 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
86 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
87 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 88 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
89 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
90 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 91 | |
93d89f63 IY |
92 | qemu_set_irq(s->irq, sci_level); |
93 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 94 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 95 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
96 | } |
97 | ||
355bf2e5 | 98 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 99 | { |
355bf2e5 | 100 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
101 | pm_update_sci(s); |
102 | } | |
103 | ||
2871a3f6 AK |
104 | static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width, |
105 | uint64_t val) | |
93d89f63 | 106 | { |
2871a3f6 AK |
107 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
108 | ||
109 | if (width != 2) { | |
110 | PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", | |
111 | (unsigned)addr, width, (unsigned)val); | |
112 | } | |
113 | ||
93d89f63 IY |
114 | switch(addr) { |
115 | case 0x00: | |
355bf2e5 | 116 | acpi_pm1_evt_write_sts(&s->ar, val); |
04dc308f | 117 | pm_update_sci(s); |
93d89f63 IY |
118 | break; |
119 | case 0x02: | |
355bf2e5 | 120 | s->ar.pm1.evt.en = val; |
93d89f63 IY |
121 | pm_update_sci(s); |
122 | break; | |
123 | case 0x04: | |
355bf2e5 | 124 | acpi_pm1_cnt_write(&s->ar, val); |
93d89f63 IY |
125 | break; |
126 | default: | |
127 | break; | |
128 | } | |
59df4c11 WC |
129 | PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr, |
130 | (unsigned int)val); | |
93d89f63 IY |
131 | } |
132 | ||
2871a3f6 AK |
133 | static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width, |
134 | uint64_t *data) | |
93d89f63 | 135 | { |
2871a3f6 | 136 | PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport); |
93d89f63 IY |
137 | uint32_t val; |
138 | ||
93d89f63 IY |
139 | switch(addr) { |
140 | case 0x00: | |
355bf2e5 | 141 | val = acpi_pm1_evt_get_sts(&s->ar, s->ar.tmr.overflow_time); |
93d89f63 IY |
142 | break; |
143 | case 0x02: | |
355bf2e5 | 144 | val = s->ar.pm1.evt.en; |
93d89f63 IY |
145 | break; |
146 | case 0x04: | |
355bf2e5 | 147 | val = s->ar.pm1.cnt.cnt; |
93d89f63 | 148 | break; |
93d89f63 | 149 | case 0x08: |
355bf2e5 | 150 | val = acpi_pm_tmr_get(&s->ar); |
93d89f63 IY |
151 | break; |
152 | default: | |
153 | val = 0; | |
154 | break; | |
155 | } | |
59df4c11 | 156 | PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val); |
2871a3f6 | 157 | *data = val; |
93d89f63 IY |
158 | } |
159 | ||
2871a3f6 AK |
160 | static const IORangeOps pm_iorange_ops = { |
161 | .read = pm_ioport_read, | |
162 | .write = pm_ioport_write, | |
163 | }; | |
164 | ||
93d89f63 IY |
165 | static void apm_ctrl_changed(uint32_t val, void *arg) |
166 | { | |
167 | PIIX4PMState *s = arg; | |
168 | ||
169 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 170 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
171 | |
172 | if (s->dev.config[0x5b] & (1 << 1)) { | |
173 | if (s->smi_irq) { | |
174 | qemu_irq_raise(s->smi_irq); | |
175 | } | |
176 | } | |
177 | } | |
178 | ||
179 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
180 | { | |
50d8ff8b | 181 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
182 | } |
183 | ||
184 | static void pm_io_space_update(PIIX4PMState *s) | |
185 | { | |
186 | uint32_t pm_io_base; | |
187 | ||
188 | if (s->dev.config[0x80] & 1) { | |
189 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); | |
190 | pm_io_base &= 0xffc0; | |
191 | ||
192 | /* XXX: need to improve memory and ioport allocation */ | |
50d8ff8b | 193 | PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base); |
2871a3f6 AK |
194 | iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64); |
195 | ioport_register(&s->ioport); | |
93d89f63 IY |
196 | } |
197 | } | |
198 | ||
199 | static void pm_write_config(PCIDevice *d, | |
200 | uint32_t address, uint32_t val, int len) | |
201 | { | |
202 | pci_default_write_config(d, address, val, len); | |
203 | if (range_covers_byte(address, len, 0x80)) | |
204 | pm_io_space_update((PIIX4PMState *)d); | |
205 | } | |
206 | ||
207 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
208 | { | |
209 | PIIX4PMState *s = opaque; | |
210 | ||
211 | pm_io_space_update(s); | |
212 | return 0; | |
213 | } | |
214 | ||
23910d3f IY |
215 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
216 | { \ | |
217 | .name = (stringify(_field)), \ | |
218 | .version_id = 0, \ | |
219 | .num = GPE_LEN, \ | |
220 | .info = &vmstate_info_uint16, \ | |
221 | .size = sizeof(uint16_t), \ | |
222 | .flags = VMS_ARRAY | VMS_POINTER, \ | |
223 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ | |
224 | } | |
225 | ||
4cf3e6f3 AW |
226 | static const VMStateDescription vmstate_gpe = { |
227 | .name = "gpe", | |
228 | .version_id = 1, | |
229 | .minimum_version_id = 1, | |
230 | .minimum_version_id_old = 1, | |
231 | .fields = (VMStateField []) { | |
23910d3f IY |
232 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
233 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
234 | VMSTATE_END_OF_LIST() |
235 | } | |
236 | }; | |
237 | ||
238 | static const VMStateDescription vmstate_pci_status = { | |
239 | .name = "pci_status", | |
240 | .version_id = 1, | |
241 | .minimum_version_id = 1, | |
242 | .minimum_version_id_old = 1, | |
243 | .fields = (VMStateField []) { | |
244 | VMSTATE_UINT32(up, struct pci_status), | |
245 | VMSTATE_UINT32(down, struct pci_status), | |
246 | VMSTATE_END_OF_LIST() | |
247 | } | |
248 | }; | |
249 | ||
93d89f63 IY |
250 | static const VMStateDescription vmstate_acpi = { |
251 | .name = "piix4_pm", | |
4cf3e6f3 | 252 | .version_id = 2, |
93d89f63 IY |
253 | .minimum_version_id = 1, |
254 | .minimum_version_id_old = 1, | |
255 | .post_load = vmstate_acpi_post_load, | |
256 | .fields = (VMStateField []) { | |
257 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
258 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
259 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
260 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 261 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
262 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
263 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
264 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
265 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
266 | struct pci_status), | |
93d89f63 IY |
267 | VMSTATE_END_OF_LIST() |
268 | } | |
269 | }; | |
270 | ||
668643b0 MT |
271 | static void piix4_update_hotplug(PIIX4PMState *s) |
272 | { | |
273 | PCIDevice *dev = &s->dev; | |
274 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
275 | DeviceState *qdev, *next; | |
276 | ||
277 | s->pci0_hotplug_enable = ~0; | |
278 | ||
d8bb00d6 | 279 | QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
40021f08 AL |
280 | PCIDevice *pdev = PCI_DEVICE(qdev); |
281 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
282 | int slot = PCI_SLOT(pdev->devfn); |
283 | ||
40021f08 | 284 | if (pc->no_hotplug) { |
668643b0 MT |
285 | s->pci0_hotplug_enable &= ~(1 << slot); |
286 | } | |
287 | } | |
288 | } | |
289 | ||
93d89f63 IY |
290 | static void piix4_reset(void *opaque) |
291 | { | |
292 | PIIX4PMState *s = opaque; | |
293 | uint8_t *pci_conf = s->dev.config; | |
294 | ||
295 | pci_conf[0x58] = 0; | |
296 | pci_conf[0x59] = 0; | |
297 | pci_conf[0x5a] = 0; | |
298 | pci_conf[0x5b] = 0; | |
299 | ||
300 | if (s->kvm_enabled) { | |
301 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
302 | pci_conf[0x5B] = 0x02; | |
303 | } | |
668643b0 | 304 | piix4_update_hotplug(s); |
93d89f63 IY |
305 | } |
306 | ||
307 | static void piix4_powerdown(void *opaque, int irq, int power_failing) | |
308 | { | |
309 | PIIX4PMState *s = opaque; | |
310 | ||
355bf2e5 GH |
311 | assert(s != NULL); |
312 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
313 | } |
314 | ||
9e8dd451 | 315 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
316 | { |
317 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
318 | uint8_t *pci_conf; | |
319 | ||
320 | pci_conf = s->dev.config; | |
321 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
322 | pci_conf[0x63] = 0x60; | |
323 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
324 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
325 | ||
326 | } | |
327 | ||
e8ec0571 | 328 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 329 | { |
e8ec0571 | 330 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
331 | uint8_t *pci_conf; |
332 | ||
93d89f63 | 333 | pci_conf = s->dev.config; |
93d89f63 IY |
334 | pci_conf[0x06] = 0x80; |
335 | pci_conf[0x07] = 0x02; | |
93d89f63 | 336 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
337 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
338 | ||
339 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ | |
340 | ||
341 | /* APM */ | |
342 | apm_init(&s->apm, apm_ctrl_changed, s); | |
343 | ||
344 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
345 | ||
93d89f63 IY |
346 | if (s->kvm_enabled) { |
347 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
348 | * support SMM mode. */ | |
349 | pci_conf[0x5B] = 0x02; | |
350 | } | |
351 | ||
352 | /* XXX: which specification is used ? The i82731AB has different | |
353 | mappings */ | |
e8ec0571 IY |
354 | pci_conf[0x90] = s->smb_io_base | 1; |
355 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 356 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
357 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
358 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 359 | |
355bf2e5 GH |
360 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer); |
361 | acpi_gpe_init(&s->ar, GPE_LEN); | |
93d89f63 IY |
362 | |
363 | qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); | |
364 | ||
e8ec0571 | 365 | pm_smbus_init(&s->dev.qdev, &s->smb); |
6141dbfe PB |
366 | s->machine_ready.notify = piix4_pm_machine_ready; |
367 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 368 | qemu_register_reset(piix4_reset, s); |
ac404095 | 369 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
370 | |
371 | return 0; | |
372 | } | |
373 | ||
374 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
375 | qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, | |
376 | int kvm_enabled) | |
377 | { | |
378 | PCIDevice *dev; | |
379 | PIIX4PMState *s; | |
380 | ||
381 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
382 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 383 | |
e8ec0571 | 384 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 385 | s->irq = sci_irq; |
355bf2e5 | 386 | acpi_pm1_cnt_init(&s->ar, cmos_s3); |
93d89f63 | 387 | s->smi_irq = smi_irq; |
e8ec0571 IY |
388 | s->kvm_enabled = kvm_enabled; |
389 | ||
390 | qdev_init_nofail(&dev->qdev); | |
93d89f63 IY |
391 | |
392 | return s->smb.smbus; | |
393 | } | |
394 | ||
40021f08 AL |
395 | static Property piix4_pm_properties[] = { |
396 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
397 | DEFINE_PROP_END_OF_LIST(), | |
398 | }; | |
399 | ||
400 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
401 | { | |
39bffca2 | 402 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
403 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
404 | ||
405 | k->no_hotplug = 1; | |
406 | k->init = piix4_pm_initfn; | |
407 | k->config_write = pm_write_config; | |
408 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
409 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
410 | k->revision = 0x03; | |
411 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
412 | dc->desc = "PM"; |
413 | dc->no_user = 1; | |
414 | dc->vmsd = &vmstate_acpi; | |
415 | dc->props = piix4_pm_properties; | |
40021f08 AL |
416 | } |
417 | ||
39bffca2 AL |
418 | static TypeInfo piix4_pm_info = { |
419 | .name = "PIIX4_PM", | |
420 | .parent = TYPE_PCI_DEVICE, | |
421 | .instance_size = sizeof(PIIX4PMState), | |
422 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
423 | }; |
424 | ||
83f7d43a | 425 | static void piix4_pm_register_types(void) |
e8ec0571 | 426 | { |
39bffca2 | 427 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
428 | } |
429 | ||
83f7d43a | 430 | type_init(piix4_pm_register_types) |
e8ec0571 | 431 | |
93d89f63 IY |
432 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
433 | { | |
633aa0ac | 434 | PIIX4PMState *s = opaque; |
355bf2e5 | 435 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 436 | |
50d8ff8b | 437 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
438 | return val; |
439 | } | |
440 | ||
93d89f63 IY |
441 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
442 | { | |
633aa0ac | 443 | PIIX4PMState *s = opaque; |
633aa0ac | 444 | |
355bf2e5 | 445 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 446 | pm_update_sci(s); |
93d89f63 | 447 | |
50d8ff8b | 448 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
449 | } |
450 | ||
451 | static uint32_t pcihotplug_read(void *opaque, uint32_t addr) | |
452 | { | |
453 | uint32_t val = 0; | |
454 | struct pci_status *g = opaque; | |
455 | switch (addr) { | |
456 | case PCI_BASE: | |
457 | val = g->up; | |
458 | break; | |
459 | case PCI_BASE + 4: | |
460 | val = g->down; | |
461 | break; | |
462 | default: | |
463 | break; | |
464 | } | |
465 | ||
50d8ff8b | 466 | PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val); |
93d89f63 IY |
467 | return val; |
468 | } | |
469 | ||
470 | static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) | |
471 | { | |
472 | struct pci_status *g = opaque; | |
473 | switch (addr) { | |
474 | case PCI_BASE: | |
475 | g->up = val; | |
476 | break; | |
477 | case PCI_BASE + 4: | |
478 | g->down = val; | |
479 | break; | |
480 | } | |
481 | ||
50d8ff8b | 482 | PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val); |
93d89f63 IY |
483 | } |
484 | ||
485 | static uint32_t pciej_read(void *opaque, uint32_t addr) | |
486 | { | |
50d8ff8b | 487 | PIIX4_DPRINTF("pciej read %x\n", addr); |
93d89f63 IY |
488 | return 0; |
489 | } | |
490 | ||
491 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
492 | { | |
493 | BusState *bus = opaque; | |
494 | DeviceState *qdev, *next; | |
93d89f63 IY |
495 | int slot = ffs(val) - 1; |
496 | ||
d8bb00d6 | 497 | QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
40021f08 AL |
498 | PCIDevice *dev = PCI_DEVICE(qdev); |
499 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
500 | if (PCI_SLOT(dev->devfn) == slot && !pc->no_hotplug) { | |
93d89f63 IY |
501 | qdev_free(qdev); |
502 | } | |
503 | } | |
504 | ||
505 | ||
50d8ff8b | 506 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
507 | } |
508 | ||
668643b0 MT |
509 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
510 | { | |
511 | PIIX4PMState *s = opaque; | |
512 | ||
513 | return s->pci0_hotplug_enable; | |
514 | } | |
515 | ||
516 | static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val) | |
517 | { | |
518 | return; | |
519 | } | |
520 | ||
4cff0a59 MT |
521 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
522 | PCIHotplugState state); | |
93d89f63 | 523 | |
ac404095 | 524 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 525 | { |
ac404095 | 526 | struct pci_status *pci0_status = &s->pci0_status; |
93d89f63 | 527 | |
23910d3f IY |
528 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
529 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
355bf2e5 | 530 | acpi_gpe_blk(&s->ar, GPE_BASE); |
ac404095 IY |
531 | |
532 | register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); | |
533 | register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); | |
93d89f63 IY |
534 | |
535 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); | |
536 | register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); | |
537 | ||
668643b0 MT |
538 | register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s); |
539 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); | |
540 | ||
ac404095 | 541 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
542 | } |
543 | ||
ac404095 | 544 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 545 | { |
355bf2e5 | 546 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 547 | s->pci0_status.up |= (1 << slot); |
93d89f63 IY |
548 | } |
549 | ||
ac404095 | 550 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 551 | { |
355bf2e5 | 552 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
ac404095 | 553 | s->pci0_status.down |= (1 << slot); |
93d89f63 IY |
554 | } |
555 | ||
4cff0a59 MT |
556 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
557 | PCIHotplugState state) | |
93d89f63 IY |
558 | { |
559 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 560 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 561 | PCI_DEVICE(qdev)); |
93d89f63 | 562 | |
4cff0a59 MT |
563 | /* Don't send event when device is enabled during qemu machine creation: |
564 | * it is present on boot, no hotplug event is necessary. We do send an | |
565 | * event when the device is disabled later. */ | |
566 | if (state == PCI_COLDPLUG_ENABLED) { | |
5beb8ad5 | 567 | return 0; |
4cff0a59 | 568 | } |
5beb8ad5 | 569 | |
ac404095 IY |
570 | s->pci0_status.up = 0; |
571 | s->pci0_status.down = 0; | |
4cff0a59 | 572 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
573 | enable_device(s, slot); |
574 | } else { | |
575 | disable_device(s, slot); | |
576 | } | |
633aa0ac GN |
577 | |
578 | pm_update_sci(s); | |
579 | ||
93d89f63 IY |
580 | return 0; |
581 | } |