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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "pci.h" | |
93d89f63 | 26 | #include "acpi.h" |
666daa68 | 27 | #include "sysemu.h" |
bf1b0071 | 28 | #include "range.h" |
6141dbfe | 29 | #include "ioport.h" |
459ae5ea | 30 | #include "fw_cfg.h" |
af11110b | 31 | #include "exec-memory.h" |
93d89f63 IY |
32 | |
33 | //#define DEBUG | |
34 | ||
50d8ff8b IY |
35 | #ifdef DEBUG |
36 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
37 | #else | |
38 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
39 | #endif | |
40 | ||
93d89f63 IY |
41 | #define ACPI_DBG_IO_ADDR 0xb044 |
42 | ||
ac404095 | 43 | #define GPE_BASE 0xafe0 |
23910d3f | 44 | #define GPE_LEN 4 |
ba737541 AW |
45 | #define PCI_UP_BASE 0xae00 |
46 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 47 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 48 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 49 | |
4441a287 GN |
50 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
51 | ||
ac404095 | 52 | struct pci_status { |
7faa8075 | 53 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
54 | uint32_t down; |
55 | }; | |
56 | ||
93d89f63 IY |
57 | typedef struct PIIX4PMState { |
58 | PCIDevice dev; | |
af11110b | 59 | MemoryRegion io; |
355bf2e5 | 60 | ACPIREGS ar; |
93d89f63 IY |
61 | |
62 | APMState apm; | |
63 | ||
93d89f63 | 64 | PMSMBus smb; |
e8ec0571 | 65 | uint32_t smb_io_base; |
93d89f63 IY |
66 | |
67 | qemu_irq irq; | |
93d89f63 IY |
68 | qemu_irq smi_irq; |
69 | int kvm_enabled; | |
6141dbfe | 70 | Notifier machine_ready; |
d010f91c | 71 | Notifier powerdown_notifier; |
ac404095 IY |
72 | |
73 | /* for pci hotplug */ | |
ac404095 | 74 | struct pci_status pci0_status; |
668643b0 | 75 | uint32_t pci0_hotplug_enable; |
7faa8075 | 76 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
77 | |
78 | uint8_t disable_s3; | |
79 | uint8_t disable_s4; | |
80 | uint8_t s4_val; | |
93d89f63 IY |
81 | } PIIX4PMState; |
82 | ||
ac404095 IY |
83 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
84 | ||
93d89f63 IY |
85 | #define ACPI_ENABLE 0xf1 |
86 | #define ACPI_DISABLE 0xf0 | |
87 | ||
93d89f63 IY |
88 | static void pm_update_sci(PIIX4PMState *s) |
89 | { | |
90 | int sci_level, pmsts; | |
93d89f63 | 91 | |
2886be1b | 92 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 93 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
94 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
95 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
96 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 97 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
98 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
99 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 100 | |
93d89f63 IY |
101 | qemu_set_irq(s->irq, sci_level); |
102 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 103 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 104 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
105 | } |
106 | ||
355bf2e5 | 107 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 108 | { |
355bf2e5 | 109 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
110 | pm_update_sci(s); |
111 | } | |
112 | ||
93d89f63 IY |
113 | static void apm_ctrl_changed(uint32_t val, void *arg) |
114 | { | |
115 | PIIX4PMState *s = arg; | |
116 | ||
117 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 118 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
119 | |
120 | if (s->dev.config[0x5b] & (1 << 1)) { | |
121 | if (s->smi_irq) { | |
122 | qemu_irq_raise(s->smi_irq); | |
123 | } | |
124 | } | |
125 | } | |
126 | ||
127 | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) | |
128 | { | |
50d8ff8b | 129 | PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val); |
93d89f63 IY |
130 | } |
131 | ||
132 | static void pm_io_space_update(PIIX4PMState *s) | |
133 | { | |
134 | uint32_t pm_io_base; | |
135 | ||
af11110b GH |
136 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); |
137 | pm_io_base &= 0xffc0; | |
93d89f63 | 138 | |
af11110b GH |
139 | memory_region_transaction_begin(); |
140 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
141 | memory_region_set_address(&s->io, pm_io_base); | |
142 | memory_region_transaction_commit(); | |
93d89f63 IY |
143 | } |
144 | ||
145 | static void pm_write_config(PCIDevice *d, | |
146 | uint32_t address, uint32_t val, int len) | |
147 | { | |
148 | pci_default_write_config(d, address, val, len); | |
149 | if (range_covers_byte(address, len, 0x80)) | |
150 | pm_io_space_update((PIIX4PMState *)d); | |
151 | } | |
152 | ||
7faa8075 AW |
153 | static void vmstate_pci_status_pre_save(void *opaque) |
154 | { | |
155 | struct pci_status *pci0_status = opaque; | |
156 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
157 | ||
158 | /* We no longer track up, so build a safe value for migrating | |
159 | * to a version that still does... of course these might get lost | |
160 | * by an old buggy implementation, but we try. */ | |
161 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
162 | } | |
163 | ||
93d89f63 IY |
164 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
165 | { | |
166 | PIIX4PMState *s = opaque; | |
167 | ||
168 | pm_io_space_update(s); | |
169 | return 0; | |
170 | } | |
171 | ||
23910d3f IY |
172 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
173 | { \ | |
174 | .name = (stringify(_field)), \ | |
175 | .version_id = 0, \ | |
23910d3f IY |
176 | .info = &vmstate_info_uint16, \ |
177 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 178 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
179 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
180 | } | |
181 | ||
4cf3e6f3 AW |
182 | static const VMStateDescription vmstate_gpe = { |
183 | .name = "gpe", | |
184 | .version_id = 1, | |
185 | .minimum_version_id = 1, | |
186 | .minimum_version_id_old = 1, | |
187 | .fields = (VMStateField []) { | |
23910d3f IY |
188 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
189 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
190 | VMSTATE_END_OF_LIST() |
191 | } | |
192 | }; | |
193 | ||
194 | static const VMStateDescription vmstate_pci_status = { | |
195 | .name = "pci_status", | |
196 | .version_id = 1, | |
197 | .minimum_version_id = 1, | |
198 | .minimum_version_id_old = 1, | |
7faa8075 | 199 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
200 | .fields = (VMStateField []) { |
201 | VMSTATE_UINT32(up, struct pci_status), | |
202 | VMSTATE_UINT32(down, struct pci_status), | |
203 | VMSTATE_END_OF_LIST() | |
204 | } | |
205 | }; | |
206 | ||
b0b873a0 MT |
207 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
208 | { | |
209 | PIIX4PMState *s = opaque; | |
210 | int ret, i; | |
211 | uint16_t temp; | |
212 | ||
213 | ret = pci_device_load(&s->dev, f); | |
214 | if (ret < 0) { | |
215 | return ret; | |
216 | } | |
217 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
218 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
219 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
220 | ||
221 | ret = vmstate_load_state(f, &vmstate_apm, opaque, 1); | |
222 | if (ret) { | |
223 | return ret; | |
224 | } | |
225 | ||
226 | qemu_get_timer(f, s->ar.tmr.timer); | |
227 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); | |
228 | ||
229 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
230 | for (i = 0; i < 3; i++) { | |
231 | qemu_get_be16s(f, &temp); | |
232 | } | |
233 | ||
234 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
235 | for (i = 0; i < 3; i++) { | |
236 | qemu_get_be16s(f, &temp); | |
237 | } | |
238 | ||
239 | ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1); | |
240 | return ret; | |
241 | } | |
242 | ||
243 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 | |
244 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
245 | * and minimum_version_id to 2 below (which breaks migration from | |
246 | * qemu 1.2). | |
247 | * | |
248 | */ | |
93d89f63 IY |
249 | static const VMStateDescription vmstate_acpi = { |
250 | .name = "piix4_pm", | |
b0b873a0 MT |
251 | .version_id = 3, |
252 | .minimum_version_id = 3, | |
93d89f63 | 253 | .minimum_version_id_old = 1, |
b0b873a0 | 254 | .load_state_old = acpi_load_old, |
93d89f63 IY |
255 | .post_load = vmstate_acpi_post_load, |
256 | .fields = (VMStateField []) { | |
257 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
258 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
259 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
260 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 261 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
262 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
263 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
264 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
265 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
266 | struct pci_status), | |
93d89f63 IY |
267 | VMSTATE_END_OF_LIST() |
268 | } | |
269 | }; | |
270 | ||
7faa8075 AW |
271 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
272 | { | |
0866aca1 | 273 | BusChild *kid, *next; |
7faa8075 AW |
274 | BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
275 | int slot = ffs(slots) - 1; | |
54bfa546 | 276 | bool slot_free = true; |
7faa8075 AW |
277 | |
278 | /* Mark request as complete */ | |
279 | s->pci0_status.down &= ~(1U << slot); | |
280 | ||
0866aca1 AL |
281 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
282 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
283 | PCIDevice *dev = PCI_DEVICE(qdev); |
284 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
285 | if (PCI_SLOT(dev->devfn) == slot) { |
286 | if (pc->no_hotplug) { | |
287 | slot_free = false; | |
288 | } else { | |
289 | qdev_free(qdev); | |
290 | } | |
7faa8075 AW |
291 | } |
292 | } | |
54bfa546 MT |
293 | if (slot_free) { |
294 | s->pci0_slot_device_present &= ~(1U << slot); | |
295 | } | |
7faa8075 AW |
296 | } |
297 | ||
668643b0 MT |
298 | static void piix4_update_hotplug(PIIX4PMState *s) |
299 | { | |
300 | PCIDevice *dev = &s->dev; | |
301 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
0866aca1 | 302 | BusChild *kid, *next; |
668643b0 | 303 | |
7faa8075 AW |
304 | /* Execute any pending removes during reset */ |
305 | while (s->pci0_status.down) { | |
306 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
307 | } | |
308 | ||
668643b0 | 309 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 310 | s->pci0_slot_device_present = 0; |
668643b0 | 311 | |
0866aca1 AL |
312 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
313 | DeviceState *qdev = kid->child; | |
40021f08 AL |
314 | PCIDevice *pdev = PCI_DEVICE(qdev); |
315 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
316 | int slot = PCI_SLOT(pdev->devfn); |
317 | ||
40021f08 | 318 | if (pc->no_hotplug) { |
7faa8075 | 319 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 320 | } |
7faa8075 AW |
321 | |
322 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
323 | } |
324 | } | |
325 | ||
93d89f63 IY |
326 | static void piix4_reset(void *opaque) |
327 | { | |
328 | PIIX4PMState *s = opaque; | |
329 | uint8_t *pci_conf = s->dev.config; | |
330 | ||
331 | pci_conf[0x58] = 0; | |
332 | pci_conf[0x59] = 0; | |
333 | pci_conf[0x5a] = 0; | |
334 | pci_conf[0x5b] = 0; | |
335 | ||
4d09d37c GN |
336 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
337 | pci_conf[0x80] = 0; | |
338 | ||
93d89f63 IY |
339 | if (s->kvm_enabled) { |
340 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
341 | pci_conf[0x5B] = 0x02; | |
342 | } | |
668643b0 | 343 | piix4_update_hotplug(s); |
93d89f63 IY |
344 | } |
345 | ||
d010f91c | 346 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 347 | { |
d010f91c | 348 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 349 | |
355bf2e5 GH |
350 | assert(s != NULL); |
351 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
352 | } |
353 | ||
9e8dd451 | 354 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
355 | { |
356 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
357 | uint8_t *pci_conf; | |
358 | ||
359 | pci_conf = s->dev.config; | |
360 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
361 | pci_conf[0x63] = 0x60; | |
362 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
363 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
364 | ||
365 | } | |
366 | ||
e8ec0571 | 367 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 368 | { |
e8ec0571 | 369 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
370 | uint8_t *pci_conf; |
371 | ||
93d89f63 | 372 | pci_conf = s->dev.config; |
93d89f63 IY |
373 | pci_conf[0x06] = 0x80; |
374 | pci_conf[0x07] = 0x02; | |
93d89f63 | 375 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
376 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
377 | ||
93d89f63 IY |
378 | /* APM */ |
379 | apm_init(&s->apm, apm_ctrl_changed, s); | |
380 | ||
381 | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); | |
382 | ||
93d89f63 IY |
383 | if (s->kvm_enabled) { |
384 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
385 | * support SMM mode. */ | |
386 | pci_conf[0x5B] = 0x02; | |
387 | } | |
388 | ||
389 | /* XXX: which specification is used ? The i82731AB has different | |
390 | mappings */ | |
e8ec0571 IY |
391 | pci_conf[0x90] = s->smb_io_base | 1; |
392 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 393 | pci_conf[0xd2] = 0x09; |
e8ec0571 IY |
394 | register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
395 | register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); | |
93d89f63 | 396 | |
ca5d64b4 | 397 | memory_region_init(&s->io, "piix4-pm", 64); |
af11110b GH |
398 | memory_region_set_enabled(&s->io, false); |
399 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
400 | ||
77d58b1e | 401 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 402 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
afafe4bb | 403 | acpi_pm1_cnt_init(&s->ar, &s->io); |
355bf2e5 | 404 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 405 | |
d010f91c IM |
406 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
407 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 408 | |
e8ec0571 | 409 | pm_smbus_init(&s->dev.qdev, &s->smb); |
6141dbfe PB |
410 | s->machine_ready.notify = piix4_pm_machine_ready; |
411 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 412 | qemu_register_reset(piix4_reset, s); |
ac404095 | 413 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
414 | |
415 | return 0; | |
416 | } | |
417 | ||
418 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 419 | qemu_irq sci_irq, qemu_irq smi_irq, |
459ae5ea | 420 | int kvm_enabled, void *fw_cfg) |
e8ec0571 IY |
421 | { |
422 | PCIDevice *dev; | |
423 | PIIX4PMState *s; | |
424 | ||
425 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
426 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 427 | |
e8ec0571 | 428 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 429 | s->irq = sci_irq; |
93d89f63 | 430 | s->smi_irq = smi_irq; |
e8ec0571 IY |
431 | s->kvm_enabled = kvm_enabled; |
432 | ||
433 | qdev_init_nofail(&dev->qdev); | |
93d89f63 | 434 | |
459ae5ea GN |
435 | if (fw_cfg) { |
436 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
437 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
438 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
439 | ||
440 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
441 | } | |
442 | ||
93d89f63 IY |
443 | return s->smb.smbus; |
444 | } | |
445 | ||
40021f08 AL |
446 | static Property piix4_pm_properties[] = { |
447 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
448 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
449 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
450 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
451 | DEFINE_PROP_END_OF_LIST(), |
452 | }; | |
453 | ||
454 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
455 | { | |
39bffca2 | 456 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
457 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
458 | ||
459 | k->no_hotplug = 1; | |
460 | k->init = piix4_pm_initfn; | |
461 | k->config_write = pm_write_config; | |
462 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
463 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
464 | k->revision = 0x03; | |
465 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
466 | dc->desc = "PM"; |
467 | dc->no_user = 1; | |
468 | dc->vmsd = &vmstate_acpi; | |
469 | dc->props = piix4_pm_properties; | |
40021f08 AL |
470 | } |
471 | ||
39bffca2 AL |
472 | static TypeInfo piix4_pm_info = { |
473 | .name = "PIIX4_PM", | |
474 | .parent = TYPE_PCI_DEVICE, | |
475 | .instance_size = sizeof(PIIX4PMState), | |
476 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
477 | }; |
478 | ||
83f7d43a | 479 | static void piix4_pm_register_types(void) |
e8ec0571 | 480 | { |
39bffca2 | 481 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
482 | } |
483 | ||
83f7d43a | 484 | type_init(piix4_pm_register_types) |
e8ec0571 | 485 | |
93d89f63 IY |
486 | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
487 | { | |
633aa0ac | 488 | PIIX4PMState *s = opaque; |
355bf2e5 | 489 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 490 | |
50d8ff8b | 491 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
492 | return val; |
493 | } | |
494 | ||
93d89f63 IY |
495 | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
496 | { | |
633aa0ac | 497 | PIIX4PMState *s = opaque; |
633aa0ac | 498 | |
355bf2e5 | 499 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 500 | pm_update_sci(s); |
93d89f63 | 501 | |
50d8ff8b | 502 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
503 | } |
504 | ||
ba737541 | 505 | static uint32_t pci_up_read(void *opaque, uint32_t addr) |
93d89f63 | 506 | { |
ba737541 | 507 | PIIX4PMState *s = opaque; |
7faa8075 AW |
508 | uint32_t val; |
509 | ||
510 | /* Manufacture an "up" value to cause a device check on any hotplug | |
511 | * slot with a device. Extra device checks are harmless. */ | |
512 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
93d89f63 | 513 | |
ba737541 | 514 | PIIX4_DPRINTF("pci_up_read %x\n", val); |
93d89f63 IY |
515 | return val; |
516 | } | |
517 | ||
ba737541 | 518 | static uint32_t pci_down_read(void *opaque, uint32_t addr) |
93d89f63 | 519 | { |
ba737541 AW |
520 | PIIX4PMState *s = opaque; |
521 | uint32_t val = s->pci0_status.down; | |
522 | ||
523 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
524 | return val; | |
93d89f63 IY |
525 | } |
526 | ||
9290f364 | 527 | static uint32_t pci_features_read(void *opaque, uint32_t addr) |
93d89f63 | 528 | { |
9290f364 AW |
529 | /* No feature defined yet */ |
530 | PIIX4_DPRINTF("pci_features_read %x\n", 0); | |
93d89f63 IY |
531 | return 0; |
532 | } | |
533 | ||
534 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
535 | { | |
7faa8075 | 536 | acpi_piix_eject_slot(opaque, val); |
93d89f63 | 537 | |
50d8ff8b | 538 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
539 | } |
540 | ||
668643b0 MT |
541 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
542 | { | |
543 | PIIX4PMState *s = opaque; | |
544 | ||
545 | return s->pci0_hotplug_enable; | |
546 | } | |
547 | ||
4cff0a59 MT |
548 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
549 | PCIHotplugState state); | |
93d89f63 | 550 | |
ac404095 | 551 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 552 | { |
93d89f63 | 553 | |
23910d3f IY |
554 | register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s); |
555 | register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s); | |
355bf2e5 | 556 | acpi_gpe_blk(&s->ar, GPE_BASE); |
ac404095 | 557 | |
ba737541 AW |
558 | register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s); |
559 | register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); | |
93d89f63 | 560 | |
7faa8075 | 561 | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); |
9290f364 | 562 | register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); |
93d89f63 | 563 | |
668643b0 MT |
564 | register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s); |
565 | ||
ac404095 | 566 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
567 | } |
568 | ||
ac404095 | 569 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 570 | { |
355bf2e5 | 571 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 572 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
573 | } |
574 | ||
ac404095 | 575 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 576 | { |
355bf2e5 | 577 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 578 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
579 | } |
580 | ||
4cff0a59 MT |
581 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
582 | PCIHotplugState state) | |
93d89f63 IY |
583 | { |
584 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 585 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 586 | PCI_DEVICE(qdev)); |
93d89f63 | 587 | |
4cff0a59 MT |
588 | /* Don't send event when device is enabled during qemu machine creation: |
589 | * it is present on boot, no hotplug event is necessary. We do send an | |
590 | * event when the device is disabled later. */ | |
591 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 592 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 593 | return 0; |
4cff0a59 | 594 | } |
5beb8ad5 | 595 | |
4cff0a59 | 596 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
597 | enable_device(s, slot); |
598 | } else { | |
599 | disable_device(s, slot); | |
600 | } | |
633aa0ac GN |
601 | |
602 | pm_update_sci(s); | |
603 | ||
93d89f63 IY |
604 | return 0; |
605 | } |