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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 IY |
20 | */ |
21 | #include "hw.h" | |
22 | #include "pc.h" | |
23 | #include "apm.h" | |
24 | #include "pm_smbus.h" | |
a2cb15b0 | 25 | #include "pci/pci.h" |
93d89f63 | 26 | #include "acpi.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
1de7afc9 | 28 | #include "qemu/range.h" |
022c62cb | 29 | #include "exec/ioport.h" |
459ae5ea | 30 | #include "fw_cfg.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
93d89f63 IY |
32 | |
33 | //#define DEBUG | |
34 | ||
50d8ff8b IY |
35 | #ifdef DEBUG |
36 | # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
37 | #else | |
38 | # define PIIX4_DPRINTF(format, ...) do { } while (0) | |
39 | #endif | |
40 | ||
ac404095 | 41 | #define GPE_BASE 0xafe0 |
23910d3f | 42 | #define GPE_LEN 4 |
c177684c GH |
43 | |
44 | #define PCI_HOTPLUG_ADDR 0xae00 | |
45 | #define PCI_HOTPLUG_SIZE 0x000f | |
ba737541 AW |
46 | #define PCI_UP_BASE 0xae00 |
47 | #define PCI_DOWN_BASE 0xae04 | |
ac404095 | 48 | #define PCI_EJ_BASE 0xae08 |
668643b0 | 49 | #define PCI_RMV_BASE 0xae0c |
ac404095 | 50 | |
4441a287 GN |
51 | #define PIIX4_PCI_HOTPLUG_STATUS 2 |
52 | ||
ac404095 | 53 | struct pci_status { |
7faa8075 | 54 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
55 | uint32_t down; |
56 | }; | |
57 | ||
93d89f63 IY |
58 | typedef struct PIIX4PMState { |
59 | PCIDevice dev; | |
af11110b | 60 | MemoryRegion io; |
b65b93f2 | 61 | MemoryRegion io_gpe; |
c177684c | 62 | MemoryRegion io_pci; |
355bf2e5 | 63 | ACPIREGS ar; |
93d89f63 IY |
64 | |
65 | APMState apm; | |
66 | ||
93d89f63 | 67 | PMSMBus smb; |
e8ec0571 | 68 | uint32_t smb_io_base; |
93d89f63 IY |
69 | |
70 | qemu_irq irq; | |
93d89f63 IY |
71 | qemu_irq smi_irq; |
72 | int kvm_enabled; | |
6141dbfe | 73 | Notifier machine_ready; |
d010f91c | 74 | Notifier powerdown_notifier; |
ac404095 IY |
75 | |
76 | /* for pci hotplug */ | |
ac404095 | 77 | struct pci_status pci0_status; |
668643b0 | 78 | uint32_t pci0_hotplug_enable; |
7faa8075 | 79 | uint32_t pci0_slot_device_present; |
459ae5ea GN |
80 | |
81 | uint8_t disable_s3; | |
82 | uint8_t disable_s4; | |
83 | uint8_t s4_val; | |
93d89f63 IY |
84 | } PIIX4PMState; |
85 | ||
ac404095 IY |
86 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s); |
87 | ||
93d89f63 IY |
88 | #define ACPI_ENABLE 0xf1 |
89 | #define ACPI_DISABLE 0xf0 | |
90 | ||
93d89f63 IY |
91 | static void pm_update_sci(PIIX4PMState *s) |
92 | { | |
93 | int sci_level, pmsts; | |
93d89f63 | 94 | |
2886be1b | 95 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 96 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
93d89f63 IY |
97 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
98 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
99 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
633aa0ac | 100 | ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
355bf2e5 GH |
101 | (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) |
102 | & PIIX4_PCI_HOTPLUG_STATUS) != 0); | |
633aa0ac | 103 | |
93d89f63 IY |
104 | qemu_set_irq(s->irq, sci_level); |
105 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 106 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 107 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
93d89f63 IY |
108 | } |
109 | ||
355bf2e5 | 110 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 111 | { |
355bf2e5 | 112 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
93d89f63 IY |
113 | pm_update_sci(s); |
114 | } | |
115 | ||
93d89f63 IY |
116 | static void apm_ctrl_changed(uint32_t val, void *arg) |
117 | { | |
118 | PIIX4PMState *s = arg; | |
119 | ||
120 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 121 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
93d89f63 IY |
122 | |
123 | if (s->dev.config[0x5b] & (1 << 1)) { | |
124 | if (s->smi_irq) { | |
125 | qemu_irq_raise(s->smi_irq); | |
126 | } | |
127 | } | |
128 | } | |
129 | ||
93d89f63 IY |
130 | static void pm_io_space_update(PIIX4PMState *s) |
131 | { | |
132 | uint32_t pm_io_base; | |
133 | ||
af11110b GH |
134 | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); |
135 | pm_io_base &= 0xffc0; | |
93d89f63 | 136 | |
af11110b GH |
137 | memory_region_transaction_begin(); |
138 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
139 | memory_region_set_address(&s->io, pm_io_base); | |
140 | memory_region_transaction_commit(); | |
93d89f63 IY |
141 | } |
142 | ||
24fe083d GH |
143 | static void smbus_io_space_update(PIIX4PMState *s) |
144 | { | |
145 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90)); | |
146 | s->smb_io_base &= 0xffc0; | |
147 | ||
148 | memory_region_transaction_begin(); | |
149 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1); | |
150 | memory_region_set_address(&s->smb.io, s->smb_io_base); | |
151 | memory_region_transaction_commit(); | |
93d89f63 IY |
152 | } |
153 | ||
154 | static void pm_write_config(PCIDevice *d, | |
155 | uint32_t address, uint32_t val, int len) | |
156 | { | |
157 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
158 | if (range_covers_byte(address, len, 0x80) || |
159 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 160 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
161 | } |
162 | if (range_covers_byte(address, len, 0xd2) || | |
163 | ranges_overlap(address, len, 0x90, 4)) { | |
164 | smbus_io_space_update((PIIX4PMState *)d); | |
165 | } | |
93d89f63 IY |
166 | } |
167 | ||
7faa8075 AW |
168 | static void vmstate_pci_status_pre_save(void *opaque) |
169 | { | |
170 | struct pci_status *pci0_status = opaque; | |
171 | PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status); | |
172 | ||
173 | /* We no longer track up, so build a safe value for migrating | |
174 | * to a version that still does... of course these might get lost | |
175 | * by an old buggy implementation, but we try. */ | |
176 | pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
177 | } | |
178 | ||
93d89f63 IY |
179 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
180 | { | |
181 | PIIX4PMState *s = opaque; | |
182 | ||
183 | pm_io_space_update(s); | |
184 | return 0; | |
185 | } | |
186 | ||
23910d3f IY |
187 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
188 | { \ | |
189 | .name = (stringify(_field)), \ | |
190 | .version_id = 0, \ | |
23910d3f IY |
191 | .info = &vmstate_info_uint16, \ |
192 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 193 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
194 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
195 | } | |
196 | ||
4cf3e6f3 AW |
197 | static const VMStateDescription vmstate_gpe = { |
198 | .name = "gpe", | |
199 | .version_id = 1, | |
200 | .minimum_version_id = 1, | |
201 | .minimum_version_id_old = 1, | |
202 | .fields = (VMStateField []) { | |
23910d3f IY |
203 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
204 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
205 | VMSTATE_END_OF_LIST() |
206 | } | |
207 | }; | |
208 | ||
209 | static const VMStateDescription vmstate_pci_status = { | |
210 | .name = "pci_status", | |
211 | .version_id = 1, | |
212 | .minimum_version_id = 1, | |
213 | .minimum_version_id_old = 1, | |
7faa8075 | 214 | .pre_save = vmstate_pci_status_pre_save, |
4cf3e6f3 AW |
215 | .fields = (VMStateField []) { |
216 | VMSTATE_UINT32(up, struct pci_status), | |
217 | VMSTATE_UINT32(down, struct pci_status), | |
218 | VMSTATE_END_OF_LIST() | |
219 | } | |
220 | }; | |
221 | ||
b0b873a0 MT |
222 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
223 | { | |
224 | PIIX4PMState *s = opaque; | |
225 | int ret, i; | |
226 | uint16_t temp; | |
227 | ||
228 | ret = pci_device_load(&s->dev, f); | |
229 | if (ret < 0) { | |
230 | return ret; | |
231 | } | |
232 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
233 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
234 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
235 | ||
236 | ret = vmstate_load_state(f, &vmstate_apm, opaque, 1); | |
237 | if (ret) { | |
238 | return ret; | |
239 | } | |
240 | ||
241 | qemu_get_timer(f, s->ar.tmr.timer); | |
242 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); | |
243 | ||
244 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
245 | for (i = 0; i < 3; i++) { | |
246 | qemu_get_be16s(f, &temp); | |
247 | } | |
248 | ||
249 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
250 | for (i = 0; i < 3; i++) { | |
251 | qemu_get_be16s(f, &temp); | |
252 | } | |
253 | ||
254 | ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 | |
259 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
260 | * and minimum_version_id to 2 below (which breaks migration from | |
261 | * qemu 1.2). | |
262 | * | |
263 | */ | |
93d89f63 IY |
264 | static const VMStateDescription vmstate_acpi = { |
265 | .name = "piix4_pm", | |
b0b873a0 MT |
266 | .version_id = 3, |
267 | .minimum_version_id = 3, | |
93d89f63 | 268 | .minimum_version_id_old = 1, |
b0b873a0 | 269 | .load_state_old = acpi_load_old, |
93d89f63 IY |
270 | .post_load = vmstate_acpi_post_load, |
271 | .fields = (VMStateField []) { | |
272 | VMSTATE_PCI_DEVICE(dev, PIIX4PMState), | |
355bf2e5 GH |
273 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
274 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
275 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 276 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
277 | VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), |
278 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), | |
279 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
4cf3e6f3 AW |
280 | VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status, |
281 | struct pci_status), | |
93d89f63 IY |
282 | VMSTATE_END_OF_LIST() |
283 | } | |
284 | }; | |
285 | ||
7faa8075 AW |
286 | static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots) |
287 | { | |
0866aca1 | 288 | BusChild *kid, *next; |
7faa8075 AW |
289 | BusState *bus = qdev_get_parent_bus(&s->dev.qdev); |
290 | int slot = ffs(slots) - 1; | |
54bfa546 | 291 | bool slot_free = true; |
7faa8075 AW |
292 | |
293 | /* Mark request as complete */ | |
294 | s->pci0_status.down &= ~(1U << slot); | |
295 | ||
0866aca1 AL |
296 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
297 | DeviceState *qdev = kid->child; | |
7faa8075 AW |
298 | PCIDevice *dev = PCI_DEVICE(qdev); |
299 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
54bfa546 MT |
300 | if (PCI_SLOT(dev->devfn) == slot) { |
301 | if (pc->no_hotplug) { | |
302 | slot_free = false; | |
303 | } else { | |
304 | qdev_free(qdev); | |
305 | } | |
7faa8075 AW |
306 | } |
307 | } | |
54bfa546 MT |
308 | if (slot_free) { |
309 | s->pci0_slot_device_present &= ~(1U << slot); | |
310 | } | |
7faa8075 AW |
311 | } |
312 | ||
668643b0 MT |
313 | static void piix4_update_hotplug(PIIX4PMState *s) |
314 | { | |
315 | PCIDevice *dev = &s->dev; | |
316 | BusState *bus = qdev_get_parent_bus(&dev->qdev); | |
0866aca1 | 317 | BusChild *kid, *next; |
668643b0 | 318 | |
7faa8075 AW |
319 | /* Execute any pending removes during reset */ |
320 | while (s->pci0_status.down) { | |
321 | acpi_piix_eject_slot(s, s->pci0_status.down); | |
322 | } | |
323 | ||
668643b0 | 324 | s->pci0_hotplug_enable = ~0; |
7faa8075 | 325 | s->pci0_slot_device_present = 0; |
668643b0 | 326 | |
0866aca1 AL |
327 | QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { |
328 | DeviceState *qdev = kid->child; | |
40021f08 AL |
329 | PCIDevice *pdev = PCI_DEVICE(qdev); |
330 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev); | |
668643b0 MT |
331 | int slot = PCI_SLOT(pdev->devfn); |
332 | ||
40021f08 | 333 | if (pc->no_hotplug) { |
7faa8075 | 334 | s->pci0_hotplug_enable &= ~(1U << slot); |
668643b0 | 335 | } |
7faa8075 AW |
336 | |
337 | s->pci0_slot_device_present |= (1U << slot); | |
668643b0 MT |
338 | } |
339 | } | |
340 | ||
93d89f63 IY |
341 | static void piix4_reset(void *opaque) |
342 | { | |
343 | PIIX4PMState *s = opaque; | |
344 | uint8_t *pci_conf = s->dev.config; | |
345 | ||
346 | pci_conf[0x58] = 0; | |
347 | pci_conf[0x59] = 0; | |
348 | pci_conf[0x5a] = 0; | |
349 | pci_conf[0x5b] = 0; | |
350 | ||
4d09d37c GN |
351 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
352 | pci_conf[0x80] = 0; | |
353 | ||
93d89f63 IY |
354 | if (s->kvm_enabled) { |
355 | /* Mark SMM as already inited (until KVM supports SMM). */ | |
356 | pci_conf[0x5B] = 0x02; | |
357 | } | |
668643b0 | 358 | piix4_update_hotplug(s); |
93d89f63 IY |
359 | } |
360 | ||
d010f91c | 361 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 362 | { |
d010f91c | 363 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 364 | |
355bf2e5 GH |
365 | assert(s != NULL); |
366 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
367 | } |
368 | ||
9e8dd451 | 369 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
370 | { |
371 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
372 | uint8_t *pci_conf; | |
373 | ||
374 | pci_conf = s->dev.config; | |
375 | pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10; | |
376 | pci_conf[0x63] = 0x60; | |
377 | pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) | | |
378 | (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0); | |
379 | ||
380 | } | |
381 | ||
e8ec0571 | 382 | static int piix4_pm_initfn(PCIDevice *dev) |
93d89f63 | 383 | { |
e8ec0571 | 384 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 IY |
385 | uint8_t *pci_conf; |
386 | ||
93d89f63 | 387 | pci_conf = s->dev.config; |
93d89f63 IY |
388 | pci_conf[0x06] = 0x80; |
389 | pci_conf[0x07] = 0x02; | |
93d89f63 | 390 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
391 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
392 | ||
93d89f63 | 393 | /* APM */ |
42d8a3cf | 394 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 395 | |
93d89f63 IY |
396 | if (s->kvm_enabled) { |
397 | /* Mark SMM as already inited to prevent SMM from running. KVM does not | |
398 | * support SMM mode. */ | |
399 | pci_conf[0x5B] = 0x02; | |
400 | } | |
401 | ||
402 | /* XXX: which specification is used ? The i82731AB has different | |
403 | mappings */ | |
e8ec0571 IY |
404 | pci_conf[0x90] = s->smb_io_base | 1; |
405 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 406 | pci_conf[0xd2] = 0x09; |
798512e5 | 407 | pm_smbus_init(&s->dev.qdev, &s->smb); |
24fe083d | 408 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
798512e5 | 409 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); |
93d89f63 | 410 | |
ca5d64b4 | 411 | memory_region_init(&s->io, "piix4-pm", 64); |
af11110b GH |
412 | memory_region_set_enabled(&s->io, false); |
413 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
93d89f63 | 414 | |
77d58b1e | 415 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 416 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
afafe4bb | 417 | acpi_pm1_cnt_init(&s->ar, &s->io); |
355bf2e5 | 418 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 419 | |
d010f91c IM |
420 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
421 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 422 | |
6141dbfe PB |
423 | s->machine_ready.notify = piix4_pm_machine_ready; |
424 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 425 | qemu_register_reset(piix4_reset, s); |
ac404095 | 426 | piix4_acpi_system_hot_add_init(dev->bus, s); |
e8ec0571 IY |
427 | |
428 | return 0; | |
429 | } | |
430 | ||
431 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
da98c8eb | 432 | qemu_irq sci_irq, qemu_irq smi_irq, |
459ae5ea | 433 | int kvm_enabled, void *fw_cfg) |
e8ec0571 IY |
434 | { |
435 | PCIDevice *dev; | |
436 | PIIX4PMState *s; | |
437 | ||
438 | dev = pci_create(bus, devfn, "PIIX4_PM"); | |
439 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
93d89f63 | 440 | |
e8ec0571 | 441 | s = DO_UPCAST(PIIX4PMState, dev, dev); |
93d89f63 | 442 | s->irq = sci_irq; |
93d89f63 | 443 | s->smi_irq = smi_irq; |
e8ec0571 IY |
444 | s->kvm_enabled = kvm_enabled; |
445 | ||
446 | qdev_init_nofail(&dev->qdev); | |
93d89f63 | 447 | |
459ae5ea GN |
448 | if (fw_cfg) { |
449 | uint8_t suspend[6] = {128, 0, 0, 129, 128, 128}; | |
450 | suspend[3] = 1 | ((!s->disable_s3) << 7); | |
451 | suspend[4] = s->s4_val | ((!s->disable_s4) << 7); | |
452 | ||
453 | fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6); | |
454 | } | |
455 | ||
93d89f63 IY |
456 | return s->smb.smbus; |
457 | } | |
458 | ||
40021f08 AL |
459 | static Property piix4_pm_properties[] = { |
460 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
459ae5ea GN |
461 | DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0), |
462 | DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0), | |
463 | DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2), | |
40021f08 AL |
464 | DEFINE_PROP_END_OF_LIST(), |
465 | }; | |
466 | ||
467 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
468 | { | |
39bffca2 | 469 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
470 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
471 | ||
472 | k->no_hotplug = 1; | |
473 | k->init = piix4_pm_initfn; | |
474 | k->config_write = pm_write_config; | |
475 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
476 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
477 | k->revision = 0x03; | |
478 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
39bffca2 AL |
479 | dc->desc = "PM"; |
480 | dc->no_user = 1; | |
481 | dc->vmsd = &vmstate_acpi; | |
482 | dc->props = piix4_pm_properties; | |
40021f08 AL |
483 | } |
484 | ||
39bffca2 AL |
485 | static TypeInfo piix4_pm_info = { |
486 | .name = "PIIX4_PM", | |
487 | .parent = TYPE_PCI_DEVICE, | |
488 | .instance_size = sizeof(PIIX4PMState), | |
489 | .class_init = piix4_pm_class_init, | |
e8ec0571 IY |
490 | }; |
491 | ||
83f7d43a | 492 | static void piix4_pm_register_types(void) |
e8ec0571 | 493 | { |
39bffca2 | 494 | type_register_static(&piix4_pm_info); |
e8ec0571 IY |
495 | } |
496 | ||
83f7d43a | 497 | type_init(piix4_pm_register_types) |
e8ec0571 | 498 | |
b65b93f2 | 499 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 500 | { |
633aa0ac | 501 | PIIX4PMState *s = opaque; |
355bf2e5 | 502 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 503 | |
50d8ff8b | 504 | PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); |
93d89f63 IY |
505 | return val; |
506 | } | |
507 | ||
b65b93f2 GH |
508 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
509 | unsigned width) | |
93d89f63 | 510 | { |
633aa0ac | 511 | PIIX4PMState *s = opaque; |
633aa0ac | 512 | |
355bf2e5 | 513 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
633aa0ac | 514 | pm_update_sci(s); |
93d89f63 | 515 | |
50d8ff8b | 516 | PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); |
93d89f63 IY |
517 | } |
518 | ||
b65b93f2 GH |
519 | static const MemoryRegionOps piix4_gpe_ops = { |
520 | .read = gpe_readb, | |
521 | .write = gpe_writeb, | |
522 | .valid.min_access_size = 1, | |
523 | .valid.max_access_size = 4, | |
524 | .impl.min_access_size = 1, | |
525 | .impl.max_access_size = 1, | |
526 | .endianness = DEVICE_LITTLE_ENDIAN, | |
527 | }; | |
528 | ||
ba737541 | 529 | static uint32_t pci_up_read(void *opaque, uint32_t addr) |
93d89f63 | 530 | { |
ba737541 | 531 | PIIX4PMState *s = opaque; |
7faa8075 AW |
532 | uint32_t val; |
533 | ||
534 | /* Manufacture an "up" value to cause a device check on any hotplug | |
535 | * slot with a device. Extra device checks are harmless. */ | |
536 | val = s->pci0_slot_device_present & s->pci0_hotplug_enable; | |
93d89f63 | 537 | |
ba737541 | 538 | PIIX4_DPRINTF("pci_up_read %x\n", val); |
93d89f63 IY |
539 | return val; |
540 | } | |
541 | ||
ba737541 | 542 | static uint32_t pci_down_read(void *opaque, uint32_t addr) |
93d89f63 | 543 | { |
ba737541 AW |
544 | PIIX4PMState *s = opaque; |
545 | uint32_t val = s->pci0_status.down; | |
546 | ||
547 | PIIX4_DPRINTF("pci_down_read %x\n", val); | |
548 | return val; | |
93d89f63 IY |
549 | } |
550 | ||
9290f364 | 551 | static uint32_t pci_features_read(void *opaque, uint32_t addr) |
93d89f63 | 552 | { |
9290f364 AW |
553 | /* No feature defined yet */ |
554 | PIIX4_DPRINTF("pci_features_read %x\n", 0); | |
93d89f63 IY |
555 | return 0; |
556 | } | |
557 | ||
558 | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) | |
559 | { | |
7faa8075 | 560 | acpi_piix_eject_slot(opaque, val); |
93d89f63 | 561 | |
50d8ff8b | 562 | PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); |
93d89f63 IY |
563 | } |
564 | ||
668643b0 MT |
565 | static uint32_t pcirmv_read(void *opaque, uint32_t addr) |
566 | { | |
567 | PIIX4PMState *s = opaque; | |
568 | ||
569 | return s->pci0_hotplug_enable; | |
570 | } | |
571 | ||
c177684c GH |
572 | static const MemoryRegionOps piix4_pci_ops = { |
573 | .old_portio = (MemoryRegionPortio[]) { | |
574 | { | |
575 | .offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, | |
576 | .read = pci_up_read, | |
577 | },{ | |
578 | .offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, | |
579 | .read = pci_down_read, | |
580 | },{ | |
581 | .offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, | |
582 | .read = pci_features_read, | |
583 | .write = pciej_write, | |
584 | },{ | |
585 | .offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, | |
586 | .read = pcirmv_read, | |
587 | }, | |
588 | PORTIO_END_OF_LIST() | |
589 | }, | |
590 | .endianness = DEVICE_LITTLE_ENDIAN, | |
591 | }; | |
592 | ||
4cff0a59 MT |
593 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
594 | PCIHotplugState state); | |
93d89f63 | 595 | |
ac404095 | 596 | static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
93d89f63 | 597 | { |
b65b93f2 GH |
598 | memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0", |
599 | GPE_LEN); | |
600 | memory_region_add_subregion(get_system_io(), GPE_BASE, &s->io_gpe); | |
ac404095 | 601 | |
c177684c GH |
602 | memory_region_init_io(&s->io_pci, &piix4_pci_ops, s, "apci-pci-hotplug", |
603 | PCI_HOTPLUG_SIZE); | |
604 | memory_region_add_subregion(get_system_io(), PCI_HOTPLUG_ADDR, | |
605 | &s->io_pci); | |
ac404095 | 606 | pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev); |
93d89f63 IY |
607 | } |
608 | ||
ac404095 | 609 | static void enable_device(PIIX4PMState *s, int slot) |
93d89f63 | 610 | { |
355bf2e5 | 611 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 612 | s->pci0_slot_device_present |= (1U << slot); |
93d89f63 IY |
613 | } |
614 | ||
ac404095 | 615 | static void disable_device(PIIX4PMState *s, int slot) |
93d89f63 | 616 | { |
355bf2e5 | 617 | s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS; |
7faa8075 | 618 | s->pci0_status.down |= (1U << slot); |
93d89f63 IY |
619 | } |
620 | ||
4cff0a59 MT |
621 | static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, |
622 | PCIHotplugState state) | |
93d89f63 IY |
623 | { |
624 | int slot = PCI_SLOT(dev->devfn); | |
ac404095 | 625 | PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, |
40021f08 | 626 | PCI_DEVICE(qdev)); |
93d89f63 | 627 | |
4cff0a59 MT |
628 | /* Don't send event when device is enabled during qemu machine creation: |
629 | * it is present on boot, no hotplug event is necessary. We do send an | |
630 | * event when the device is disabled later. */ | |
631 | if (state == PCI_COLDPLUG_ENABLED) { | |
7faa8075 | 632 | s->pci0_slot_device_present |= (1U << slot); |
5beb8ad5 | 633 | return 0; |
4cff0a59 | 634 | } |
5beb8ad5 | 635 | |
4cff0a59 | 636 | if (state == PCI_HOTPLUG_ENABLED) { |
ac404095 IY |
637 | enable_device(s, slot); |
638 | } else { | |
639 | disable_device(s, slot); | |
640 | } | |
633aa0ac GN |
641 | |
642 | pm_update_sci(s); | |
643 | ||
93d89f63 IY |
644 | return 0; |
645 | } |