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Commit | Line | Data |
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80bb2ff7 RH |
1 | /* |
2 | * QEMU Alpha PCI support functions. | |
3 | * | |
4 | * Some of this isn't very Alpha specific at all. | |
5 | * | |
6 | * ??? Sparse memory access not implemented. | |
7 | */ | |
8 | ||
e2e5e114 | 9 | #include "qemu/osdep.h" |
4771d756 PB |
10 | #include "qemu-common.h" |
11 | #include "cpu.h" | |
47b43a1f | 12 | #include "alpha_sys.h" |
1de7afc9 | 13 | #include "qemu/log.h" |
9c17d615 | 14 | #include "sysemu/sysemu.h" |
c6ce9f17 | 15 | #include "trace.h" |
80bb2ff7 RH |
16 | |
17 | ||
3661049f RH |
18 | /* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ |
19 | ||
20 | static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) | |
21 | { | |
22 | return 0; | |
23 | } | |
24 | ||
25 | static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) | |
26 | { | |
27 | } | |
28 | ||
29 | const MemoryRegionOps alpha_pci_ignore_ops = { | |
30 | .read = ignore_read, | |
31 | .write = ignore_write, | |
32 | .endianness = DEVICE_LITTLE_ENDIAN, | |
33 | .valid = { | |
34 | .min_access_size = 1, | |
35 | .max_access_size = 8, | |
36 | }, | |
37 | .impl = { | |
38 | .min_access_size = 1, | |
39 | .max_access_size = 8, | |
40 | }, | |
41 | }; | |
42 | ||
43 | ||
80bb2ff7 | 44 | /* PCI config space reads/writes, to byte-word addressable memory. */ |
a8170e5e | 45 | static uint64_t bw_conf1_read(void *opaque, hwaddr addr, |
80bb2ff7 RH |
46 | unsigned size) |
47 | { | |
48 | PCIBus *b = opaque; | |
49 | return pci_data_read(b, addr, size); | |
50 | } | |
51 | ||
a8170e5e | 52 | static void bw_conf1_write(void *opaque, hwaddr addr, |
80bb2ff7 RH |
53 | uint64_t val, unsigned size) |
54 | { | |
55 | PCIBus *b = opaque; | |
56 | pci_data_write(b, addr, val, size); | |
57 | } | |
58 | ||
59 | const MemoryRegionOps alpha_pci_conf1_ops = { | |
60 | .read = bw_conf1_read, | |
61 | .write = bw_conf1_write, | |
62 | .endianness = DEVICE_LITTLE_ENDIAN, | |
63 | .impl = { | |
64 | .min_access_size = 1, | |
65 | .max_access_size = 4, | |
66 | }, | |
67 | }; | |
68 | ||
69 | /* PCI/EISA Interrupt Acknowledge Cycle. */ | |
70 | ||
a8170e5e | 71 | static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) |
80bb2ff7 RH |
72 | { |
73 | return pic_read_irq(isa_pic); | |
74 | } | |
75 | ||
a8170e5e | 76 | static void special_write(void *opaque, hwaddr addr, |
80bb2ff7 RH |
77 | uint64_t val, unsigned size) |
78 | { | |
c6ce9f17 | 79 | trace_alpha_pci_iack_write(); |
80bb2ff7 RH |
80 | } |
81 | ||
82 | const MemoryRegionOps alpha_pci_iack_ops = { | |
83 | .read = iack_read, | |
84 | .write = special_write, | |
85 | .endianness = DEVICE_LITTLE_ENDIAN, | |
86 | .valid = { | |
87 | .min_access_size = 4, | |
88 | .max_access_size = 4, | |
89 | }, | |
90 | .impl = { | |
91 | .min_access_size = 4, | |
92 | .max_access_size = 4, | |
93 | }, | |
94 | }; |