[mirror_qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "rwhandler.h"
#include "apb_pci.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

#define PBM_PCI_IMR_MASK    0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000

#define POR          (1 << 31)
#define SOFT_POR     (1 << 30)
#define SOFT_XIR     (1 << 29)
#define BTN_POR      (1 << 28)
#define BTN_XIR      (1 << 27)
#define RESET_MASK   0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK  0x60000000

typedef struct APBState {
    SysBusDevice busdev;
    PCIHostState host_state;
    ReadWriteHandler pci_config_handler;
    uint32_t iommu[4];
    uint32_t pci_control[16];
    uint32_t pci_irq_map[8];
    uint32_t obio_irq_map[32];
    qemu_irq pci_irqs[32];
    uint32_t reset_control;
} APBState;

static unsigned int nr_resets;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    APBState *s = opaque;

    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        s->iommu[(addr & 0xf) >> 2] = val;
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        s->pci_control[(addr & 0x3f) >> 2] = val;
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val &= RESET_MASK;
            s->reset_control &= ~(val & RESET_WCMASK);
            s->reset_control |= val & RESET_WMASK;
            if (val & SOFT_POR) {
                nr_resets = 0;
                qemu_system_reset_request();
            } else if (val & SOFT_XIR) {
                qemu_system_reset_request();
            }
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    APBState *s = opaque;
    uint32_t val;

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        val = 0;
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        val = s->iommu[(addr & 0xf) >> 2];
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        val = 0;
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            val = s->pci_irq_map[(addr & 0x3f) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        val = s->pci_control[(addr & 0x3f) >> 2];
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val = s->reset_control;
        } else {
            val = 0;
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        val = 0;
        break;
    }
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);

    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
                                 uint32_t val, int size)
{
    APBState *s = container_of(h, APBState, pci_config_handler);

    val = qemu_bswap_len(val, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
    pci_data_write(s->host_state.bus, addr, val, size);
}

static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
                                    int size)
{
    uint32_t ret;
    APBState *s = container_of(h, APBState, pci_config_handler);

    ret = pci_data_read(s->host_state.bus, addr, size);
    ret = qemu_bswap_len(ret, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    APBState *s = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    if (irq_num < 32) {
        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->pci_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->pci_irqs[irq_num]);
        }
    }
}

static void apb_pci_bridge_init(PCIBus *b)
{
    PCIDevice *dev = pci_bridge_get_device(b);

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY);
    pci_set_word(dev->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
    pci_set_byte(dev->config + PCI_HEADER_TYPE,
                 pci_get_byte(dev->config + PCI_HEADER_TYPE) |
                 PCI_HEADER_TYPE_MULTI_FUNCTION);
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;
    unsigned int i;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* pci_ioport */
    sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
    /* pci_config */
    sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
    /* mem_data */
    sysbus_mmio_map(s, 3, mem_base);
    d = FROM_SYSBUS(APBState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, d,
                                         0, 32);
    pci_bus_set_mem_base(d->host_state.bus, mem_base);

    for (i = 0; i < 32; i++) {
        sysbus_connect_irq(s, i, pic[i]);
    }

    pci_create_simple(d->host_state.bus, 0, "pbm");
    /* APB secondary busses */
    *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 1");
    apb_pci_bridge_init(*bus2);

    *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 2");
    apb_pci_bridge_init(*bus3);

    return d->host_state.bus;
}

static void pci_pbm_reset(DeviceState *d)
{
    unsigned int i;
    APBState *s = container_of(d, APBState, busdev.qdev);

    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
    }

    if (nr_resets++ == 0) {
        /* Power on reset */
        s->reset_control = POR;
    }
}

static int pci_pbm_init_device(SysBusDevice *dev)
{
    APBState *s;
    int pci_mem_data, apb_config, pci_ioport, pci_config;
    unsigned int i;

    s = FROM_SYSBUS(APBState, dev);
    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
    }
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->pci_irqs[i]);
    }

    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s);
    sysbus_init_mmio(dev, 0x10000ULL, apb_config);
    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                          pci_apb_iowrite, s);
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
    /* pci_config */
    s->pci_config_handler.read = apb_pci_config_read;
    s->pci_config_handler.write = apb_pci_config_write;
    pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
    assert(pci_config >= 0);
    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
    /* mem_data */
    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
    sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
    pci_set_word(d->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(d->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    pci_set_byte(d->config + PCI_HEADER_TYPE,
                 PCI_HEADER_TYPE_NORMAL);
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
    .header_type  = PCI_HEADER_TYPE_BRIDGE,
};

static SysBusDeviceInfo pbm_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(APBState),
    .qdev.reset = pci_pbm_reset,
    .init = pci_pbm_init_device,
};
static void pbm_register_devices(void)
{
    sysbus_register_withprop(&pbm_host_info);
    pci_qdev_register(&pbm_pci_host_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
63e6f31d	32	#include "rwhandler.h"
18e08a55	33	#include "apb_pci.h"
a94fd955 BS	34
	35	/* debug APB */
	36	//#define DEBUG_APB
	37
	38	#ifdef DEBUG_APB
001faf32 BS	39	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	40	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	41	#else
001faf32	42	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	43	#endif
a94fd955 BS	44
930f3fe1 BS	45	/*
	46	* Chipset docs:
	47	* PBM: "UltraSPARC IIi User's Manual",
	48	* http://www.sun.com/processors/manuals/805-0087.pdf
	49	*
	50	* APB: "Advanced PCI Bridge (APB) User's Manual",
	51	* http://www.sun.com/processors/manuals/805-1251.pdf
	52	*/
	53
95819af0 BS	54	#define PBM_PCI_IMR_MASK 0x7fffffff
	55	#define PBM_PCI_IMR_ENABLED 0x80000000
	56
	57	#define POR (1 << 31)
	58	#define SOFT_POR (1 << 30)
	59	#define SOFT_XIR (1 << 29)
	60	#define BTN_POR (1 << 28)
	61	#define BTN_XIR (1 << 27)
	62	#define RESET_MASK 0xf8000000
	63	#define RESET_WCMASK 0x98000000
	64	#define RESET_WMASK 0x60000000
	65
72f44c8c BS	66	typedef struct APBState {
	67	SysBusDevice busdev;
	68	PCIHostState host_state;
63e6f31d	69	ReadWriteHandler pci_config_handler;
95819af0 BS	70	uint32_t iommu[4];
	71	uint32_t pci_control[16];
	72	uint32_t pci_irq_map[8];
	73	uint32_t obio_irq_map[32];
	74	qemu_irq pci_irqs[32];
	75	uint32_t reset_control;
72f44c8c	76	} APBState;
502a5395	77
95819af0 BS	78	static unsigned int nr_resets;
95819af0 BS	79
c227f099	80	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	81	uint32_t val)
502a5395	82	{
95819af0 BS	83	APBState *s = opaque;
	84
	85	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	86
	87	switch (addr & 0xffff) {
	88	case 0x30 ... 0x4f: /* DMA error registers */
	89	/* XXX: not implemented yet */
	90	break;
	91	case 0x200 ... 0x20b: /* IOMMU */
	92	s->iommu[(addr & 0xf) >> 2] = val;
	93	break;
	94	case 0x20c ... 0x3ff: /* IOMMU flush */
	95	break;
	96	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	97	if (addr & 4) {
	98	s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
	99	s->pci_irq_map[(addr & 0x3f) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	100	}
	101	break;
	102	case 0x2000 ... 0x202f: /* PCI control */
	103	s->pci_control[(addr & 0x3f) >> 2] = val;
	104	break;
	105	case 0xf020 ... 0xf027: /* Reset control */
	106	if (addr & 4) {
	107	val &= RESET_MASK;
	108	s->reset_control &= ~(val & RESET_WCMASK);
	109	s->reset_control \|= val & RESET_WMASK;
	110	if (val & SOFT_POR) {
	111	nr_resets = 0;
	112	qemu_system_reset_request();
	113	} else if (val & SOFT_XIR) {
	114	qemu_system_reset_request();
	115	}
	116	}
	117	break;
	118	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	119	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	120	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	121	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	122	/* we don't care */
502a5395	123	default:
f930d07e	124	break;
502a5395 PB	125	}
	126	}
	127
	128	static uint32_t apb_config_readl (void *opaque,
c227f099	129	target_phys_addr_t addr)
502a5395	130	{
95819af0	131	APBState *s = opaque;
502a5395 PB	132	uint32_t val;
502a5395 PB	133
95819af0 BS	134	switch (addr & 0xffff) {
	135	case 0x30 ... 0x4f: /* DMA error registers */
	136	val = 0;
	137	/* XXX: not implemented yet */
	138	break;
	139	case 0x200 ... 0x20b: /* IOMMU */
	140	val = s->iommu[(addr & 0xf) >> 2];
	141	break;
	142	case 0x20c ... 0x3ff: /* IOMMU flush */
	143	val = 0;
	144	break;
	145	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	146	if (addr & 4) {
	147	val = s->pci_irq_map[(addr & 0x3f) >> 3];
	148	} else {
	149	val = 0;
	150	}
	151	break;
	152	case 0x2000 ... 0x202f: /* PCI control */
	153	val = s->pci_control[(addr & 0x3f) >> 2];
	154	break;
	155	case 0xf020 ... 0xf027: /* Reset control */
	156	if (addr & 4) {
	157	val = s->reset_control;
	158	} else {
	159	val = 0;
	160	}
	161	break;
	162	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	163	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	164	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	165	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	166	/* we don't care */
502a5395	167	default:
f930d07e BS	168	val = 0;
f930d07e BS	169	break;
502a5395	170	}
95819af0 BS	171	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
95819af0 BS	172
502a5395 PB	173	return val;
	174	}
	175
d60efc6b	176	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	177	&apb_config_writel,
	178	&apb_config_writel,
	179	&apb_config_writel,
	180	};
	181
d60efc6b	182	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	183	&apb_config_readl,
	184	&apb_config_readl,
	185	&apb_config_readl,
	186	};
	187
63e6f31d	188	static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
5a5d4a76 BS	189	uint32_t val, int size)
5a5d4a76 BS	190	{
63e6f31d MT	191	APBState *s = container_of(h, APBState, pci_config_handler);
	192
	193	val = qemu_bswap_len(val, size);
5a5d4a76	194	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
8414f45c	195	pci_data_write(s->host_state.bus, addr, val, size);
5a5d4a76 BS	196	}
5a5d4a76 BS	197
63e6f31d	198	static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
5a5d4a76 BS	199	int size)
	200	{
	201	uint32_t ret;
63e6f31d	202	APBState *s = container_of(h, APBState, pci_config_handler);
5a5d4a76	203
8414f45c	204	ret = pci_data_read(s->host_state.bus, addr, size);
63e6f31d	205	ret = qemu_bswap_len(ret, size);
5a5d4a76 BS	206	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	207	return ret;
	208	}
	209
c227f099	210	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	211	uint32_t val)
502a5395 PB	212	{
afcea8cb	213	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	214	}
502a5395 PB	215
c227f099	216	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	217	uint32_t val)
502a5395 PB	218	{
a4d5f62c	219	cpu_outw(addr & IOPORTS_MASK, bswap16(val));
502a5395 PB	220	}
502a5395 PB	221
c227f099	222	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	223	uint32_t val)
502a5395 PB	224	{
a4d5f62c	225	cpu_outl(addr & IOPORTS_MASK, bswap32(val));
502a5395 PB	226	}
502a5395 PB	227
c227f099	228	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	229	{
	230	uint32_t val;
	231
afcea8cb	232	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	233	return val;
	234	}
	235
c227f099	236	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	237	{
	238	uint32_t val;
	239
a4d5f62c	240	val = bswap16(cpu_inw(addr & IOPORTS_MASK));
502a5395 PB	241	return val;
	242	}
	243
c227f099	244	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	245	{
	246	uint32_t val;
	247
a4d5f62c	248	val = bswap32(cpu_inl(addr & IOPORTS_MASK));
502a5395 PB	249	return val;
	250	}
	251
d60efc6b	252	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	253	&pci_apb_iowriteb,
	254	&pci_apb_iowritew,
	255	&pci_apb_iowritel,
	256	};
	257
d60efc6b	258	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	259	&pci_apb_ioreadb,
	260	&pci_apb_ioreadw,
	261	&pci_apb_ioreadl,
	262	};
	263
80b3ada7	264	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	265	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	266	{
80b3ada7 PB	267	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	268	}
	269
	270	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	271	{
	272	int bus_offset;
	273	if (pci_dev->devfn & 1)
	274	bus_offset = 16;
	275	else
	276	bus_offset = 0;
	277	return bus_offset + irq_num;
d2b59317 PB	278	}
d2b59317 PB	279
5d4e84c8	280	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	281	{
95819af0	282	APBState *s = opaque;
5d4e84c8	283
80b3ada7	284	/* PCI IRQ map onto the first 32 INO. */
95819af0 BS	285	if (irq_num < 32) {
	286	if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
	287	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
	288	qemu_set_irq(s->pci_irqs[irq_num], level);
	289	} else {
	290	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
	291	qemu_irq_lower(s->pci_irqs[irq_num]);
	292	}
	293	}
502a5395 PB	294	}
502a5395 PB	295
d6318738 MT	296	static void apb_pci_bridge_init(PCIBus *b)
	297	{
	298	PCIDevice *dev = pci_bridge_get_device(b);
	299
	300	/*
	301	* command register:
	302	* According to PCI bridge spec, after reset
	303	* bus master bit is off
	304	* memory space enable bit is off
	305	* According to manual (805-1251.pdf).
	306	* the reset value should be zero unless the boot pin is tied high
	307	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	308	*/
	309	pci_set_word(dev->config + PCI_COMMAND,
9fe52c7f BS	310	PCI_COMMAND_MEMORY);
	311	pci_set_word(dev->config + PCI_STATUS,
	312	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	313	PCI_STATUS_DEVSEL_MEDIUM);
	314	pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
	315	pci_set_byte(dev->config + PCI_HEADER_TYPE,
	316	pci_get_byte(dev->config + PCI_HEADER_TYPE) \|
	317	PCI_HEADER_TYPE_MULTI_FUNCTION);
d6318738 MT	318	}
d6318738 MT	319
c227f099 AL	320	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	321	target_phys_addr_t mem_base,
c190ea07	322	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	323	{
72f44c8c BS	324	DeviceState *dev;
	325	SysBusDevice *s;
	326	APBState *d;
95819af0	327	unsigned int i;
502a5395	328
80b3ada7	329	/* Ultrasparc PBM main bus */
72f44c8c	330	dev = qdev_create(NULL, "pbm");
e23a1b33	331	qdev_init_nofail(dev);
72f44c8c BS	332	s = sysbus_from_qdev(dev);
72f44c8c BS	333	/* apb_config */
bae7b517	334	sysbus_mmio_map(s, 0, special_base);
72f44c8c BS	335	/* pci_ioport */
72f44c8c BS	336	sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
204c7a39	337	/* pci_config */
72f44c8c BS	338	sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
72f44c8c BS	339	/* mem_data */
204c7a39	340	sysbus_mmio_map(s, 3, mem_base);
72f44c8c	341	d = FROM_SYSBUS(APBState, s);
c5ff6d54	342	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
95819af0	343	pci_apb_set_irq, pci_pbm_map_irq, d,
72f44c8c	344	0, 32);
f6b6f1bc BS	345	pci_bus_set_mem_base(d->host_state.bus, mem_base);
f6b6f1bc BS	346
95819af0 BS	347	for (i = 0; i < 32; i++) {
	348	sysbus_connect_irq(s, i, pic[i]);
	349	}
	350
72f44c8c BS	351	pci_create_simple(d->host_state.bus, 0, "pbm");
72f44c8c BS	352	/* APB secondary busses */
2217dcff IY	353	*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
	354	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	355	pci_apb_map_irq,
72f44c8c	356	"Advanced PCI Bus secondary bridge 1");
d6318738 MT	357	apb_pci_bridge_init(*bus2);
d6318738 MT	358
2217dcff IY	359	*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
	360	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	361	pci_apb_map_irq,
72f44c8c	362	"Advanced PCI Bus secondary bridge 2");
d6318738	363	apb_pci_bridge_init(*bus3);
502a5395	364
72f44c8c BS	365	return d->host_state.bus;
	366	}
	367
95819af0	368	static void pci_pbm_reset(DeviceState *d)
72f44c8c	369	{
95819af0 BS	370	unsigned int i;
95819af0 BS	371	APBState *s = container_of(d, APBState, busdev.qdev);
72f44c8c	372
95819af0 BS	373	for (i = 0; i < 8; i++) {
	374	s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
	375	}
	376
	377	if (nr_resets++ == 0) {
	378	/* Power on reset */
	379	s->reset_control = POR;
	380	}
	381	}
	382
	383	static int pci_pbm_init_device(SysBusDevice *dev)
	384	{
72f44c8c	385	APBState *s;
204c7a39	386	int pci_mem_data, apb_config, pci_ioport, pci_config;
95819af0	387	unsigned int i;
72f44c8c BS	388
72f44c8c BS	389	s = FROM_SYSBUS(APBState, dev);
95819af0 BS	390	for (i = 0; i < 8; i++) {
	391	s->pci_irq_map[i] = (0x1f << 6) \| (i << 2);
	392	}
	393	for (i = 0; i < 32; i++) {
	394	sysbus_init_irq(dev, &s->pci_irqs[i]);
	395	}
	396
72f44c8c	397	/* apb_config */
1eed09cb	398	apb_config = cpu_register_io_memory(apb_config_read,
f930d07e	399	apb_config_write, s);
bae7b517	400	sysbus_init_mmio(dev, 0x10000ULL, apb_config);
72f44c8c	401	/* pci_ioport */
1eed09cb	402	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
502a5395	403	pci_apb_iowrite, s);
72f44c8c	404	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
5a5d4a76	405	/* pci_config */
63e6f31d MT	406	s->pci_config_handler.read = apb_pci_config_read;
	407	s->pci_config_handler.write = apb_pci_config_write;
	408	pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
	409	assert(pci_config >= 0);
5a5d4a76	410	sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
72f44c8c	411	/* mem_data */
c9a43af9	412	pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
72f44c8c	413	sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
81a322d4	414	return 0;
72f44c8c	415	}
502a5395	416
81a322d4	417	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	418	{
deb54399 AL	419	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
deb54399 AL	420	pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
9fe52c7f BS	421	pci_set_word(d->config + PCI_COMMAND,
	422	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	423	pci_set_word(d->config + PCI_STATUS,
	424	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	425	PCI_STATUS_DEVSEL_MEDIUM);
173a543b	426	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
9fe52c7f BS	427	pci_set_byte(d->config + PCI_HEADER_TYPE,
9fe52c7f BS	428	PCI_HEADER_TYPE_NORMAL);
81a322d4	429	return 0;
72f44c8c	430	}
80b3ada7	431
72f44c8c BS	432	static PCIDeviceInfo pbm_pci_host_info = {
	433	.qdev.name = "pbm",
	434	.qdev.size = sizeof(PCIDevice),
	435	.init = pbm_pci_host_init,
776e1bbb	436	.header_type = PCI_HEADER_TYPE_BRIDGE,
72f44c8c BS	437	};
72f44c8c BS	438
95819af0 BS	439	static SysBusDeviceInfo pbm_host_info = {
	440	.qdev.name = "pbm",
	441	.qdev.size = sizeof(APBState),
	442	.qdev.reset = pci_pbm_reset,
	443	.init = pci_pbm_init_device,
	444	};
72f44c8c BS	445	static void pbm_register_devices(void)
72f44c8c BS	446	{
95819af0	447	sysbus_register_withprop(&pbm_host_info);
72f44c8c	448	pci_qdev_register(&pbm_pci_host_info);
502a5395	449	}
72f44c8c BS	450
72f44c8c BS	451	device_init(pbm_register_devices)