[mirror_qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"

typedef struct APBState {
    SysBusDevice busdev;
    PCIHostState host_state;
} APBState;

static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
                                         uint32_t val)
{
    APBState *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
                val);
    s->host_state.config_reg = val;
}

static uint32_t pci_apb_config_readl (void *opaque,
                                            target_phys_addr_t addr)
{
    APBState *s = opaque;
    uint32_t val;

    val = s->host_state.config_reg;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
                val);
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_config_write[] = {
    &pci_apb_config_writel,
    &pci_apb_config_writel,
    &pci_apb_config_writel,
};

static CPUReadMemoryFunc * const pci_apb_config_read[] = {
    &pci_apb_config_readl,
    &pci_apb_config_readl,
    &pci_apb_config_readl,
};

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    //PCIBus *s = opaque;

    switch (addr & 0x3f) {
    case 0x00: // Control/Status
    case 0x10: // AFSR
    case 0x18: // AFAR
    case 0x20: // Diagnostic
    case 0x28: // Target address space
        // XXX
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    //PCIBus *s = opaque;
    uint32_t val;

    switch (addr & 0x3f) {
    case 0x00: // Control/Status
    case 0x10: // AFSR
    case 0x18: // AFAR
    case 0x20: // Diagnostic
    case 0x28: // Target address space
        // XXX
    default:
        val = 0;
        break;
    }
    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static CPUWriteMemoryFunc * const pci_apb_write[] = {
    &pci_host_data_writeb,
    &pci_host_data_writew,
    &pci_host_data_writel,
};

static CPUReadMemoryFunc * const pci_apb_read[] = {
    &pci_host_data_readb,
    &pci_host_data_readw,
    &pci_host_data_readl,
};

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, val);
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inw(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inl(addr & IOPORTS_MASK);
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    qemu_set_irq(pic[irq_num], level);
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base + 0x2000ULL);
    /* pci_ioport */
    sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
    /* mem_config: XXX size should be 4G-prom */
    sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
    /* mem_data */
    sysbus_mmio_map(s, 3, mem_base);
    d = FROM_SYSBUS(APBState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, pic,
                                         0, 32);
    pci_create_simple(d->host_state.bus, 0, "pbm");
    /* APB secondary busses */
    *bus2 = pci_bridge_init(d->host_state.bus, 8, PCI_VENDOR_ID_SUN,
                            PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 1");
    *bus3 = pci_bridge_init(d->host_state.bus, 9, PCI_VENDOR_ID_SUN,
                            PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 2");

    return d->host_state.bus;
}

static int pci_pbm_init_device(SysBusDevice *dev)
{

    APBState *s;
    int pci_mem_config, pci_mem_data, apb_config, pci_ioport;

    s = FROM_SYSBUS(APBState, dev);
    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s);
    sysbus_init_mmio(dev, 0x40ULL, apb_config);
    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                          pci_apb_iowrite, s);
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
    /* mem_config  */
    pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
                                            pci_apb_config_write, s);
    sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
    /* mem_data */
    pci_mem_data = cpu_register_io_memory(pci_apb_read,
                                          pci_apb_write, &s->host_state);
    sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
    d->config[0x04] = 0x06; // command = bus master, pci mem
    d->config[0x05] = 0x00;
    d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
    d->config[0x07] = 0x03; // status = medium devsel
    d->config[0x08] = 0x00; // revision
    d->config[0x09] = 0x00; // programming i/f
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
};

static void pbm_register_devices(void)
{
    sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
    pci_qdev_register(&pbm_pci_host_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
a94fd955 BS	31
	32	/* debug APB */
	33	//#define DEBUG_APB
	34
	35	#ifdef DEBUG_APB
001faf32 BS	36	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	37	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	38	#else
001faf32	39	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	40	#endif
a94fd955 BS	41
c227f099	42	typedef target_phys_addr_t pci_addr_t;
502a5395 PB	43	#include "pci_host.h"
502a5395 PB	44
72f44c8c BS	45	typedef struct APBState {
	46	SysBusDevice busdev;
	47	PCIHostState host_state;
	48	} APBState;
502a5395	49
c227f099	50	static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
502a5395 PB	51	uint32_t val)
	52	{
	53	APBState *s = opaque;
502a5395	54
a94fd955 BS	55	#ifdef TARGET_WORDS_BIGENDIAN
	56	val = bswap32(val);
	57	#endif
	58	APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
	59	val);
72f44c8c	60	s->host_state.config_reg = val;
502a5395 PB	61	}
	62
	63	static uint32_t pci_apb_config_readl (void *opaque,
c227f099	64	target_phys_addr_t addr)
502a5395 PB	65	{
	66	APBState *s = opaque;
	67	uint32_t val;
502a5395	68
72f44c8c	69	val = s->host_state.config_reg;
a94fd955 BS	70	#ifdef TARGET_WORDS_BIGENDIAN
	71	val = bswap32(val);
	72	#endif
	73	APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
	74	val);
502a5395 PB	75	return val;
	76	}
	77
d60efc6b	78	static CPUWriteMemoryFunc * const pci_apb_config_write[] = {
502a5395 PB	79	&pci_apb_config_writel,
	80	&pci_apb_config_writel,
	81	&pci_apb_config_writel,
	82	};
	83
d60efc6b	84	static CPUReadMemoryFunc * const pci_apb_config_read[] = {
502a5395 PB	85	&pci_apb_config_readl,
	86	&pci_apb_config_readl,
	87	&pci_apb_config_readl,
	88	};
	89
c227f099	90	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	91	uint32_t val)
502a5395 PB	92	{
	93	//PCIBus *s = opaque;
	94
	95	switch (addr & 0x3f) {
	96	case 0x00: // Control/Status
	97	case 0x10: // AFSR
	98	case 0x18: // AFAR
	99	case 0x20: // Diagnostic
	100	case 0x28: // Target address space
f930d07e	101	// XXX
502a5395	102	default:
f930d07e	103	break;
502a5395 PB	104	}
	105	}
	106
	107	static uint32_t apb_config_readl (void *opaque,
c227f099	108	target_phys_addr_t addr)
502a5395 PB	109	{
	110	//PCIBus *s = opaque;
	111	uint32_t val;
	112
	113	switch (addr & 0x3f) {
	114	case 0x00: // Control/Status
	115	case 0x10: // AFSR
	116	case 0x18: // AFAR
	117	case 0x20: // Diagnostic
	118	case 0x28: // Target address space
f930d07e	119	// XXX
502a5395	120	default:
f930d07e BS	121	val = 0;
f930d07e BS	122	break;
502a5395 PB	123	}
	124	return val;
	125	}
	126
d60efc6b	127	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	128	&apb_config_writel,
	129	&apb_config_writel,
	130	&apb_config_writel,
	131	};
	132
d60efc6b	133	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	134	&apb_config_readl,
	135	&apb_config_readl,
	136	&apb_config_readl,
	137	};
	138
d60efc6b	139	static CPUWriteMemoryFunc * const pci_apb_write[] = {
502a5395 PB	140	&pci_host_data_writeb,
	141	&pci_host_data_writew,
	142	&pci_host_data_writel,
	143	};
	144
d60efc6b	145	static CPUReadMemoryFunc * const pci_apb_read[] = {
502a5395 PB	146	&pci_host_data_readb,
	147	&pci_host_data_readw,
	148	&pci_host_data_readl,
	149	};
	150
c227f099	151	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	152	uint32_t val)
502a5395 PB	153	{
afcea8cb	154	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	155	}
502a5395 PB	156
c227f099	157	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	158	uint32_t val)
502a5395 PB	159	{
afcea8cb	160	cpu_outw(addr & IOPORTS_MASK, val);
502a5395 PB	161	}
502a5395 PB	162
c227f099	163	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	164	uint32_t val)
502a5395 PB	165	{
afcea8cb	166	cpu_outl(addr & IOPORTS_MASK, val);
502a5395 PB	167	}
502a5395 PB	168
c227f099	169	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	170	{
	171	uint32_t val;
	172
afcea8cb	173	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	174	return val;
	175	}
	176
c227f099	177	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	178	{
	179	uint32_t val;
	180
afcea8cb	181	val = cpu_inw(addr & IOPORTS_MASK);
502a5395 PB	182	return val;
	183	}
	184
c227f099	185	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	186	{
	187	uint32_t val;
	188
afcea8cb	189	val = cpu_inl(addr & IOPORTS_MASK);
502a5395 PB	190	return val;
	191	}
	192
d60efc6b	193	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	194	&pci_apb_iowriteb,
	195	&pci_apb_iowritew,
	196	&pci_apb_iowritel,
	197	};
	198
d60efc6b	199	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	200	&pci_apb_ioreadb,
	201	&pci_apb_ioreadw,
	202	&pci_apb_ioreadl,
	203	};
	204
80b3ada7	205	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	206	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	207	{
80b3ada7 PB	208	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	209	}
	210
	211	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	212	{
	213	int bus_offset;
	214	if (pci_dev->devfn & 1)
	215	bus_offset = 16;
	216	else
	217	bus_offset = 0;
	218	return bus_offset + irq_num;
d2b59317 PB	219	}
d2b59317 PB	220
5d4e84c8	221	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	222	{
5d4e84c8 JQ	223	qemu_irq *pic = opaque;
5d4e84c8 JQ	224
80b3ada7	225	/* PCI IRQ map onto the first 32 INO. */
d537cf6c	226	qemu_set_irq(pic[irq_num], level);
502a5395 PB	227	}
502a5395 PB	228
c227f099 AL	229	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	230	target_phys_addr_t mem_base,
c190ea07	231	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	232	{
72f44c8c BS	233	DeviceState *dev;
	234	SysBusDevice *s;
	235	APBState *d;
502a5395	236
80b3ada7	237	/* Ultrasparc PBM main bus */
72f44c8c BS	238	dev = qdev_create(NULL, "pbm");
	239	qdev_init(dev);
	240	s = sysbus_from_qdev(dev);
	241	/* apb_config */
	242	sysbus_mmio_map(s, 0, special_base + 0x2000ULL);
	243	/* pci_ioport */
	244	sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
	245	/* mem_config: XXX size should be 4G-prom */
	246	sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
	247	/* mem_data */
	248	sysbus_mmio_map(s, 3, mem_base);
	249	d = FROM_SYSBUS(APBState, s);
c5ff6d54	250	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
72f44c8c BS	251	pci_apb_set_irq, pci_pbm_map_irq, pic,
	252	0, 32);
	253	pci_create_simple(d->host_state.bus, 0, "pbm");
	254	/* APB secondary busses */
	255	*bus2 = pci_bridge_init(d->host_state.bus, 8, PCI_VENDOR_ID_SUN,
	256	PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq,
	257	"Advanced PCI Bus secondary bridge 1");
	258	*bus3 = pci_bridge_init(d->host_state.bus, 9, PCI_VENDOR_ID_SUN,
	259	PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq,
	260	"Advanced PCI Bus secondary bridge 2");
502a5395	261
72f44c8c BS	262	return d->host_state.bus;
	263	}
	264
81a322d4	265	static int pci_pbm_init_device(SysBusDevice *dev)
72f44c8c BS	266	{
	267
	268	APBState *s;
	269	int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
	270
	271	s = FROM_SYSBUS(APBState, dev);
	272	/* apb_config */
1eed09cb	273	apb_config = cpu_register_io_memory(apb_config_read,
f930d07e	274	apb_config_write, s);
72f44c8c BS	275	sysbus_init_mmio(dev, 0x40ULL, apb_config);
72f44c8c BS	276	/* pci_ioport */
1eed09cb	277	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
502a5395	278	pci_apb_iowrite, s);
72f44c8c BS	279	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
	280	/* mem_config */
	281	pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
	282	pci_apb_config_write, s);
	283	sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
	284	/* mem_data */
	285	pci_mem_data = cpu_register_io_memory(pci_apb_read,
	286	pci_apb_write, &s->host_state);
	287	sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
81a322d4	288	return 0;
72f44c8c	289	}
502a5395	290
81a322d4	291	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	292	{
deb54399 AL	293	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
deb54399 AL	294	pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
502a5395 PB	295	d->config[0x04] = 0x06; // command = bus master, pci mem
	296	d->config[0x05] = 0x00;
	297	d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
	298	d->config[0x07] = 0x03; // status = medium devsel
	299	d->config[0x08] = 0x00; // revision
	300	d->config[0x09] = 0x00; // programming i/f
173a543b	301	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395	302	d->config[0x0D] = 0x10; // latency_timer
110c50fd	303	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
81a322d4	304	return 0;
72f44c8c	305	}
80b3ada7	306
72f44c8c BS	307	static PCIDeviceInfo pbm_pci_host_info = {
	308	.qdev.name = "pbm",
	309	.qdev.size = sizeof(PCIDevice),
	310	.init = pbm_pci_host_init,
	311	};
	312
	313	static void pbm_register_devices(void)
	314	{
	315	sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
	316	pci_qdev_register(&pbm_pci_host_info);
502a5395	317	}
72f44c8c BS	318
72f44c8c BS	319	device_init(pbm_register_devices)