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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
87ecb68b PB |
19 | #include "hw.h" |
20 | #include "pc.h" | |
aa28b9bf | 21 | #include "apic.h" |
54c96da7 MT |
22 | #include "pci.h" |
23 | #include "msix.h" | |
87ecb68b | 24 | #include "qemu-timer.h" |
bb7e7293 | 25 | #include "host-utils.h" |
8d2ba1fb | 26 | #include "kvm.h" |
574bbf7b FB |
27 | |
28 | //#define DEBUG_APIC | |
29 | ||
30 | /* APIC Local Vector Table */ | |
31 | #define APIC_LVT_TIMER 0 | |
32 | #define APIC_LVT_THERMAL 1 | |
33 | #define APIC_LVT_PERFORM 2 | |
34 | #define APIC_LVT_LINT0 3 | |
35 | #define APIC_LVT_LINT1 4 | |
36 | #define APIC_LVT_ERROR 5 | |
37 | #define APIC_LVT_NB 6 | |
38 | ||
39 | /* APIC delivery modes */ | |
40 | #define APIC_DM_FIXED 0 | |
41 | #define APIC_DM_LOWPRI 1 | |
42 | #define APIC_DM_SMI 2 | |
43 | #define APIC_DM_NMI 4 | |
44 | #define APIC_DM_INIT 5 | |
45 | #define APIC_DM_SIPI 6 | |
46 | #define APIC_DM_EXTINT 7 | |
47 | ||
d592d303 FB |
48 | /* APIC destination mode */ |
49 | #define APIC_DESTMODE_FLAT 0xf | |
50 | #define APIC_DESTMODE_CLUSTER 1 | |
51 | ||
574bbf7b FB |
52 | #define APIC_TRIGGER_EDGE 0 |
53 | #define APIC_TRIGGER_LEVEL 1 | |
54 | ||
55 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
56 | #define APIC_LVT_MASKED (1<<16) | |
57 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
58 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
59 | #define APIC_INPUT_POLARITY (1<<13) | |
60 | #define APIC_SEND_PENDING (1<<12) | |
61 | ||
62 | #define ESR_ILLEGAL_ADDRESS (1 << 7) | |
63 | ||
64 | #define APIC_SV_ENABLE (1 << 8) | |
65 | ||
d3e9db93 FB |
66 | #define MAX_APICS 255 |
67 | #define MAX_APIC_WORDS 8 | |
68 | ||
54c96da7 MT |
69 | /* Intel APIC constants: from include/asm/msidef.h */ |
70 | #define MSI_DATA_VECTOR_SHIFT 0 | |
71 | #define MSI_DATA_VECTOR_MASK 0x000000ff | |
72 | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 | |
73 | #define MSI_DATA_TRIGGER_SHIFT 15 | |
74 | #define MSI_DATA_LEVEL_SHIFT 14 | |
75 | #define MSI_ADDR_DEST_MODE_SHIFT 2 | |
76 | #define MSI_ADDR_DEST_ID_SHIFT 12 | |
77 | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 | |
78 | ||
79 | #define MSI_ADDR_BASE 0xfee00000 | |
80 | #define MSI_ADDR_SIZE 0x100000 | |
81 | ||
574bbf7b FB |
82 | typedef struct APICState { |
83 | CPUState *cpu_env; | |
84 | uint32_t apicbase; | |
85 | uint8_t id; | |
d592d303 | 86 | uint8_t arb_id; |
574bbf7b FB |
87 | uint8_t tpr; |
88 | uint32_t spurious_vec; | |
d592d303 FB |
89 | uint8_t log_dest; |
90 | uint8_t dest_mode; | |
574bbf7b FB |
91 | uint32_t isr[8]; /* in service register */ |
92 | uint32_t tmr[8]; /* trigger mode register */ | |
93 | uint32_t irr[8]; /* interrupt request register */ | |
94 | uint32_t lvt[APIC_LVT_NB]; | |
95 | uint32_t esr; /* error register */ | |
96 | uint32_t icr[2]; | |
97 | ||
98 | uint32_t divide_conf; | |
99 | int count_shift; | |
100 | uint32_t initial_count; | |
101 | int64_t initial_count_load_time, next_time; | |
678e12cc | 102 | uint32_t idx; |
574bbf7b | 103 | QEMUTimer *timer; |
b09ea7d5 GN |
104 | int sipi_vector; |
105 | int wait_for_sipi; | |
574bbf7b FB |
106 | } APICState; |
107 | ||
108 | static int apic_io_memory; | |
d3e9db93 | 109 | static APICState *local_apics[MAX_APICS + 1]; |
678e12cc | 110 | static int last_apic_idx = 0; |
73822ec8 AL |
111 | static int apic_irq_delivered; |
112 | ||
d592d303 | 113 | |
d592d303 FB |
114 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
115 | static void apic_update_irq(APICState *s); | |
610626af AL |
116 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
117 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 118 | |
3b63c04e AJ |
119 | /* Find first bit starting from msb */ |
120 | static int fls_bit(uint32_t value) | |
121 | { | |
122 | return 31 - clz32(value); | |
123 | } | |
124 | ||
e95f5491 | 125 | /* Find first bit starting from lsb */ |
d3e9db93 FB |
126 | static int ffs_bit(uint32_t value) |
127 | { | |
bb7e7293 | 128 | return ctz32(value); |
d3e9db93 FB |
129 | } |
130 | ||
131 | static inline void set_bit(uint32_t *tab, int index) | |
132 | { | |
133 | int i, mask; | |
134 | i = index >> 5; | |
135 | mask = 1 << (index & 0x1f); | |
136 | tab[i] |= mask; | |
137 | } | |
138 | ||
139 | static inline void reset_bit(uint32_t *tab, int index) | |
140 | { | |
141 | int i, mask; | |
142 | i = index >> 5; | |
143 | mask = 1 << (index & 0x1f); | |
144 | tab[i] &= ~mask; | |
145 | } | |
146 | ||
73822ec8 AL |
147 | static inline int get_bit(uint32_t *tab, int index) |
148 | { | |
149 | int i, mask; | |
150 | i = index >> 5; | |
151 | mask = 1 << (index & 0x1f); | |
152 | return !!(tab[i] & mask); | |
153 | } | |
154 | ||
1a7de94a | 155 | static void apic_local_deliver(CPUState *env, int vector) |
a5b38b51 AJ |
156 | { |
157 | APICState *s = env->apic_state; | |
158 | uint32_t lvt = s->lvt[vector]; | |
159 | int trigger_mode; | |
160 | ||
161 | if (lvt & APIC_LVT_MASKED) | |
162 | return; | |
163 | ||
164 | switch ((lvt >> 8) & 7) { | |
165 | case APIC_DM_SMI: | |
166 | cpu_interrupt(env, CPU_INTERRUPT_SMI); | |
167 | break; | |
168 | ||
169 | case APIC_DM_NMI: | |
170 | cpu_interrupt(env, CPU_INTERRUPT_NMI); | |
171 | break; | |
172 | ||
173 | case APIC_DM_EXTINT: | |
174 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
175 | break; | |
176 | ||
177 | case APIC_DM_FIXED: | |
178 | trigger_mode = APIC_TRIGGER_EDGE; | |
179 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
180 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
181 | trigger_mode = APIC_TRIGGER_LEVEL; | |
182 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
183 | } | |
184 | } | |
185 | ||
1a7de94a AJ |
186 | void apic_deliver_pic_intr(CPUState *env, int level) |
187 | { | |
188 | if (level) | |
189 | apic_local_deliver(env, APIC_LVT_LINT0); | |
190 | else { | |
191 | APICState *s = env->apic_state; | |
192 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; | |
193 | ||
194 | switch ((lvt >> 8) & 7) { | |
195 | case APIC_DM_FIXED: | |
196 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
197 | break; | |
198 | reset_bit(s->irr, lvt & 0xff); | |
199 | /* fall through */ | |
200 | case APIC_DM_EXTINT: | |
201 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
202 | break; | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
d3e9db93 FB |
207 | #define foreach_apic(apic, deliver_bitmask, code) \ |
208 | {\ | |
209 | int __i, __j, __mask;\ | |
210 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
211 | __mask = deliver_bitmask[__i];\ | |
212 | if (__mask) {\ | |
213 | for(__j = 0; __j < 32; __j++) {\ | |
214 | if (__mask & (1 << __j)) {\ | |
215 | apic = local_apics[__i * 32 + __j];\ | |
216 | if (apic) {\ | |
217 | code;\ | |
218 | }\ | |
219 | }\ | |
220 | }\ | |
221 | }\ | |
222 | }\ | |
223 | } | |
224 | ||
5fafdf24 | 225 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
d3e9db93 | 226 | uint8_t delivery_mode, |
d592d303 FB |
227 | uint8_t vector_num, uint8_t polarity, |
228 | uint8_t trigger_mode) | |
229 | { | |
230 | APICState *apic_iter; | |
231 | ||
232 | switch (delivery_mode) { | |
233 | case APIC_DM_LOWPRI: | |
8dd69b8f | 234 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
235 | { |
236 | int i, d; | |
237 | d = -1; | |
238 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
239 | if (deliver_bitmask[i]) { | |
240 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
241 | break; | |
242 | } | |
243 | } | |
244 | if (d >= 0) { | |
245 | apic_iter = local_apics[d]; | |
246 | if (apic_iter) { | |
247 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
248 | } | |
249 | } | |
8dd69b8f | 250 | } |
d3e9db93 | 251 | return; |
8dd69b8f | 252 | |
d592d303 | 253 | case APIC_DM_FIXED: |
d592d303 FB |
254 | break; |
255 | ||
256 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
257 | foreach_apic(apic_iter, deliver_bitmask, |
258 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
259 | return; | |
260 | ||
d592d303 | 261 | case APIC_DM_NMI: |
e2eb9d3e AJ |
262 | foreach_apic(apic_iter, deliver_bitmask, |
263 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
264 | return; | |
d592d303 FB |
265 | |
266 | case APIC_DM_INIT: | |
267 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 268 | foreach_apic(apic_iter, deliver_bitmask, |
b09ea7d5 | 269 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
d592d303 | 270 | return; |
3b46e624 | 271 | |
d592d303 | 272 | case APIC_DM_EXTINT: |
b1fc0348 | 273 | /* handled in I/O APIC code */ |
d592d303 FB |
274 | break; |
275 | ||
276 | default: | |
277 | return; | |
278 | } | |
279 | ||
5fafdf24 | 280 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 281 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 282 | } |
574bbf7b | 283 | |
610626af AL |
284 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
285 | uint8_t delivery_mode, uint8_t vector_num, | |
286 | uint8_t polarity, uint8_t trigger_mode) | |
287 | { | |
288 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
289 | ||
290 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
291 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, | |
292 | trigger_mode); | |
293 | } | |
294 | ||
574bbf7b FB |
295 | void cpu_set_apic_base(CPUState *env, uint64_t val) |
296 | { | |
297 | APICState *s = env->apic_state; | |
298 | #ifdef DEBUG_APIC | |
26a76461 | 299 | printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
574bbf7b | 300 | #endif |
2c7c13d4 AJ |
301 | if (!s) |
302 | return; | |
5fafdf24 | 303 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
304 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
305 | /* if disabled, cannot be enabled again */ | |
306 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
307 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
308 | env->cpuid_features &= ~CPUID_APIC; | |
309 | s->spurious_vec &= ~APIC_SV_ENABLE; | |
310 | } | |
311 | } | |
312 | ||
313 | uint64_t cpu_get_apic_base(CPUState *env) | |
314 | { | |
315 | APICState *s = env->apic_state; | |
316 | #ifdef DEBUG_APIC | |
2c7c13d4 AJ |
317 | printf("cpu_get_apic_base: %016" PRIx64 "\n", |
318 | s ? (uint64_t)s->apicbase: 0); | |
574bbf7b | 319 | #endif |
2c7c13d4 | 320 | return s ? s->apicbase : 0; |
574bbf7b FB |
321 | } |
322 | ||
9230e66e FB |
323 | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val) |
324 | { | |
325 | APICState *s = env->apic_state; | |
2c7c13d4 AJ |
326 | if (!s) |
327 | return; | |
9230e66e | 328 | s->tpr = (val & 0x0f) << 4; |
d592d303 | 329 | apic_update_irq(s); |
9230e66e FB |
330 | } |
331 | ||
332 | uint8_t cpu_get_apic_tpr(CPUX86State *env) | |
333 | { | |
334 | APICState *s = env->apic_state; | |
2c7c13d4 | 335 | return s ? s->tpr >> 4 : 0; |
9230e66e FB |
336 | } |
337 | ||
d592d303 FB |
338 | /* return -1 if no bit is set */ |
339 | static int get_highest_priority_int(uint32_t *tab) | |
340 | { | |
341 | int i; | |
342 | for(i = 7; i >= 0; i--) { | |
343 | if (tab[i] != 0) { | |
3b63c04e | 344 | return i * 32 + fls_bit(tab[i]); |
d592d303 FB |
345 | } |
346 | } | |
347 | return -1; | |
348 | } | |
349 | ||
574bbf7b FB |
350 | static int apic_get_ppr(APICState *s) |
351 | { | |
352 | int tpr, isrv, ppr; | |
353 | ||
354 | tpr = (s->tpr >> 4); | |
355 | isrv = get_highest_priority_int(s->isr); | |
356 | if (isrv < 0) | |
357 | isrv = 0; | |
358 | isrv >>= 4; | |
359 | if (tpr >= isrv) | |
360 | ppr = s->tpr; | |
361 | else | |
362 | ppr = isrv << 4; | |
363 | return ppr; | |
364 | } | |
365 | ||
d592d303 FB |
366 | static int apic_get_arb_pri(APICState *s) |
367 | { | |
368 | /* XXX: arbitration */ | |
369 | return 0; | |
370 | } | |
371 | ||
574bbf7b FB |
372 | /* signal the CPU if an irq is pending */ |
373 | static void apic_update_irq(APICState *s) | |
374 | { | |
d592d303 FB |
375 | int irrv, ppr; |
376 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
377 | return; | |
574bbf7b FB |
378 | irrv = get_highest_priority_int(s->irr); |
379 | if (irrv < 0) | |
380 | return; | |
d592d303 FB |
381 | ppr = apic_get_ppr(s); |
382 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) | |
574bbf7b FB |
383 | return; |
384 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); | |
385 | } | |
386 | ||
73822ec8 AL |
387 | void apic_reset_irq_delivered(void) |
388 | { | |
389 | apic_irq_delivered = 0; | |
390 | } | |
391 | ||
392 | int apic_get_irq_delivered(void) | |
393 | { | |
394 | return apic_irq_delivered; | |
395 | } | |
396 | ||
574bbf7b FB |
397 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
398 | { | |
73822ec8 AL |
399 | apic_irq_delivered += !get_bit(s->irr, vector_num); |
400 | ||
574bbf7b FB |
401 | set_bit(s->irr, vector_num); |
402 | if (trigger_mode) | |
403 | set_bit(s->tmr, vector_num); | |
404 | else | |
405 | reset_bit(s->tmr, vector_num); | |
406 | apic_update_irq(s); | |
407 | } | |
408 | ||
409 | static void apic_eoi(APICState *s) | |
410 | { | |
411 | int isrv; | |
412 | isrv = get_highest_priority_int(s->isr); | |
413 | if (isrv < 0) | |
414 | return; | |
415 | reset_bit(s->isr, isrv); | |
d592d303 FB |
416 | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to |
417 | set the remote IRR bit for level triggered interrupts. */ | |
574bbf7b FB |
418 | apic_update_irq(s); |
419 | } | |
420 | ||
678e12cc GN |
421 | static int apic_find_dest(uint8_t dest) |
422 | { | |
423 | APICState *apic = local_apics[dest]; | |
424 | int i; | |
425 | ||
426 | if (apic && apic->id == dest) | |
427 | return dest; /* shortcut in case apic->id == apic->idx */ | |
428 | ||
429 | for (i = 0; i < MAX_APICS; i++) { | |
430 | apic = local_apics[i]; | |
431 | if (apic && apic->id == dest) | |
432 | return i; | |
433 | } | |
434 | ||
435 | return -1; | |
436 | } | |
437 | ||
d3e9db93 FB |
438 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
439 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 440 | { |
d592d303 | 441 | APICState *apic_iter; |
d3e9db93 | 442 | int i; |
d592d303 FB |
443 | |
444 | if (dest_mode == 0) { | |
d3e9db93 FB |
445 | if (dest == 0xff) { |
446 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
447 | } else { | |
678e12cc | 448 | int idx = apic_find_dest(dest); |
d3e9db93 | 449 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc GN |
450 | if (idx >= 0) |
451 | set_bit(deliver_bitmask, idx); | |
d3e9db93 | 452 | } |
d592d303 FB |
453 | } else { |
454 | /* XXX: cluster mode */ | |
d3e9db93 FB |
455 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
456 | for(i = 0; i < MAX_APICS; i++) { | |
457 | apic_iter = local_apics[i]; | |
458 | if (apic_iter) { | |
459 | if (apic_iter->dest_mode == 0xf) { | |
460 | if (dest & apic_iter->log_dest) | |
461 | set_bit(deliver_bitmask, i); | |
462 | } else if (apic_iter->dest_mode == 0x0) { | |
463 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
464 | (dest & apic_iter->log_dest & 0x0f)) { | |
465 | set_bit(deliver_bitmask, i); | |
466 | } | |
467 | } | |
468 | } | |
d592d303 FB |
469 | } |
470 | } | |
d592d303 FB |
471 | } |
472 | ||
473 | ||
b09ea7d5 | 474 | void apic_init_reset(CPUState *env) |
d592d303 | 475 | { |
b09ea7d5 | 476 | APICState *s = env->apic_state; |
d592d303 FB |
477 | int i; |
478 | ||
b09ea7d5 GN |
479 | if (!s) |
480 | return; | |
481 | ||
d592d303 FB |
482 | s->tpr = 0; |
483 | s->spurious_vec = 0xff; | |
484 | s->log_dest = 0; | |
e0fd8781 | 485 | s->dest_mode = 0xf; |
d592d303 FB |
486 | memset(s->isr, 0, sizeof(s->isr)); |
487 | memset(s->tmr, 0, sizeof(s->tmr)); | |
488 | memset(s->irr, 0, sizeof(s->irr)); | |
b4511723 FB |
489 | for(i = 0; i < APIC_LVT_NB; i++) |
490 | s->lvt[i] = 1 << 16; /* mask LVT */ | |
d592d303 FB |
491 | s->esr = 0; |
492 | memset(s->icr, 0, sizeof(s->icr)); | |
493 | s->divide_conf = 0; | |
494 | s->count_shift = 0; | |
495 | s->initial_count = 0; | |
496 | s->initial_count_load_time = 0; | |
497 | s->next_time = 0; | |
b09ea7d5 | 498 | s->wait_for_sipi = 1; |
3003b8bb | 499 | |
b09ea7d5 | 500 | env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
d592d303 FB |
501 | } |
502 | ||
e0fd8781 FB |
503 | static void apic_startup(APICState *s, int vector_num) |
504 | { | |
b09ea7d5 GN |
505 | s->sipi_vector = vector_num; |
506 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); | |
507 | } | |
508 | ||
509 | void apic_sipi(CPUState *env) | |
510 | { | |
511 | APICState *s = env->apic_state; | |
512 | ||
513 | cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); | |
514 | ||
515 | if (!s->wait_for_sipi) | |
e0fd8781 | 516 | return; |
b09ea7d5 | 517 | |
e0fd8781 | 518 | env->eip = 0; |
b09ea7d5 | 519 | cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
19a2223f | 520 | env->segs[R_CS].limit, env->segs[R_CS].flags); |
ce5232c5 | 521 | env->halted = 0; |
b09ea7d5 | 522 | s->wait_for_sipi = 0; |
e0fd8781 FB |
523 | } |
524 | ||
d592d303 FB |
525 | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
526 | uint8_t delivery_mode, uint8_t vector_num, | |
527 | uint8_t polarity, uint8_t trigger_mode) | |
528 | { | |
d3e9db93 | 529 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 FB |
530 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
531 | APICState *apic_iter; | |
532 | ||
e0fd8781 | 533 | switch (dest_shorthand) { |
d3e9db93 FB |
534 | case 0: |
535 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
536 | break; | |
537 | case 1: | |
538 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
678e12cc | 539 | set_bit(deliver_bitmask, s->idx); |
d3e9db93 FB |
540 | break; |
541 | case 2: | |
542 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
543 | break; | |
544 | case 3: | |
545 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
678e12cc | 546 | reset_bit(deliver_bitmask, s->idx); |
d3e9db93 | 547 | break; |
e0fd8781 FB |
548 | } |
549 | ||
d592d303 | 550 | switch (delivery_mode) { |
d592d303 FB |
551 | case APIC_DM_INIT: |
552 | { | |
553 | int trig_mode = (s->icr[0] >> 15) & 1; | |
554 | int level = (s->icr[0] >> 14) & 1; | |
555 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 556 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 557 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
558 | return; |
559 | } | |
560 | } | |
561 | break; | |
562 | ||
563 | case APIC_DM_SIPI: | |
5fafdf24 | 564 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 565 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
566 | return; |
567 | } | |
568 | ||
d592d303 FB |
569 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
570 | trigger_mode); | |
571 | } | |
572 | ||
574bbf7b FB |
573 | int apic_get_interrupt(CPUState *env) |
574 | { | |
575 | APICState *s = env->apic_state; | |
576 | int intno; | |
577 | ||
578 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
579 | IRQs */ | |
580 | if (!s) | |
581 | return -1; | |
582 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
583 | return -1; | |
3b46e624 | 584 | |
574bbf7b FB |
585 | /* XXX: spurious IRQ handling */ |
586 | intno = get_highest_priority_int(s->irr); | |
587 | if (intno < 0) | |
588 | return -1; | |
d592d303 FB |
589 | if (s->tpr && intno <= s->tpr) |
590 | return s->spurious_vec & 0xff; | |
b4511723 | 591 | reset_bit(s->irr, intno); |
574bbf7b FB |
592 | set_bit(s->isr, intno); |
593 | apic_update_irq(s); | |
594 | return intno; | |
595 | } | |
596 | ||
0e21e12b TS |
597 | int apic_accept_pic_intr(CPUState *env) |
598 | { | |
599 | APICState *s = env->apic_state; | |
600 | uint32_t lvt0; | |
601 | ||
602 | if (!s) | |
603 | return -1; | |
604 | ||
605 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
606 | ||
a5b38b51 AJ |
607 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
608 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
609 | return 1; |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
574bbf7b FB |
614 | static uint32_t apic_get_current_count(APICState *s) |
615 | { | |
616 | int64_t d; | |
617 | uint32_t val; | |
5fafdf24 | 618 | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
619 | s->count_shift; |
620 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
621 | /* periodic */ | |
d592d303 | 622 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
623 | } else { |
624 | if (d >= s->initial_count) | |
625 | val = 0; | |
626 | else | |
627 | val = s->initial_count - d; | |
628 | } | |
629 | return val; | |
630 | } | |
631 | ||
632 | static void apic_timer_update(APICState *s, int64_t current_time) | |
633 | { | |
634 | int64_t next_time, d; | |
3b46e624 | 635 | |
574bbf7b | 636 | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { |
5fafdf24 | 637 | d = (current_time - s->initial_count_load_time) >> |
574bbf7b FB |
638 | s->count_shift; |
639 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
681f8c29 AL |
640 | if (!s->initial_count) |
641 | goto no_timer; | |
d592d303 | 642 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
574bbf7b FB |
643 | } else { |
644 | if (d >= s->initial_count) | |
645 | goto no_timer; | |
d592d303 | 646 | d = (uint64_t)s->initial_count + 1; |
574bbf7b FB |
647 | } |
648 | next_time = s->initial_count_load_time + (d << s->count_shift); | |
649 | qemu_mod_timer(s->timer, next_time); | |
650 | s->next_time = next_time; | |
651 | } else { | |
652 | no_timer: | |
653 | qemu_del_timer(s->timer); | |
654 | } | |
655 | } | |
656 | ||
657 | static void apic_timer(void *opaque) | |
658 | { | |
659 | APICState *s = opaque; | |
660 | ||
a5b38b51 | 661 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
574bbf7b FB |
662 | apic_timer_update(s, s->next_time); |
663 | } | |
664 | ||
c227f099 | 665 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
666 | { |
667 | return 0; | |
668 | } | |
669 | ||
c227f099 | 670 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
671 | { |
672 | return 0; | |
673 | } | |
674 | ||
c227f099 | 675 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
676 | { |
677 | } | |
678 | ||
c227f099 | 679 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
680 | { |
681 | } | |
682 | ||
c227f099 | 683 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
574bbf7b FB |
684 | { |
685 | CPUState *env; | |
686 | APICState *s; | |
687 | uint32_t val; | |
688 | int index; | |
689 | ||
690 | env = cpu_single_env; | |
691 | if (!env) | |
692 | return 0; | |
693 | s = env->apic_state; | |
694 | ||
695 | index = (addr >> 4) & 0xff; | |
696 | switch(index) { | |
697 | case 0x02: /* id */ | |
698 | val = s->id << 24; | |
699 | break; | |
700 | case 0x03: /* version */ | |
701 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
702 | break; | |
703 | case 0x08: | |
704 | val = s->tpr; | |
705 | break; | |
d592d303 FB |
706 | case 0x09: |
707 | val = apic_get_arb_pri(s); | |
708 | break; | |
574bbf7b FB |
709 | case 0x0a: |
710 | /* ppr */ | |
711 | val = apic_get_ppr(s); | |
712 | break; | |
b237db36 AJ |
713 | case 0x0b: |
714 | val = 0; | |
715 | break; | |
d592d303 FB |
716 | case 0x0d: |
717 | val = s->log_dest << 24; | |
718 | break; | |
719 | case 0x0e: | |
720 | val = s->dest_mode << 28; | |
721 | break; | |
574bbf7b FB |
722 | case 0x0f: |
723 | val = s->spurious_vec; | |
724 | break; | |
725 | case 0x10 ... 0x17: | |
726 | val = s->isr[index & 7]; | |
727 | break; | |
728 | case 0x18 ... 0x1f: | |
729 | val = s->tmr[index & 7]; | |
730 | break; | |
731 | case 0x20 ... 0x27: | |
732 | val = s->irr[index & 7]; | |
733 | break; | |
734 | case 0x28: | |
735 | val = s->esr; | |
736 | break; | |
574bbf7b FB |
737 | case 0x30: |
738 | case 0x31: | |
739 | val = s->icr[index & 1]; | |
740 | break; | |
e0fd8781 FB |
741 | case 0x32 ... 0x37: |
742 | val = s->lvt[index - 0x32]; | |
743 | break; | |
574bbf7b FB |
744 | case 0x38: |
745 | val = s->initial_count; | |
746 | break; | |
747 | case 0x39: | |
748 | val = apic_get_current_count(s); | |
749 | break; | |
750 | case 0x3e: | |
751 | val = s->divide_conf; | |
752 | break; | |
753 | default: | |
754 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
755 | val = 0; | |
756 | break; | |
757 | } | |
758 | #ifdef DEBUG_APIC | |
759 | printf("APIC read: %08x = %08x\n", (uint32_t)addr, val); | |
760 | #endif | |
761 | return val; | |
762 | } | |
763 | ||
c227f099 | 764 | static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
54c96da7 MT |
765 | { |
766 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
767 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
768 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
769 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
770 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
771 | /* XXX: Ignore redirection hint. */ | |
772 | apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode); | |
773 | } | |
774 | ||
c227f099 | 775 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
574bbf7b FB |
776 | { |
777 | CPUState *env; | |
778 | APICState *s; | |
54c96da7 MT |
779 | int index = (addr >> 4) & 0xff; |
780 | if (addr > 0xfff || !index) { | |
781 | /* MSI and MMIO APIC are at the same memory location, | |
782 | * but actually not on the global bus: MSI is on PCI bus | |
783 | * APIC is connected directly to the CPU. | |
784 | * Mapping them on the global bus happens to work because | |
785 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
786 | apic_send_msi(addr, val); | |
787 | return; | |
788 | } | |
574bbf7b FB |
789 | |
790 | env = cpu_single_env; | |
791 | if (!env) | |
792 | return; | |
793 | s = env->apic_state; | |
794 | ||
795 | #ifdef DEBUG_APIC | |
796 | printf("APIC write: %08x = %08x\n", (uint32_t)addr, val); | |
797 | #endif | |
798 | ||
574bbf7b FB |
799 | switch(index) { |
800 | case 0x02: | |
801 | s->id = (val >> 24); | |
802 | break; | |
e0fd8781 FB |
803 | case 0x03: |
804 | break; | |
574bbf7b FB |
805 | case 0x08: |
806 | s->tpr = val; | |
d592d303 | 807 | apic_update_irq(s); |
574bbf7b | 808 | break; |
e0fd8781 FB |
809 | case 0x09: |
810 | case 0x0a: | |
811 | break; | |
574bbf7b FB |
812 | case 0x0b: /* EOI */ |
813 | apic_eoi(s); | |
814 | break; | |
d592d303 FB |
815 | case 0x0d: |
816 | s->log_dest = val >> 24; | |
817 | break; | |
818 | case 0x0e: | |
819 | s->dest_mode = val >> 28; | |
820 | break; | |
574bbf7b FB |
821 | case 0x0f: |
822 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 823 | apic_update_irq(s); |
574bbf7b | 824 | break; |
e0fd8781 FB |
825 | case 0x10 ... 0x17: |
826 | case 0x18 ... 0x1f: | |
827 | case 0x20 ... 0x27: | |
828 | case 0x28: | |
829 | break; | |
574bbf7b | 830 | case 0x30: |
d592d303 FB |
831 | s->icr[0] = val; |
832 | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, | |
833 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), | |
834 | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); | |
835 | break; | |
574bbf7b | 836 | case 0x31: |
d592d303 | 837 | s->icr[1] = val; |
574bbf7b FB |
838 | break; |
839 | case 0x32 ... 0x37: | |
840 | { | |
841 | int n = index - 0x32; | |
842 | s->lvt[n] = val; | |
843 | if (n == APIC_LVT_TIMER) | |
844 | apic_timer_update(s, qemu_get_clock(vm_clock)); | |
845 | } | |
846 | break; | |
847 | case 0x38: | |
848 | s->initial_count = val; | |
849 | s->initial_count_load_time = qemu_get_clock(vm_clock); | |
850 | apic_timer_update(s, s->initial_count_load_time); | |
851 | break; | |
e0fd8781 FB |
852 | case 0x39: |
853 | break; | |
574bbf7b FB |
854 | case 0x3e: |
855 | { | |
856 | int v; | |
857 | s->divide_conf = val & 0xb; | |
858 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
859 | s->count_shift = (v + 1) & 7; | |
860 | } | |
861 | break; | |
862 | default: | |
863 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
864 | break; | |
865 | } | |
866 | } | |
867 | ||
695dcf71 JQ |
868 | /* This function is only used for old state version 1 and 2 */ |
869 | static int apic_load_old(QEMUFile *f, void *opaque, int version_id) | |
d592d303 FB |
870 | { |
871 | APICState *s = opaque; | |
872 | int i; | |
873 | ||
e6cf6a8c | 874 | if (version_id > 2) |
d592d303 FB |
875 | return -EINVAL; |
876 | ||
877 | /* XXX: what if the base changes? (registered memory regions) */ | |
878 | qemu_get_be32s(f, &s->apicbase); | |
879 | qemu_get_8s(f, &s->id); | |
880 | qemu_get_8s(f, &s->arb_id); | |
881 | qemu_get_8s(f, &s->tpr); | |
882 | qemu_get_be32s(f, &s->spurious_vec); | |
883 | qemu_get_8s(f, &s->log_dest); | |
884 | qemu_get_8s(f, &s->dest_mode); | |
885 | for (i = 0; i < 8; i++) { | |
886 | qemu_get_be32s(f, &s->isr[i]); | |
887 | qemu_get_be32s(f, &s->tmr[i]); | |
888 | qemu_get_be32s(f, &s->irr[i]); | |
889 | } | |
890 | for (i = 0; i < APIC_LVT_NB; i++) { | |
891 | qemu_get_be32s(f, &s->lvt[i]); | |
892 | } | |
893 | qemu_get_be32s(f, &s->esr); | |
894 | qemu_get_be32s(f, &s->icr[0]); | |
895 | qemu_get_be32s(f, &s->icr[1]); | |
896 | qemu_get_be32s(f, &s->divide_conf); | |
bee8d684 | 897 | s->count_shift=qemu_get_be32(f); |
d592d303 | 898 | qemu_get_be32s(f, &s->initial_count); |
bee8d684 TS |
899 | s->initial_count_load_time=qemu_get_be64(f); |
900 | s->next_time=qemu_get_be64(f); | |
e6cf6a8c FB |
901 | |
902 | if (version_id >= 2) | |
903 | qemu_get_timer(f, s->timer); | |
d592d303 FB |
904 | return 0; |
905 | } | |
574bbf7b | 906 | |
695dcf71 JQ |
907 | static const VMStateDescription vmstate_apic = { |
908 | .name = "apic", | |
909 | .version_id = 3, | |
910 | .minimum_version_id = 3, | |
911 | .minimum_version_id_old = 1, | |
912 | .load_state_old = apic_load_old, | |
913 | .fields = (VMStateField []) { | |
914 | VMSTATE_UINT32(apicbase, APICState), | |
915 | VMSTATE_UINT8(id, APICState), | |
916 | VMSTATE_UINT8(arb_id, APICState), | |
917 | VMSTATE_UINT8(tpr, APICState), | |
918 | VMSTATE_UINT32(spurious_vec, APICState), | |
919 | VMSTATE_UINT8(log_dest, APICState), | |
920 | VMSTATE_UINT8(dest_mode, APICState), | |
921 | VMSTATE_UINT32_ARRAY(isr, APICState, 8), | |
922 | VMSTATE_UINT32_ARRAY(tmr, APICState, 8), | |
923 | VMSTATE_UINT32_ARRAY(irr, APICState, 8), | |
924 | VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), | |
925 | VMSTATE_UINT32(esr, APICState), | |
926 | VMSTATE_UINT32_ARRAY(icr, APICState, 2), | |
927 | VMSTATE_UINT32(divide_conf, APICState), | |
928 | VMSTATE_INT32(count_shift, APICState), | |
929 | VMSTATE_UINT32(initial_count, APICState), | |
930 | VMSTATE_INT64(initial_count_load_time, APICState), | |
931 | VMSTATE_INT64(next_time, APICState), | |
932 | VMSTATE_TIMER(timer, APICState), | |
933 | VMSTATE_END_OF_LIST() | |
934 | } | |
935 | }; | |
936 | ||
d592d303 FB |
937 | static void apic_reset(void *opaque) |
938 | { | |
939 | APICState *s = opaque; | |
4c0960c0 | 940 | int bsp; |
fec5fa02 | 941 | |
4c0960c0 | 942 | bsp = cpu_is_bsp(s->cpu_env); |
fec5fa02 | 943 | s->apicbase = 0xfee00000 | |
678e12cc | 944 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
fec5fa02 | 945 | |
b09ea7d5 GN |
946 | cpu_reset(s->cpu_env); |
947 | apic_init_reset(s->cpu_env); | |
0e21e12b | 948 | |
678e12cc | 949 | if (bsp) { |
a5b38b51 AJ |
950 | /* |
951 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
952 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
953 | * processor when local APIC is enabled. | |
954 | */ | |
955 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
956 | } | |
d592d303 | 957 | } |
574bbf7b | 958 | |
d60efc6b | 959 | static CPUReadMemoryFunc * const apic_mem_read[3] = { |
574bbf7b FB |
960 | apic_mem_readb, |
961 | apic_mem_readw, | |
962 | apic_mem_readl, | |
963 | }; | |
964 | ||
d60efc6b | 965 | static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
574bbf7b FB |
966 | apic_mem_writeb, |
967 | apic_mem_writew, | |
968 | apic_mem_writel, | |
969 | }; | |
970 | ||
971 | int apic_init(CPUState *env) | |
972 | { | |
973 | APICState *s; | |
574bbf7b | 974 | |
678e12cc | 975 | if (last_apic_idx >= MAX_APICS) |
d3e9db93 | 976 | return -1; |
d592d303 | 977 | s = qemu_mallocz(sizeof(APICState)); |
574bbf7b | 978 | env->apic_state = s; |
678e12cc GN |
979 | s->idx = last_apic_idx++; |
980 | s->id = env->cpuid_apic_id; | |
574bbf7b | 981 | s->cpu_env = env; |
574bbf7b | 982 | |
54c96da7 | 983 | msix_supported = 1; |
0e21e12b | 984 | |
d592d303 | 985 | /* XXX: mapping more APICs at the same memory location */ |
574bbf7b FB |
986 | if (apic_io_memory == 0) { |
987 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
988 | on the global memory bus. */ | |
1eed09cb | 989 | apic_io_memory = cpu_register_io_memory(apic_mem_read, |
574bbf7b | 990 | apic_mem_write, NULL); |
54c96da7 MT |
991 | /* XXX: what if the base changes? */ |
992 | cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, | |
d592d303 | 993 | apic_io_memory); |
574bbf7b FB |
994 | } |
995 | s->timer = qemu_new_timer(vm_clock, apic_timer, s); | |
d592d303 | 996 | |
695dcf71 | 997 | vmstate_register(s->idx, &vmstate_apic, s); |
a08d4367 | 998 | qemu_register_reset(apic_reset, s); |
3b46e624 | 999 | |
678e12cc | 1000 | local_apics[s->idx] = s; |
d592d303 FB |
1001 | return 0; |
1002 | } |