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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
87ecb68b PB |
20 | #include "hw.h" |
21 | #include "pc.h" | |
22 | #include "qemu-timer.h" | |
574bbf7b FB |
23 | |
24 | //#define DEBUG_APIC | |
d592d303 | 25 | //#define DEBUG_IOAPIC |
574bbf7b FB |
26 | |
27 | /* APIC Local Vector Table */ | |
28 | #define APIC_LVT_TIMER 0 | |
29 | #define APIC_LVT_THERMAL 1 | |
30 | #define APIC_LVT_PERFORM 2 | |
31 | #define APIC_LVT_LINT0 3 | |
32 | #define APIC_LVT_LINT1 4 | |
33 | #define APIC_LVT_ERROR 5 | |
34 | #define APIC_LVT_NB 6 | |
35 | ||
36 | /* APIC delivery modes */ | |
37 | #define APIC_DM_FIXED 0 | |
38 | #define APIC_DM_LOWPRI 1 | |
39 | #define APIC_DM_SMI 2 | |
40 | #define APIC_DM_NMI 4 | |
41 | #define APIC_DM_INIT 5 | |
42 | #define APIC_DM_SIPI 6 | |
43 | #define APIC_DM_EXTINT 7 | |
44 | ||
d592d303 FB |
45 | /* APIC destination mode */ |
46 | #define APIC_DESTMODE_FLAT 0xf | |
47 | #define APIC_DESTMODE_CLUSTER 1 | |
48 | ||
574bbf7b FB |
49 | #define APIC_TRIGGER_EDGE 0 |
50 | #define APIC_TRIGGER_LEVEL 1 | |
51 | ||
52 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
53 | #define APIC_LVT_MASKED (1<<16) | |
54 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
55 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
56 | #define APIC_INPUT_POLARITY (1<<13) | |
57 | #define APIC_SEND_PENDING (1<<12) | |
58 | ||
d592d303 FB |
59 | #define IOAPIC_NUM_PINS 0x18 |
60 | ||
574bbf7b FB |
61 | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
62 | ||
63 | #define APIC_SV_ENABLE (1 << 8) | |
64 | ||
d3e9db93 FB |
65 | #define MAX_APICS 255 |
66 | #define MAX_APIC_WORDS 8 | |
67 | ||
574bbf7b FB |
68 | typedef struct APICState { |
69 | CPUState *cpu_env; | |
70 | uint32_t apicbase; | |
71 | uint8_t id; | |
d592d303 | 72 | uint8_t arb_id; |
574bbf7b FB |
73 | uint8_t tpr; |
74 | uint32_t spurious_vec; | |
d592d303 FB |
75 | uint8_t log_dest; |
76 | uint8_t dest_mode; | |
574bbf7b FB |
77 | uint32_t isr[8]; /* in service register */ |
78 | uint32_t tmr[8]; /* trigger mode register */ | |
79 | uint32_t irr[8]; /* interrupt request register */ | |
80 | uint32_t lvt[APIC_LVT_NB]; | |
81 | uint32_t esr; /* error register */ | |
82 | uint32_t icr[2]; | |
83 | ||
84 | uint32_t divide_conf; | |
85 | int count_shift; | |
86 | uint32_t initial_count; | |
87 | int64_t initial_count_load_time, next_time; | |
88 | QEMUTimer *timer; | |
89 | } APICState; | |
90 | ||
d592d303 FB |
91 | struct IOAPICState { |
92 | uint8_t id; | |
93 | uint8_t ioregsel; | |
94 | ||
95 | uint32_t irr; | |
96 | uint64_t ioredtbl[IOAPIC_NUM_PINS]; | |
97 | }; | |
98 | ||
574bbf7b | 99 | static int apic_io_memory; |
d3e9db93 | 100 | static APICState *local_apics[MAX_APICS + 1]; |
d592d303 | 101 | static int last_apic_id = 0; |
d592d303 FB |
102 | |
103 | static void apic_init_ipi(APICState *s); | |
104 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); | |
105 | static void apic_update_irq(APICState *s); | |
106 | ||
d3e9db93 FB |
107 | /* Find first bit starting from msb. Return 0 if value = 0 */ |
108 | static int fls_bit(uint32_t value) | |
109 | { | |
110 | unsigned int ret = 0; | |
111 | ||
112 | #if defined(HOST_I386) | |
113 | __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value)); | |
114 | return ret; | |
115 | #else | |
116 | if (value > 0xffff) | |
117 | value >>= 16, ret = 16; | |
118 | if (value > 0xff) | |
119 | value >>= 8, ret += 8; | |
120 | if (value > 0xf) | |
121 | value >>= 4, ret += 4; | |
122 | if (value > 0x3) | |
123 | value >>= 2, ret += 2; | |
124 | return ret + (value >> 1); | |
125 | #endif | |
126 | } | |
127 | ||
128 | /* Find first bit starting from lsb. Return 0 if value = 0 */ | |
129 | static int ffs_bit(uint32_t value) | |
130 | { | |
131 | unsigned int ret = 0; | |
132 | ||
133 | #if defined(HOST_I386) | |
134 | __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value)); | |
135 | return ret; | |
136 | #else | |
137 | if (!value) | |
138 | return 0; | |
139 | if (!(value & 0xffff)) | |
140 | value >>= 16, ret = 16; | |
141 | if (!(value & 0xff)) | |
142 | value >>= 8, ret += 8; | |
143 | if (!(value & 0xf)) | |
144 | value >>= 4, ret += 4; | |
145 | if (!(value & 0x3)) | |
146 | value >>= 2, ret += 2; | |
147 | if (!(value & 0x1)) | |
148 | ret++; | |
149 | return ret; | |
150 | #endif | |
151 | } | |
152 | ||
153 | static inline void set_bit(uint32_t *tab, int index) | |
154 | { | |
155 | int i, mask; | |
156 | i = index >> 5; | |
157 | mask = 1 << (index & 0x1f); | |
158 | tab[i] |= mask; | |
159 | } | |
160 | ||
161 | static inline void reset_bit(uint32_t *tab, int index) | |
162 | { | |
163 | int i, mask; | |
164 | i = index >> 5; | |
165 | mask = 1 << (index & 0x1f); | |
166 | tab[i] &= ~mask; | |
167 | } | |
168 | ||
a5b38b51 AJ |
169 | void apic_local_deliver(CPUState *env, int vector) |
170 | { | |
171 | APICState *s = env->apic_state; | |
172 | uint32_t lvt = s->lvt[vector]; | |
173 | int trigger_mode; | |
174 | ||
175 | if (lvt & APIC_LVT_MASKED) | |
176 | return; | |
177 | ||
178 | switch ((lvt >> 8) & 7) { | |
179 | case APIC_DM_SMI: | |
180 | cpu_interrupt(env, CPU_INTERRUPT_SMI); | |
181 | break; | |
182 | ||
183 | case APIC_DM_NMI: | |
184 | cpu_interrupt(env, CPU_INTERRUPT_NMI); | |
185 | break; | |
186 | ||
187 | case APIC_DM_EXTINT: | |
188 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
189 | break; | |
190 | ||
191 | case APIC_DM_FIXED: | |
192 | trigger_mode = APIC_TRIGGER_EDGE; | |
193 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
194 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
195 | trigger_mode = APIC_TRIGGER_LEVEL; | |
196 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
197 | } | |
198 | } | |
199 | ||
d3e9db93 FB |
200 | #define foreach_apic(apic, deliver_bitmask, code) \ |
201 | {\ | |
202 | int __i, __j, __mask;\ | |
203 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ | |
204 | __mask = deliver_bitmask[__i];\ | |
205 | if (__mask) {\ | |
206 | for(__j = 0; __j < 32; __j++) {\ | |
207 | if (__mask & (1 << __j)) {\ | |
208 | apic = local_apics[__i * 32 + __j];\ | |
209 | if (apic) {\ | |
210 | code;\ | |
211 | }\ | |
212 | }\ | |
213 | }\ | |
214 | }\ | |
215 | }\ | |
216 | } | |
217 | ||
5fafdf24 | 218 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
d3e9db93 | 219 | uint8_t delivery_mode, |
d592d303 FB |
220 | uint8_t vector_num, uint8_t polarity, |
221 | uint8_t trigger_mode) | |
222 | { | |
223 | APICState *apic_iter; | |
224 | ||
225 | switch (delivery_mode) { | |
226 | case APIC_DM_LOWPRI: | |
8dd69b8f | 227 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
228 | { |
229 | int i, d; | |
230 | d = -1; | |
231 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
232 | if (deliver_bitmask[i]) { | |
233 | d = i * 32 + ffs_bit(deliver_bitmask[i]); | |
234 | break; | |
235 | } | |
236 | } | |
237 | if (d >= 0) { | |
238 | apic_iter = local_apics[d]; | |
239 | if (apic_iter) { | |
240 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
241 | } | |
242 | } | |
8dd69b8f | 243 | } |
d3e9db93 | 244 | return; |
8dd69b8f | 245 | |
d592d303 | 246 | case APIC_DM_FIXED: |
d592d303 FB |
247 | break; |
248 | ||
249 | case APIC_DM_SMI: | |
e2eb9d3e AJ |
250 | foreach_apic(apic_iter, deliver_bitmask, |
251 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); | |
252 | return; | |
253 | ||
d592d303 | 254 | case APIC_DM_NMI: |
e2eb9d3e AJ |
255 | foreach_apic(apic_iter, deliver_bitmask, |
256 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); | |
257 | return; | |
d592d303 FB |
258 | |
259 | case APIC_DM_INIT: | |
260 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 261 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 262 | apic_init_ipi(apic_iter) ); |
d592d303 | 263 | return; |
3b46e624 | 264 | |
d592d303 | 265 | case APIC_DM_EXTINT: |
b1fc0348 | 266 | /* handled in I/O APIC code */ |
d592d303 FB |
267 | break; |
268 | ||
269 | default: | |
270 | return; | |
271 | } | |
272 | ||
5fafdf24 | 273 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 274 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 275 | } |
574bbf7b FB |
276 | |
277 | void cpu_set_apic_base(CPUState *env, uint64_t val) | |
278 | { | |
279 | APICState *s = env->apic_state; | |
280 | #ifdef DEBUG_APIC | |
26a76461 | 281 | printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
574bbf7b | 282 | #endif |
5fafdf24 | 283 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
284 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
285 | /* if disabled, cannot be enabled again */ | |
286 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
287 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
288 | env->cpuid_features &= ~CPUID_APIC; | |
289 | s->spurious_vec &= ~APIC_SV_ENABLE; | |
290 | } | |
291 | } | |
292 | ||
293 | uint64_t cpu_get_apic_base(CPUState *env) | |
294 | { | |
295 | APICState *s = env->apic_state; | |
296 | #ifdef DEBUG_APIC | |
26a76461 | 297 | printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase); |
574bbf7b FB |
298 | #endif |
299 | return s->apicbase; | |
300 | } | |
301 | ||
9230e66e FB |
302 | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val) |
303 | { | |
304 | APICState *s = env->apic_state; | |
305 | s->tpr = (val & 0x0f) << 4; | |
d592d303 | 306 | apic_update_irq(s); |
9230e66e FB |
307 | } |
308 | ||
309 | uint8_t cpu_get_apic_tpr(CPUX86State *env) | |
310 | { | |
311 | APICState *s = env->apic_state; | |
312 | return s->tpr >> 4; | |
313 | } | |
314 | ||
d592d303 FB |
315 | /* return -1 if no bit is set */ |
316 | static int get_highest_priority_int(uint32_t *tab) | |
317 | { | |
318 | int i; | |
319 | for(i = 7; i >= 0; i--) { | |
320 | if (tab[i] != 0) { | |
321 | return i * 32 + fls_bit(tab[i]); | |
322 | } | |
323 | } | |
324 | return -1; | |
325 | } | |
326 | ||
574bbf7b FB |
327 | static int apic_get_ppr(APICState *s) |
328 | { | |
329 | int tpr, isrv, ppr; | |
330 | ||
331 | tpr = (s->tpr >> 4); | |
332 | isrv = get_highest_priority_int(s->isr); | |
333 | if (isrv < 0) | |
334 | isrv = 0; | |
335 | isrv >>= 4; | |
336 | if (tpr >= isrv) | |
337 | ppr = s->tpr; | |
338 | else | |
339 | ppr = isrv << 4; | |
340 | return ppr; | |
341 | } | |
342 | ||
d592d303 FB |
343 | static int apic_get_arb_pri(APICState *s) |
344 | { | |
345 | /* XXX: arbitration */ | |
346 | return 0; | |
347 | } | |
348 | ||
574bbf7b FB |
349 | /* signal the CPU if an irq is pending */ |
350 | static void apic_update_irq(APICState *s) | |
351 | { | |
d592d303 FB |
352 | int irrv, ppr; |
353 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
354 | return; | |
574bbf7b FB |
355 | irrv = get_highest_priority_int(s->irr); |
356 | if (irrv < 0) | |
357 | return; | |
d592d303 FB |
358 | ppr = apic_get_ppr(s); |
359 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) | |
574bbf7b FB |
360 | return; |
361 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); | |
362 | } | |
363 | ||
364 | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) | |
365 | { | |
366 | set_bit(s->irr, vector_num); | |
367 | if (trigger_mode) | |
368 | set_bit(s->tmr, vector_num); | |
369 | else | |
370 | reset_bit(s->tmr, vector_num); | |
371 | apic_update_irq(s); | |
372 | } | |
373 | ||
374 | static void apic_eoi(APICState *s) | |
375 | { | |
376 | int isrv; | |
377 | isrv = get_highest_priority_int(s->isr); | |
378 | if (isrv < 0) | |
379 | return; | |
380 | reset_bit(s->isr, isrv); | |
d592d303 FB |
381 | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to |
382 | set the remote IRR bit for level triggered interrupts. */ | |
574bbf7b FB |
383 | apic_update_irq(s); |
384 | } | |
385 | ||
d3e9db93 FB |
386 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
387 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 388 | { |
d592d303 | 389 | APICState *apic_iter; |
d3e9db93 | 390 | int i; |
d592d303 FB |
391 | |
392 | if (dest_mode == 0) { | |
d3e9db93 FB |
393 | if (dest == 0xff) { |
394 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
395 | } else { | |
396 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); | |
397 | set_bit(deliver_bitmask, dest); | |
398 | } | |
d592d303 FB |
399 | } else { |
400 | /* XXX: cluster mode */ | |
d3e9db93 FB |
401 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
402 | for(i = 0; i < MAX_APICS; i++) { | |
403 | apic_iter = local_apics[i]; | |
404 | if (apic_iter) { | |
405 | if (apic_iter->dest_mode == 0xf) { | |
406 | if (dest & apic_iter->log_dest) | |
407 | set_bit(deliver_bitmask, i); | |
408 | } else if (apic_iter->dest_mode == 0x0) { | |
409 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
410 | (dest & apic_iter->log_dest & 0x0f)) { | |
411 | set_bit(deliver_bitmask, i); | |
412 | } | |
413 | } | |
414 | } | |
d592d303 FB |
415 | } |
416 | } | |
d592d303 FB |
417 | } |
418 | ||
419 | ||
420 | static void apic_init_ipi(APICState *s) | |
421 | { | |
422 | int i; | |
423 | ||
d592d303 FB |
424 | s->tpr = 0; |
425 | s->spurious_vec = 0xff; | |
426 | s->log_dest = 0; | |
e0fd8781 | 427 | s->dest_mode = 0xf; |
d592d303 FB |
428 | memset(s->isr, 0, sizeof(s->isr)); |
429 | memset(s->tmr, 0, sizeof(s->tmr)); | |
430 | memset(s->irr, 0, sizeof(s->irr)); | |
b4511723 FB |
431 | for(i = 0; i < APIC_LVT_NB; i++) |
432 | s->lvt[i] = 1 << 16; /* mask LVT */ | |
d592d303 FB |
433 | s->esr = 0; |
434 | memset(s->icr, 0, sizeof(s->icr)); | |
435 | s->divide_conf = 0; | |
436 | s->count_shift = 0; | |
437 | s->initial_count = 0; | |
438 | s->initial_count_load_time = 0; | |
439 | s->next_time = 0; | |
440 | } | |
441 | ||
e0fd8781 FB |
442 | /* send a SIPI message to the CPU to start it */ |
443 | static void apic_startup(APICState *s, int vector_num) | |
444 | { | |
445 | CPUState *env = s->cpu_env; | |
8dd69b8f | 446 | if (!(env->hflags & HF_HALTED_MASK)) |
e0fd8781 FB |
447 | return; |
448 | env->eip = 0; | |
5fafdf24 | 449 | cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, |
e0fd8781 | 450 | 0xffff, 0); |
8dd69b8f | 451 | env->hflags &= ~HF_HALTED_MASK; |
e0fd8781 FB |
452 | } |
453 | ||
d592d303 FB |
454 | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
455 | uint8_t delivery_mode, uint8_t vector_num, | |
456 | uint8_t polarity, uint8_t trigger_mode) | |
457 | { | |
d3e9db93 | 458 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 FB |
459 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
460 | APICState *apic_iter; | |
461 | ||
e0fd8781 | 462 | switch (dest_shorthand) { |
d3e9db93 FB |
463 | case 0: |
464 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
465 | break; | |
466 | case 1: | |
467 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
468 | set_bit(deliver_bitmask, s->id); | |
469 | break; | |
470 | case 2: | |
471 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
472 | break; | |
473 | case 3: | |
474 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
475 | reset_bit(deliver_bitmask, s->id); | |
476 | break; | |
e0fd8781 FB |
477 | } |
478 | ||
d592d303 | 479 | switch (delivery_mode) { |
d592d303 FB |
480 | case APIC_DM_INIT: |
481 | { | |
482 | int trig_mode = (s->icr[0] >> 15) & 1; | |
483 | int level = (s->icr[0] >> 14) & 1; | |
484 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 485 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 486 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
487 | return; |
488 | } | |
489 | } | |
490 | break; | |
491 | ||
492 | case APIC_DM_SIPI: | |
5fafdf24 | 493 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 494 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
495 | return; |
496 | } | |
497 | ||
d592d303 FB |
498 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
499 | trigger_mode); | |
500 | } | |
501 | ||
574bbf7b FB |
502 | int apic_get_interrupt(CPUState *env) |
503 | { | |
504 | APICState *s = env->apic_state; | |
505 | int intno; | |
506 | ||
507 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
508 | IRQs */ | |
509 | if (!s) | |
510 | return -1; | |
511 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
512 | return -1; | |
3b46e624 | 513 | |
574bbf7b FB |
514 | /* XXX: spurious IRQ handling */ |
515 | intno = get_highest_priority_int(s->irr); | |
516 | if (intno < 0) | |
517 | return -1; | |
d592d303 FB |
518 | if (s->tpr && intno <= s->tpr) |
519 | return s->spurious_vec & 0xff; | |
b4511723 | 520 | reset_bit(s->irr, intno); |
574bbf7b FB |
521 | set_bit(s->isr, intno); |
522 | apic_update_irq(s); | |
523 | return intno; | |
524 | } | |
525 | ||
0e21e12b TS |
526 | int apic_accept_pic_intr(CPUState *env) |
527 | { | |
528 | APICState *s = env->apic_state; | |
529 | uint32_t lvt0; | |
530 | ||
531 | if (!s) | |
532 | return -1; | |
533 | ||
534 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
535 | ||
a5b38b51 AJ |
536 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
537 | (lvt0 & APIC_LVT_MASKED) == 0) | |
0e21e12b TS |
538 | return 1; |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
574bbf7b FB |
543 | static uint32_t apic_get_current_count(APICState *s) |
544 | { | |
545 | int64_t d; | |
546 | uint32_t val; | |
5fafdf24 | 547 | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
574bbf7b FB |
548 | s->count_shift; |
549 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
550 | /* periodic */ | |
d592d303 | 551 | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1)); |
574bbf7b FB |
552 | } else { |
553 | if (d >= s->initial_count) | |
554 | val = 0; | |
555 | else | |
556 | val = s->initial_count - d; | |
557 | } | |
558 | return val; | |
559 | } | |
560 | ||
561 | static void apic_timer_update(APICState *s, int64_t current_time) | |
562 | { | |
563 | int64_t next_time, d; | |
3b46e624 | 564 | |
574bbf7b | 565 | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { |
5fafdf24 | 566 | d = (current_time - s->initial_count_load_time) >> |
574bbf7b FB |
567 | s->count_shift; |
568 | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { | |
d592d303 | 569 | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
574bbf7b FB |
570 | } else { |
571 | if (d >= s->initial_count) | |
572 | goto no_timer; | |
d592d303 | 573 | d = (uint64_t)s->initial_count + 1; |
574bbf7b FB |
574 | } |
575 | next_time = s->initial_count_load_time + (d << s->count_shift); | |
576 | qemu_mod_timer(s->timer, next_time); | |
577 | s->next_time = next_time; | |
578 | } else { | |
579 | no_timer: | |
580 | qemu_del_timer(s->timer); | |
581 | } | |
582 | } | |
583 | ||
584 | static void apic_timer(void *opaque) | |
585 | { | |
586 | APICState *s = opaque; | |
587 | ||
a5b38b51 | 588 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
574bbf7b FB |
589 | apic_timer_update(s, s->next_time); |
590 | } | |
591 | ||
592 | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) | |
593 | { | |
594 | return 0; | |
595 | } | |
596 | ||
597 | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) | |
598 | { | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) | |
603 | { | |
604 | } | |
605 | ||
606 | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) | |
607 | { | |
608 | } | |
609 | ||
610 | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) | |
611 | { | |
612 | CPUState *env; | |
613 | APICState *s; | |
614 | uint32_t val; | |
615 | int index; | |
616 | ||
617 | env = cpu_single_env; | |
618 | if (!env) | |
619 | return 0; | |
620 | s = env->apic_state; | |
621 | ||
622 | index = (addr >> 4) & 0xff; | |
623 | switch(index) { | |
624 | case 0x02: /* id */ | |
625 | val = s->id << 24; | |
626 | break; | |
627 | case 0x03: /* version */ | |
628 | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ | |
629 | break; | |
630 | case 0x08: | |
631 | val = s->tpr; | |
632 | break; | |
d592d303 FB |
633 | case 0x09: |
634 | val = apic_get_arb_pri(s); | |
635 | break; | |
574bbf7b FB |
636 | case 0x0a: |
637 | /* ppr */ | |
638 | val = apic_get_ppr(s); | |
639 | break; | |
b237db36 AJ |
640 | case 0x0b: |
641 | val = 0; | |
642 | break; | |
d592d303 FB |
643 | case 0x0d: |
644 | val = s->log_dest << 24; | |
645 | break; | |
646 | case 0x0e: | |
647 | val = s->dest_mode << 28; | |
648 | break; | |
574bbf7b FB |
649 | case 0x0f: |
650 | val = s->spurious_vec; | |
651 | break; | |
652 | case 0x10 ... 0x17: | |
653 | val = s->isr[index & 7]; | |
654 | break; | |
655 | case 0x18 ... 0x1f: | |
656 | val = s->tmr[index & 7]; | |
657 | break; | |
658 | case 0x20 ... 0x27: | |
659 | val = s->irr[index & 7]; | |
660 | break; | |
661 | case 0x28: | |
662 | val = s->esr; | |
663 | break; | |
574bbf7b FB |
664 | case 0x30: |
665 | case 0x31: | |
666 | val = s->icr[index & 1]; | |
667 | break; | |
e0fd8781 FB |
668 | case 0x32 ... 0x37: |
669 | val = s->lvt[index - 0x32]; | |
670 | break; | |
574bbf7b FB |
671 | case 0x38: |
672 | val = s->initial_count; | |
673 | break; | |
674 | case 0x39: | |
675 | val = apic_get_current_count(s); | |
676 | break; | |
677 | case 0x3e: | |
678 | val = s->divide_conf; | |
679 | break; | |
680 | default: | |
681 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
682 | val = 0; | |
683 | break; | |
684 | } | |
685 | #ifdef DEBUG_APIC | |
686 | printf("APIC read: %08x = %08x\n", (uint32_t)addr, val); | |
687 | #endif | |
688 | return val; | |
689 | } | |
690 | ||
691 | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
692 | { | |
693 | CPUState *env; | |
694 | APICState *s; | |
695 | int index; | |
696 | ||
697 | env = cpu_single_env; | |
698 | if (!env) | |
699 | return; | |
700 | s = env->apic_state; | |
701 | ||
702 | #ifdef DEBUG_APIC | |
703 | printf("APIC write: %08x = %08x\n", (uint32_t)addr, val); | |
704 | #endif | |
705 | ||
706 | index = (addr >> 4) & 0xff; | |
707 | switch(index) { | |
708 | case 0x02: | |
709 | s->id = (val >> 24); | |
710 | break; | |
e0fd8781 FB |
711 | case 0x03: |
712 | break; | |
574bbf7b FB |
713 | case 0x08: |
714 | s->tpr = val; | |
d592d303 | 715 | apic_update_irq(s); |
574bbf7b | 716 | break; |
e0fd8781 FB |
717 | case 0x09: |
718 | case 0x0a: | |
719 | break; | |
574bbf7b FB |
720 | case 0x0b: /* EOI */ |
721 | apic_eoi(s); | |
722 | break; | |
d592d303 FB |
723 | case 0x0d: |
724 | s->log_dest = val >> 24; | |
725 | break; | |
726 | case 0x0e: | |
727 | s->dest_mode = val >> 28; | |
728 | break; | |
574bbf7b FB |
729 | case 0x0f: |
730 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 731 | apic_update_irq(s); |
574bbf7b | 732 | break; |
e0fd8781 FB |
733 | case 0x10 ... 0x17: |
734 | case 0x18 ... 0x1f: | |
735 | case 0x20 ... 0x27: | |
736 | case 0x28: | |
737 | break; | |
574bbf7b | 738 | case 0x30: |
d592d303 FB |
739 | s->icr[0] = val; |
740 | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, | |
741 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), | |
742 | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); | |
743 | break; | |
574bbf7b | 744 | case 0x31: |
d592d303 | 745 | s->icr[1] = val; |
574bbf7b FB |
746 | break; |
747 | case 0x32 ... 0x37: | |
748 | { | |
749 | int n = index - 0x32; | |
750 | s->lvt[n] = val; | |
751 | if (n == APIC_LVT_TIMER) | |
752 | apic_timer_update(s, qemu_get_clock(vm_clock)); | |
753 | } | |
754 | break; | |
755 | case 0x38: | |
756 | s->initial_count = val; | |
757 | s->initial_count_load_time = qemu_get_clock(vm_clock); | |
758 | apic_timer_update(s, s->initial_count_load_time); | |
759 | break; | |
e0fd8781 FB |
760 | case 0x39: |
761 | break; | |
574bbf7b FB |
762 | case 0x3e: |
763 | { | |
764 | int v; | |
765 | s->divide_conf = val & 0xb; | |
766 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
767 | s->count_shift = (v + 1) & 7; | |
768 | } | |
769 | break; | |
770 | default: | |
771 | s->esr |= ESR_ILLEGAL_ADDRESS; | |
772 | break; | |
773 | } | |
774 | } | |
775 | ||
d592d303 FB |
776 | static void apic_save(QEMUFile *f, void *opaque) |
777 | { | |
778 | APICState *s = opaque; | |
779 | int i; | |
780 | ||
781 | qemu_put_be32s(f, &s->apicbase); | |
782 | qemu_put_8s(f, &s->id); | |
783 | qemu_put_8s(f, &s->arb_id); | |
784 | qemu_put_8s(f, &s->tpr); | |
785 | qemu_put_be32s(f, &s->spurious_vec); | |
786 | qemu_put_8s(f, &s->log_dest); | |
787 | qemu_put_8s(f, &s->dest_mode); | |
788 | for (i = 0; i < 8; i++) { | |
789 | qemu_put_be32s(f, &s->isr[i]); | |
790 | qemu_put_be32s(f, &s->tmr[i]); | |
791 | qemu_put_be32s(f, &s->irr[i]); | |
792 | } | |
793 | for (i = 0; i < APIC_LVT_NB; i++) { | |
794 | qemu_put_be32s(f, &s->lvt[i]); | |
795 | } | |
796 | qemu_put_be32s(f, &s->esr); | |
797 | qemu_put_be32s(f, &s->icr[0]); | |
798 | qemu_put_be32s(f, &s->icr[1]); | |
799 | qemu_put_be32s(f, &s->divide_conf); | |
bee8d684 | 800 | qemu_put_be32(f, s->count_shift); |
d592d303 | 801 | qemu_put_be32s(f, &s->initial_count); |
bee8d684 TS |
802 | qemu_put_be64(f, s->initial_count_load_time); |
803 | qemu_put_be64(f, s->next_time); | |
e6cf6a8c FB |
804 | |
805 | qemu_put_timer(f, s->timer); | |
d592d303 FB |
806 | } |
807 | ||
808 | static int apic_load(QEMUFile *f, void *opaque, int version_id) | |
809 | { | |
810 | APICState *s = opaque; | |
811 | int i; | |
812 | ||
e6cf6a8c | 813 | if (version_id > 2) |
d592d303 FB |
814 | return -EINVAL; |
815 | ||
816 | /* XXX: what if the base changes? (registered memory regions) */ | |
817 | qemu_get_be32s(f, &s->apicbase); | |
818 | qemu_get_8s(f, &s->id); | |
819 | qemu_get_8s(f, &s->arb_id); | |
820 | qemu_get_8s(f, &s->tpr); | |
821 | qemu_get_be32s(f, &s->spurious_vec); | |
822 | qemu_get_8s(f, &s->log_dest); | |
823 | qemu_get_8s(f, &s->dest_mode); | |
824 | for (i = 0; i < 8; i++) { | |
825 | qemu_get_be32s(f, &s->isr[i]); | |
826 | qemu_get_be32s(f, &s->tmr[i]); | |
827 | qemu_get_be32s(f, &s->irr[i]); | |
828 | } | |
829 | for (i = 0; i < APIC_LVT_NB; i++) { | |
830 | qemu_get_be32s(f, &s->lvt[i]); | |
831 | } | |
832 | qemu_get_be32s(f, &s->esr); | |
833 | qemu_get_be32s(f, &s->icr[0]); | |
834 | qemu_get_be32s(f, &s->icr[1]); | |
835 | qemu_get_be32s(f, &s->divide_conf); | |
bee8d684 | 836 | s->count_shift=qemu_get_be32(f); |
d592d303 | 837 | qemu_get_be32s(f, &s->initial_count); |
bee8d684 TS |
838 | s->initial_count_load_time=qemu_get_be64(f); |
839 | s->next_time=qemu_get_be64(f); | |
e6cf6a8c FB |
840 | |
841 | if (version_id >= 2) | |
842 | qemu_get_timer(f, s->timer); | |
d592d303 FB |
843 | return 0; |
844 | } | |
574bbf7b | 845 | |
d592d303 FB |
846 | static void apic_reset(void *opaque) |
847 | { | |
848 | APICState *s = opaque; | |
849 | apic_init_ipi(s); | |
0e21e12b | 850 | |
a5b38b51 AJ |
851 | if (s->id == 0) { |
852 | /* | |
853 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
854 | * time typically by BIOS, so PIC interrupt can be delivered to the | |
855 | * processor when local APIC is enabled. | |
856 | */ | |
857 | s->lvt[APIC_LVT_LINT0] = 0x700; | |
858 | } | |
d592d303 | 859 | } |
574bbf7b FB |
860 | |
861 | static CPUReadMemoryFunc *apic_mem_read[3] = { | |
862 | apic_mem_readb, | |
863 | apic_mem_readw, | |
864 | apic_mem_readl, | |
865 | }; | |
866 | ||
867 | static CPUWriteMemoryFunc *apic_mem_write[3] = { | |
868 | apic_mem_writeb, | |
869 | apic_mem_writew, | |
870 | apic_mem_writel, | |
871 | }; | |
872 | ||
873 | int apic_init(CPUState *env) | |
874 | { | |
875 | APICState *s; | |
574bbf7b | 876 | |
d3e9db93 FB |
877 | if (last_apic_id >= MAX_APICS) |
878 | return -1; | |
d592d303 | 879 | s = qemu_mallocz(sizeof(APICState)); |
574bbf7b FB |
880 | if (!s) |
881 | return -1; | |
574bbf7b | 882 | env->apic_state = s; |
d592d303 | 883 | s->id = last_apic_id++; |
eae7629b | 884 | env->cpuid_apic_id = s->id; |
574bbf7b | 885 | s->cpu_env = env; |
5fafdf24 | 886 | s->apicbase = 0xfee00000 | |
d592d303 | 887 | (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE; |
574bbf7b | 888 | |
a5b38b51 | 889 | apic_reset(s); |
0e21e12b | 890 | |
d592d303 | 891 | /* XXX: mapping more APICs at the same memory location */ |
574bbf7b FB |
892 | if (apic_io_memory == 0) { |
893 | /* NOTE: the APIC is directly connected to the CPU - it is not | |
894 | on the global memory bus. */ | |
5fafdf24 | 895 | apic_io_memory = cpu_register_io_memory(0, apic_mem_read, |
574bbf7b | 896 | apic_mem_write, NULL); |
d592d303 FB |
897 | cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, |
898 | apic_io_memory); | |
574bbf7b FB |
899 | } |
900 | s->timer = qemu_new_timer(vm_clock, apic_timer, s); | |
d592d303 | 901 | |
be0164f2 | 902 | register_savevm("apic", s->id, 2, apic_save, apic_load, s); |
d592d303 | 903 | qemu_register_reset(apic_reset, s); |
3b46e624 | 904 | |
d3e9db93 | 905 | local_apics[s->id] = s; |
d592d303 FB |
906 | return 0; |
907 | } | |
908 | ||
909 | static void ioapic_service(IOAPICState *s) | |
910 | { | |
b1fc0348 FB |
911 | uint8_t i; |
912 | uint8_t trig_mode; | |
d592d303 | 913 | uint8_t vector; |
b1fc0348 | 914 | uint8_t delivery_mode; |
d592d303 FB |
915 | uint32_t mask; |
916 | uint64_t entry; | |
917 | uint8_t dest; | |
918 | uint8_t dest_mode; | |
b1fc0348 | 919 | uint8_t polarity; |
d3e9db93 | 920 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 | 921 | |
b1fc0348 FB |
922 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
923 | mask = 1 << i; | |
d592d303 | 924 | if (s->irr & mask) { |
b1fc0348 | 925 | entry = s->ioredtbl[i]; |
d592d303 | 926 | if (!(entry & APIC_LVT_MASKED)) { |
b1fc0348 | 927 | trig_mode = ((entry >> 15) & 1); |
d592d303 FB |
928 | dest = entry >> 56; |
929 | dest_mode = (entry >> 11) & 1; | |
b1fc0348 FB |
930 | delivery_mode = (entry >> 8) & 7; |
931 | polarity = (entry >> 13) & 1; | |
932 | if (trig_mode == APIC_TRIGGER_EDGE) | |
933 | s->irr &= ~mask; | |
934 | if (delivery_mode == APIC_DM_EXTINT) | |
935 | vector = pic_read_irq(isa_pic); | |
936 | else | |
937 | vector = entry & 0xff; | |
3b46e624 | 938 | |
d3e9db93 | 939 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
5fafdf24 | 940 | apic_bus_deliver(deliver_bitmask, delivery_mode, |
d3e9db93 | 941 | vector, polarity, trig_mode); |
d592d303 FB |
942 | } |
943 | } | |
944 | } | |
945 | } | |
946 | ||
947 | void ioapic_set_irq(void *opaque, int vector, int level) | |
948 | { | |
949 | IOAPICState *s = opaque; | |
950 | ||
951 | if (vector >= 0 && vector < IOAPIC_NUM_PINS) { | |
952 | uint32_t mask = 1 << vector; | |
953 | uint64_t entry = s->ioredtbl[vector]; | |
954 | ||
955 | if ((entry >> 15) & 1) { | |
956 | /* level triggered */ | |
957 | if (level) { | |
958 | s->irr |= mask; | |
959 | ioapic_service(s); | |
960 | } else { | |
961 | s->irr &= ~mask; | |
962 | } | |
963 | } else { | |
964 | /* edge triggered */ | |
965 | if (level) { | |
966 | s->irr |= mask; | |
967 | ioapic_service(s); | |
968 | } | |
969 | } | |
970 | } | |
971 | } | |
972 | ||
973 | static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) | |
974 | { | |
975 | IOAPICState *s = opaque; | |
976 | int index; | |
977 | uint32_t val = 0; | |
978 | ||
979 | addr &= 0xff; | |
980 | if (addr == 0x00) { | |
981 | val = s->ioregsel; | |
982 | } else if (addr == 0x10) { | |
983 | switch (s->ioregsel) { | |
984 | case 0x00: | |
985 | val = s->id << 24; | |
986 | break; | |
987 | case 0x01: | |
988 | val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ | |
989 | break; | |
990 | case 0x02: | |
991 | val = 0; | |
992 | break; | |
993 | default: | |
994 | index = (s->ioregsel - 0x10) >> 1; | |
995 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
996 | if (s->ioregsel & 1) | |
997 | val = s->ioredtbl[index] >> 32; | |
998 | else | |
999 | val = s->ioredtbl[index] & 0xffffffff; | |
1000 | } | |
1001 | } | |
1002 | #ifdef DEBUG_IOAPIC | |
1003 | printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val); | |
1004 | #endif | |
1005 | } | |
1006 | return val; | |
1007 | } | |
1008 | ||
1009 | static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
1010 | { | |
1011 | IOAPICState *s = opaque; | |
1012 | int index; | |
1013 | ||
1014 | addr &= 0xff; | |
1015 | if (addr == 0x00) { | |
1016 | s->ioregsel = val; | |
1017 | return; | |
1018 | } else if (addr == 0x10) { | |
1019 | #ifdef DEBUG_IOAPIC | |
1020 | printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val); | |
1021 | #endif | |
1022 | switch (s->ioregsel) { | |
1023 | case 0x00: | |
1024 | s->id = (val >> 24) & 0xff; | |
1025 | return; | |
1026 | case 0x01: | |
1027 | case 0x02: | |
1028 | return; | |
1029 | default: | |
1030 | index = (s->ioregsel - 0x10) >> 1; | |
1031 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
1032 | if (s->ioregsel & 1) { | |
1033 | s->ioredtbl[index] &= 0xffffffff; | |
1034 | s->ioredtbl[index] |= (uint64_t)val << 32; | |
1035 | } else { | |
1036 | s->ioredtbl[index] &= ~0xffffffffULL; | |
1037 | s->ioredtbl[index] |= val; | |
1038 | } | |
1039 | ioapic_service(s); | |
1040 | } | |
1041 | } | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | static void ioapic_save(QEMUFile *f, void *opaque) | |
1046 | { | |
1047 | IOAPICState *s = opaque; | |
1048 | int i; | |
1049 | ||
1050 | qemu_put_8s(f, &s->id); | |
1051 | qemu_put_8s(f, &s->ioregsel); | |
1052 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1053 | qemu_put_be64s(f, &s->ioredtbl[i]); | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | static int ioapic_load(QEMUFile *f, void *opaque, int version_id) | |
1058 | { | |
1059 | IOAPICState *s = opaque; | |
1060 | int i; | |
1061 | ||
1062 | if (version_id != 1) | |
1063 | return -EINVAL; | |
1064 | ||
1065 | qemu_get_8s(f, &s->id); | |
1066 | qemu_get_8s(f, &s->ioregsel); | |
1067 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1068 | qemu_get_be64s(f, &s->ioredtbl[i]); | |
1069 | } | |
574bbf7b FB |
1070 | return 0; |
1071 | } | |
d592d303 FB |
1072 | |
1073 | static void ioapic_reset(void *opaque) | |
1074 | { | |
1075 | IOAPICState *s = opaque; | |
1076 | int i; | |
1077 | ||
1078 | memset(s, 0, sizeof(*s)); | |
1079 | for(i = 0; i < IOAPIC_NUM_PINS; i++) | |
1080 | s->ioredtbl[i] = 1 << 16; /* mask LVT */ | |
1081 | } | |
1082 | ||
1083 | static CPUReadMemoryFunc *ioapic_mem_read[3] = { | |
1084 | ioapic_mem_readl, | |
1085 | ioapic_mem_readl, | |
1086 | ioapic_mem_readl, | |
1087 | }; | |
1088 | ||
1089 | static CPUWriteMemoryFunc *ioapic_mem_write[3] = { | |
1090 | ioapic_mem_writel, | |
1091 | ioapic_mem_writel, | |
1092 | ioapic_mem_writel, | |
1093 | }; | |
1094 | ||
1095 | IOAPICState *ioapic_init(void) | |
1096 | { | |
1097 | IOAPICState *s; | |
1098 | int io_memory; | |
1099 | ||
b1fc0348 | 1100 | s = qemu_mallocz(sizeof(IOAPICState)); |
d592d303 FB |
1101 | if (!s) |
1102 | return NULL; | |
d592d303 FB |
1103 | ioapic_reset(s); |
1104 | s->id = last_apic_id++; | |
1105 | ||
5fafdf24 | 1106 | io_memory = cpu_register_io_memory(0, ioapic_mem_read, |
d592d303 FB |
1107 | ioapic_mem_write, s); |
1108 | cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); | |
1109 | ||
1110 | register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s); | |
1111 | qemu_register_reset(ioapic_reset, s); | |
3b46e624 | 1112 | |
d592d303 FB |
1113 | return s; |
1114 | } |