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574bbf7b
FB
1/*
2 * APIC support
5fafdf24 3 *
574bbf7b
FB
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
574bbf7b 18 */
87ecb68b 19#include "hw.h"
aa28b9bf 20#include "apic.h"
87ecb68b 21#include "qemu-timer.h"
bb7e7293 22#include "host-utils.h"
8546b099 23#include "sysbus.h"
d8023f31 24#include "trace.h"
574bbf7b
FB
25
26/* APIC Local Vector Table */
27#define APIC_LVT_TIMER 0
28#define APIC_LVT_THERMAL 1
29#define APIC_LVT_PERFORM 2
30#define APIC_LVT_LINT0 3
31#define APIC_LVT_LINT1 4
32#define APIC_LVT_ERROR 5
33#define APIC_LVT_NB 6
34
35/* APIC delivery modes */
36#define APIC_DM_FIXED 0
37#define APIC_DM_LOWPRI 1
38#define APIC_DM_SMI 2
39#define APIC_DM_NMI 4
40#define APIC_DM_INIT 5
41#define APIC_DM_SIPI 6
42#define APIC_DM_EXTINT 7
43
d592d303
FB
44/* APIC destination mode */
45#define APIC_DESTMODE_FLAT 0xf
46#define APIC_DESTMODE_CLUSTER 1
47
574bbf7b
FB
48#define APIC_TRIGGER_EDGE 0
49#define APIC_TRIGGER_LEVEL 1
50
51#define APIC_LVT_TIMER_PERIODIC (1<<17)
52#define APIC_LVT_MASKED (1<<16)
53#define APIC_LVT_LEVEL_TRIGGER (1<<15)
54#define APIC_LVT_REMOTE_IRR (1<<14)
55#define APIC_INPUT_POLARITY (1<<13)
56#define APIC_SEND_PENDING (1<<12)
57
58#define ESR_ILLEGAL_ADDRESS (1 << 7)
59
60#define APIC_SV_ENABLE (1 << 8)
61
d3e9db93
FB
62#define MAX_APICS 255
63#define MAX_APIC_WORDS 8
64
54c96da7
MT
65/* Intel APIC constants: from include/asm/msidef.h */
66#define MSI_DATA_VECTOR_SHIFT 0
67#define MSI_DATA_VECTOR_MASK 0x000000ff
68#define MSI_DATA_DELIVERY_MODE_SHIFT 8
69#define MSI_DATA_TRIGGER_SHIFT 15
70#define MSI_DATA_LEVEL_SHIFT 14
71#define MSI_ADDR_DEST_MODE_SHIFT 2
72#define MSI_ADDR_DEST_ID_SHIFT 12
73#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
74
54c96da7
MT
75#define MSI_ADDR_SIZE 0x100000
76
92a16d7a
BS
77typedef struct APICState APICState;
78
cf6d64bf 79struct APICState {
8546b099
BS
80 SysBusDevice busdev;
81 void *cpu_env;
574bbf7b
FB
82 uint32_t apicbase;
83 uint8_t id;
d592d303 84 uint8_t arb_id;
574bbf7b
FB
85 uint8_t tpr;
86 uint32_t spurious_vec;
d592d303
FB
87 uint8_t log_dest;
88 uint8_t dest_mode;
574bbf7b
FB
89 uint32_t isr[8]; /* in service register */
90 uint32_t tmr[8]; /* trigger mode register */
91 uint32_t irr[8]; /* interrupt request register */
92 uint32_t lvt[APIC_LVT_NB];
93 uint32_t esr; /* error register */
94 uint32_t icr[2];
95
96 uint32_t divide_conf;
97 int count_shift;
98 uint32_t initial_count;
99 int64_t initial_count_load_time, next_time;
678e12cc 100 uint32_t idx;
574bbf7b 101 QEMUTimer *timer;
b09ea7d5
GN
102 int sipi_vector;
103 int wait_for_sipi;
cf6d64bf 104};
574bbf7b 105
d3e9db93 106static APICState *local_apics[MAX_APICS + 1];
73822ec8
AL
107static int apic_irq_delivered;
108
d592d303
FB
109static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
110static void apic_update_irq(APICState *s);
610626af
AL
111static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
112 uint8_t dest, uint8_t dest_mode);
d592d303 113
3b63c04e
AJ
114/* Find first bit starting from msb */
115static int fls_bit(uint32_t value)
116{
117 return 31 - clz32(value);
118}
119
e95f5491 120/* Find first bit starting from lsb */
d3e9db93
FB
121static int ffs_bit(uint32_t value)
122{
bb7e7293 123 return ctz32(value);
d3e9db93
FB
124}
125
126static inline void set_bit(uint32_t *tab, int index)
127{
128 int i, mask;
129 i = index >> 5;
130 mask = 1 << (index & 0x1f);
131 tab[i] |= mask;
132}
133
134static inline void reset_bit(uint32_t *tab, int index)
135{
136 int i, mask;
137 i = index >> 5;
138 mask = 1 << (index & 0x1f);
139 tab[i] &= ~mask;
140}
141
73822ec8
AL
142static inline int get_bit(uint32_t *tab, int index)
143{
144 int i, mask;
145 i = index >> 5;
146 mask = 1 << (index & 0x1f);
147 return !!(tab[i] & mask);
148}
149
cf6d64bf 150static void apic_local_deliver(APICState *s, int vector)
a5b38b51 151{
a5b38b51
AJ
152 uint32_t lvt = s->lvt[vector];
153 int trigger_mode;
154
d8023f31
BS
155 trace_apic_local_deliver(vector, (lvt >> 8) & 7);
156
a5b38b51
AJ
157 if (lvt & APIC_LVT_MASKED)
158 return;
159
160 switch ((lvt >> 8) & 7) {
161 case APIC_DM_SMI:
cf6d64bf 162 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
a5b38b51
AJ
163 break;
164
165 case APIC_DM_NMI:
cf6d64bf 166 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
a5b38b51
AJ
167 break;
168
169 case APIC_DM_EXTINT:
cf6d64bf 170 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
a5b38b51
AJ
171 break;
172
173 case APIC_DM_FIXED:
174 trigger_mode = APIC_TRIGGER_EDGE;
175 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
176 (lvt & APIC_LVT_LEVEL_TRIGGER))
177 trigger_mode = APIC_TRIGGER_LEVEL;
178 apic_set_irq(s, lvt & 0xff, trigger_mode);
179 }
180}
181
92a16d7a 182void apic_deliver_pic_intr(DeviceState *d, int level)
1a7de94a 183{
92a16d7a
BS
184 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
185
cf6d64bf
BS
186 if (level) {
187 apic_local_deliver(s, APIC_LVT_LINT0);
188 } else {
1a7de94a
AJ
189 uint32_t lvt = s->lvt[APIC_LVT_LINT0];
190
191 switch ((lvt >> 8) & 7) {
192 case APIC_DM_FIXED:
193 if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
194 break;
195 reset_bit(s->irr, lvt & 0xff);
196 /* fall through */
197 case APIC_DM_EXTINT:
cf6d64bf 198 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
1a7de94a
AJ
199 break;
200 }
201 }
202}
203
d3e9db93
FB
204#define foreach_apic(apic, deliver_bitmask, code) \
205{\
206 int __i, __j, __mask;\
207 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
208 __mask = deliver_bitmask[__i];\
209 if (__mask) {\
210 for(__j = 0; __j < 32; __j++) {\
211 if (__mask & (1 << __j)) {\
212 apic = local_apics[__i * 32 + __j];\
213 if (apic) {\
214 code;\
215 }\
216 }\
217 }\
218 }\
219 }\
220}
221
5fafdf24 222static void apic_bus_deliver(const uint32_t *deliver_bitmask,
d3e9db93 223 uint8_t delivery_mode,
d592d303
FB
224 uint8_t vector_num, uint8_t polarity,
225 uint8_t trigger_mode)
226{
227 APICState *apic_iter;
228
229 switch (delivery_mode) {
230 case APIC_DM_LOWPRI:
8dd69b8f 231 /* XXX: search for focus processor, arbitration */
d3e9db93
FB
232 {
233 int i, d;
234 d = -1;
235 for(i = 0; i < MAX_APIC_WORDS; i++) {
236 if (deliver_bitmask[i]) {
237 d = i * 32 + ffs_bit(deliver_bitmask[i]);
238 break;
239 }
240 }
241 if (d >= 0) {
242 apic_iter = local_apics[d];
243 if (apic_iter) {
244 apic_set_irq(apic_iter, vector_num, trigger_mode);
245 }
246 }
8dd69b8f 247 }
d3e9db93 248 return;
8dd69b8f 249
d592d303 250 case APIC_DM_FIXED:
d592d303
FB
251 break;
252
253 case APIC_DM_SMI:
e2eb9d3e
AJ
254 foreach_apic(apic_iter, deliver_bitmask,
255 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
256 return;
257
d592d303 258 case APIC_DM_NMI:
e2eb9d3e
AJ
259 foreach_apic(apic_iter, deliver_bitmask,
260 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
261 return;
d592d303
FB
262
263 case APIC_DM_INIT:
264 /* normal INIT IPI sent to processors */
5fafdf24 265 foreach_apic(apic_iter, deliver_bitmask,
b09ea7d5 266 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
d592d303 267 return;
3b46e624 268
d592d303 269 case APIC_DM_EXTINT:
b1fc0348 270 /* handled in I/O APIC code */
d592d303
FB
271 break;
272
273 default:
274 return;
275 }
276
5fafdf24 277 foreach_apic(apic_iter, deliver_bitmask,
d3e9db93 278 apic_set_irq(apic_iter, vector_num, trigger_mode) );
d592d303 279}
574bbf7b 280
610626af
AL
281void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
282 uint8_t delivery_mode, uint8_t vector_num,
283 uint8_t polarity, uint8_t trigger_mode)
284{
285 uint32_t deliver_bitmask[MAX_APIC_WORDS];
286
d8023f31
BS
287 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
288 polarity, trigger_mode);
289
610626af
AL
290 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
291 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
292 trigger_mode);
293}
294
92a16d7a 295void cpu_set_apic_base(DeviceState *d, uint64_t val)
574bbf7b 296{
92a16d7a
BS
297 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
298
d8023f31
BS
299 trace_cpu_set_apic_base(val);
300
2c7c13d4
AJ
301 if (!s)
302 return;
5fafdf24 303 s->apicbase = (val & 0xfffff000) |
574bbf7b
FB
304 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
305 /* if disabled, cannot be enabled again */
306 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
307 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
0e26b7b8 308 cpu_clear_apic_feature(s->cpu_env);
574bbf7b
FB
309 s->spurious_vec &= ~APIC_SV_ENABLE;
310 }
311}
312
92a16d7a 313uint64_t cpu_get_apic_base(DeviceState *d)
574bbf7b 314{
92a16d7a
BS
315 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
316
d8023f31
BS
317 trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
318
2c7c13d4 319 return s ? s->apicbase : 0;
574bbf7b
FB
320}
321
92a16d7a 322void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
9230e66e 323{
92a16d7a
BS
324 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
325
2c7c13d4
AJ
326 if (!s)
327 return;
9230e66e 328 s->tpr = (val & 0x0f) << 4;
d592d303 329 apic_update_irq(s);
9230e66e
FB
330}
331
92a16d7a 332uint8_t cpu_get_apic_tpr(DeviceState *d)
9230e66e 333{
92a16d7a
BS
334 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
335
2c7c13d4 336 return s ? s->tpr >> 4 : 0;
9230e66e
FB
337}
338
d592d303
FB
339/* return -1 if no bit is set */
340static int get_highest_priority_int(uint32_t *tab)
341{
342 int i;
343 for(i = 7; i >= 0; i--) {
344 if (tab[i] != 0) {
3b63c04e 345 return i * 32 + fls_bit(tab[i]);
d592d303
FB
346 }
347 }
348 return -1;
349}
350
574bbf7b
FB
351static int apic_get_ppr(APICState *s)
352{
353 int tpr, isrv, ppr;
354
355 tpr = (s->tpr >> 4);
356 isrv = get_highest_priority_int(s->isr);
357 if (isrv < 0)
358 isrv = 0;
359 isrv >>= 4;
360 if (tpr >= isrv)
361 ppr = s->tpr;
362 else
363 ppr = isrv << 4;
364 return ppr;
365}
366
d592d303
FB
367static int apic_get_arb_pri(APICState *s)
368{
369 /* XXX: arbitration */
370 return 0;
371}
372
574bbf7b
FB
373/* signal the CPU if an irq is pending */
374static void apic_update_irq(APICState *s)
375{
d592d303
FB
376 int irrv, ppr;
377 if (!(s->spurious_vec & APIC_SV_ENABLE))
378 return;
574bbf7b
FB
379 irrv = get_highest_priority_int(s->irr);
380 if (irrv < 0)
381 return;
d592d303
FB
382 ppr = apic_get_ppr(s);
383 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
574bbf7b
FB
384 return;
385 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
386}
387
73822ec8
AL
388void apic_reset_irq_delivered(void)
389{
d8023f31
BS
390 trace_apic_reset_irq_delivered(apic_irq_delivered);
391
73822ec8
AL
392 apic_irq_delivered = 0;
393}
394
395int apic_get_irq_delivered(void)
396{
d8023f31
BS
397 trace_apic_get_irq_delivered(apic_irq_delivered);
398
73822ec8
AL
399 return apic_irq_delivered;
400}
401
574bbf7b
FB
402static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
403{
73822ec8 404 apic_irq_delivered += !get_bit(s->irr, vector_num);
d8023f31
BS
405
406 trace_apic_set_irq(apic_irq_delivered);
73822ec8 407
574bbf7b
FB
408 set_bit(s->irr, vector_num);
409 if (trigger_mode)
410 set_bit(s->tmr, vector_num);
411 else
412 reset_bit(s->tmr, vector_num);
413 apic_update_irq(s);
414}
415
416static void apic_eoi(APICState *s)
417{
418 int isrv;
419 isrv = get_highest_priority_int(s->isr);
420 if (isrv < 0)
421 return;
422 reset_bit(s->isr, isrv);
d592d303
FB
423 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
424 set the remote IRR bit for level triggered interrupts. */
574bbf7b
FB
425 apic_update_irq(s);
426}
427
678e12cc
GN
428static int apic_find_dest(uint8_t dest)
429{
430 APICState *apic = local_apics[dest];
431 int i;
432
433 if (apic && apic->id == dest)
434 return dest; /* shortcut in case apic->id == apic->idx */
435
436 for (i = 0; i < MAX_APICS; i++) {
437 apic = local_apics[i];
438 if (apic && apic->id == dest)
439 return i;
b538e53e
AW
440 if (!apic)
441 break;
678e12cc
GN
442 }
443
444 return -1;
445}
446
d3e9db93
FB
447static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
448 uint8_t dest, uint8_t dest_mode)
d592d303 449{
d592d303 450 APICState *apic_iter;
d3e9db93 451 int i;
d592d303
FB
452
453 if (dest_mode == 0) {
d3e9db93
FB
454 if (dest == 0xff) {
455 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
456 } else {
678e12cc 457 int idx = apic_find_dest(dest);
d3e9db93 458 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
678e12cc
GN
459 if (idx >= 0)
460 set_bit(deliver_bitmask, idx);
d3e9db93 461 }
d592d303
FB
462 } else {
463 /* XXX: cluster mode */
d3e9db93
FB
464 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
465 for(i = 0; i < MAX_APICS; i++) {
466 apic_iter = local_apics[i];
467 if (apic_iter) {
468 if (apic_iter->dest_mode == 0xf) {
469 if (dest & apic_iter->log_dest)
470 set_bit(deliver_bitmask, i);
471 } else if (apic_iter->dest_mode == 0x0) {
472 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
473 (dest & apic_iter->log_dest & 0x0f)) {
474 set_bit(deliver_bitmask, i);
475 }
476 }
b538e53e
AW
477 } else {
478 break;
d3e9db93 479 }
d592d303
FB
480 }
481 }
d592d303
FB
482}
483
92a16d7a 484void apic_init_reset(DeviceState *d)
d592d303 485{
92a16d7a 486 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
d592d303
FB
487 int i;
488
b09ea7d5
GN
489 if (!s)
490 return;
491
d592d303
FB
492 s->tpr = 0;
493 s->spurious_vec = 0xff;
494 s->log_dest = 0;
e0fd8781 495 s->dest_mode = 0xf;
d592d303
FB
496 memset(s->isr, 0, sizeof(s->isr));
497 memset(s->tmr, 0, sizeof(s->tmr));
498 memset(s->irr, 0, sizeof(s->irr));
b4511723
FB
499 for(i = 0; i < APIC_LVT_NB; i++)
500 s->lvt[i] = 1 << 16; /* mask LVT */
d592d303
FB
501 s->esr = 0;
502 memset(s->icr, 0, sizeof(s->icr));
503 s->divide_conf = 0;
504 s->count_shift = 0;
505 s->initial_count = 0;
506 s->initial_count_load_time = 0;
507 s->next_time = 0;
b09ea7d5 508 s->wait_for_sipi = 1;
d592d303
FB
509}
510
e0fd8781
FB
511static void apic_startup(APICState *s, int vector_num)
512{
b09ea7d5
GN
513 s->sipi_vector = vector_num;
514 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
515}
516
92a16d7a 517void apic_sipi(DeviceState *d)
b09ea7d5 518{
92a16d7a
BS
519 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
520
4a942cea 521 cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
b09ea7d5
GN
522
523 if (!s->wait_for_sipi)
e0fd8781 524 return;
0e26b7b8 525 cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
b09ea7d5 526 s->wait_for_sipi = 0;
e0fd8781
FB
527}
528
92a16d7a 529static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
d592d303
FB
530 uint8_t delivery_mode, uint8_t vector_num,
531 uint8_t polarity, uint8_t trigger_mode)
532{
92a16d7a 533 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
d3e9db93 534 uint32_t deliver_bitmask[MAX_APIC_WORDS];
d592d303
FB
535 int dest_shorthand = (s->icr[0] >> 18) & 3;
536 APICState *apic_iter;
537
e0fd8781 538 switch (dest_shorthand) {
d3e9db93
FB
539 case 0:
540 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
541 break;
542 case 1:
543 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
678e12cc 544 set_bit(deliver_bitmask, s->idx);
d3e9db93
FB
545 break;
546 case 2:
547 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
548 break;
549 case 3:
550 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
678e12cc 551 reset_bit(deliver_bitmask, s->idx);
d3e9db93 552 break;
e0fd8781
FB
553 }
554
d592d303 555 switch (delivery_mode) {
d592d303
FB
556 case APIC_DM_INIT:
557 {
558 int trig_mode = (s->icr[0] >> 15) & 1;
559 int level = (s->icr[0] >> 14) & 1;
560 if (level == 0 && trig_mode == 1) {
5fafdf24 561 foreach_apic(apic_iter, deliver_bitmask,
d3e9db93 562 apic_iter->arb_id = apic_iter->id );
d592d303
FB
563 return;
564 }
565 }
566 break;
567
568 case APIC_DM_SIPI:
5fafdf24 569 foreach_apic(apic_iter, deliver_bitmask,
d3e9db93 570 apic_startup(apic_iter, vector_num) );
d592d303
FB
571 return;
572 }
573
d592d303
FB
574 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
575 trigger_mode);
576}
577
92a16d7a 578int apic_get_interrupt(DeviceState *d)
574bbf7b 579{
92a16d7a 580 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
574bbf7b
FB
581 int intno;
582
583 /* if the APIC is installed or enabled, we let the 8259 handle the
584 IRQs */
585 if (!s)
586 return -1;
587 if (!(s->spurious_vec & APIC_SV_ENABLE))
588 return -1;
3b46e624 589
574bbf7b
FB
590 /* XXX: spurious IRQ handling */
591 intno = get_highest_priority_int(s->irr);
592 if (intno < 0)
593 return -1;
d592d303
FB
594 if (s->tpr && intno <= s->tpr)
595 return s->spurious_vec & 0xff;
b4511723 596 reset_bit(s->irr, intno);
574bbf7b
FB
597 set_bit(s->isr, intno);
598 apic_update_irq(s);
599 return intno;
600}
601
92a16d7a 602int apic_accept_pic_intr(DeviceState *d)
0e21e12b 603{
92a16d7a 604 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
0e21e12b
TS
605 uint32_t lvt0;
606
607 if (!s)
608 return -1;
609
610 lvt0 = s->lvt[APIC_LVT_LINT0];
611
a5b38b51
AJ
612 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
613 (lvt0 & APIC_LVT_MASKED) == 0)
0e21e12b
TS
614 return 1;
615
616 return 0;
617}
618
574bbf7b
FB
619static uint32_t apic_get_current_count(APICState *s)
620{
621 int64_t d;
622 uint32_t val;
5fafdf24 623 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
574bbf7b
FB
624 s->count_shift;
625 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
626 /* periodic */
d592d303 627 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
574bbf7b
FB
628 } else {
629 if (d >= s->initial_count)
630 val = 0;
631 else
632 val = s->initial_count - d;
633 }
634 return val;
635}
636
637static void apic_timer_update(APICState *s, int64_t current_time)
638{
639 int64_t next_time, d;
3b46e624 640
574bbf7b 641 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
5fafdf24 642 d = (current_time - s->initial_count_load_time) >>
574bbf7b
FB
643 s->count_shift;
644 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
681f8c29
AL
645 if (!s->initial_count)
646 goto no_timer;
d592d303 647 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
574bbf7b
FB
648 } else {
649 if (d >= s->initial_count)
650 goto no_timer;
d592d303 651 d = (uint64_t)s->initial_count + 1;
574bbf7b
FB
652 }
653 next_time = s->initial_count_load_time + (d << s->count_shift);
654 qemu_mod_timer(s->timer, next_time);
655 s->next_time = next_time;
656 } else {
657 no_timer:
658 qemu_del_timer(s->timer);
659 }
660}
661
662static void apic_timer(void *opaque)
663{
664 APICState *s = opaque;
665
cf6d64bf 666 apic_local_deliver(s, APIC_LVT_TIMER);
574bbf7b
FB
667 apic_timer_update(s, s->next_time);
668}
669
c227f099 670static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
574bbf7b
FB
671{
672 return 0;
673}
674
c227f099 675static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
574bbf7b
FB
676{
677 return 0;
678}
679
c227f099 680static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
574bbf7b
FB
681{
682}
683
c227f099 684static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
574bbf7b
FB
685{
686}
687
c227f099 688static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
574bbf7b 689{
92a16d7a 690 DeviceState *d;
574bbf7b
FB
691 APICState *s;
692 uint32_t val;
693 int index;
694
92a16d7a
BS
695 d = cpu_get_current_apic();
696 if (!d) {
574bbf7b 697 return 0;
0e26b7b8 698 }
92a16d7a 699 s = DO_UPCAST(APICState, busdev.qdev, d);
574bbf7b
FB
700
701 index = (addr >> 4) & 0xff;
702 switch(index) {
703 case 0x02: /* id */
704 val = s->id << 24;
705 break;
706 case 0x03: /* version */
707 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
708 break;
709 case 0x08:
710 val = s->tpr;
711 break;
d592d303
FB
712 case 0x09:
713 val = apic_get_arb_pri(s);
714 break;
574bbf7b
FB
715 case 0x0a:
716 /* ppr */
717 val = apic_get_ppr(s);
718 break;
b237db36
AJ
719 case 0x0b:
720 val = 0;
721 break;
d592d303
FB
722 case 0x0d:
723 val = s->log_dest << 24;
724 break;
725 case 0x0e:
726 val = s->dest_mode << 28;
727 break;
574bbf7b
FB
728 case 0x0f:
729 val = s->spurious_vec;
730 break;
731 case 0x10 ... 0x17:
732 val = s->isr[index & 7];
733 break;
734 case 0x18 ... 0x1f:
735 val = s->tmr[index & 7];
736 break;
737 case 0x20 ... 0x27:
738 val = s->irr[index & 7];
739 break;
740 case 0x28:
741 val = s->esr;
742 break;
574bbf7b
FB
743 case 0x30:
744 case 0x31:
745 val = s->icr[index & 1];
746 break;
e0fd8781
FB
747 case 0x32 ... 0x37:
748 val = s->lvt[index - 0x32];
749 break;
574bbf7b
FB
750 case 0x38:
751 val = s->initial_count;
752 break;
753 case 0x39:
754 val = apic_get_current_count(s);
755 break;
756 case 0x3e:
757 val = s->divide_conf;
758 break;
759 default:
760 s->esr |= ESR_ILLEGAL_ADDRESS;
761 val = 0;
762 break;
763 }
d8023f31 764 trace_apic_mem_readl(addr, val);
574bbf7b
FB
765 return val;
766}
767
c227f099 768static void apic_send_msi(target_phys_addr_t addr, uint32 data)
54c96da7
MT
769{
770 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
771 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
772 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
773 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
774 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
775 /* XXX: Ignore redirection hint. */
776 apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
777}
778
c227f099 779static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
574bbf7b 780{
92a16d7a 781 DeviceState *d;
574bbf7b 782 APICState *s;
54c96da7
MT
783 int index = (addr >> 4) & 0xff;
784 if (addr > 0xfff || !index) {
785 /* MSI and MMIO APIC are at the same memory location,
786 * but actually not on the global bus: MSI is on PCI bus
787 * APIC is connected directly to the CPU.
788 * Mapping them on the global bus happens to work because
789 * MSI registers are reserved in APIC MMIO and vice versa. */
790 apic_send_msi(addr, val);
791 return;
792 }
574bbf7b 793
92a16d7a
BS
794 d = cpu_get_current_apic();
795 if (!d) {
574bbf7b 796 return;
0e26b7b8 797 }
92a16d7a 798 s = DO_UPCAST(APICState, busdev.qdev, d);
574bbf7b 799
d8023f31 800 trace_apic_mem_writel(addr, val);
574bbf7b 801
574bbf7b
FB
802 switch(index) {
803 case 0x02:
804 s->id = (val >> 24);
805 break;
e0fd8781
FB
806 case 0x03:
807 break;
574bbf7b
FB
808 case 0x08:
809 s->tpr = val;
d592d303 810 apic_update_irq(s);
574bbf7b 811 break;
e0fd8781
FB
812 case 0x09:
813 case 0x0a:
814 break;
574bbf7b
FB
815 case 0x0b: /* EOI */
816 apic_eoi(s);
817 break;
d592d303
FB
818 case 0x0d:
819 s->log_dest = val >> 24;
820 break;
821 case 0x0e:
822 s->dest_mode = val >> 28;
823 break;
574bbf7b
FB
824 case 0x0f:
825 s->spurious_vec = val & 0x1ff;
d592d303 826 apic_update_irq(s);
574bbf7b 827 break;
e0fd8781
FB
828 case 0x10 ... 0x17:
829 case 0x18 ... 0x1f:
830 case 0x20 ... 0x27:
831 case 0x28:
832 break;
574bbf7b 833 case 0x30:
d592d303 834 s->icr[0] = val;
92a16d7a 835 apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
d592d303
FB
836 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
837 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
838 break;
574bbf7b 839 case 0x31:
d592d303 840 s->icr[1] = val;
574bbf7b
FB
841 break;
842 case 0x32 ... 0x37:
843 {
844 int n = index - 0x32;
845 s->lvt[n] = val;
846 if (n == APIC_LVT_TIMER)
847 apic_timer_update(s, qemu_get_clock(vm_clock));
848 }
849 break;
850 case 0x38:
851 s->initial_count = val;
852 s->initial_count_load_time = qemu_get_clock(vm_clock);
853 apic_timer_update(s, s->initial_count_load_time);
854 break;
e0fd8781
FB
855 case 0x39:
856 break;
574bbf7b
FB
857 case 0x3e:
858 {
859 int v;
860 s->divide_conf = val & 0xb;
861 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
862 s->count_shift = (v + 1) & 7;
863 }
864 break;
865 default:
866 s->esr |= ESR_ILLEGAL_ADDRESS;
867 break;
868 }
869}
870
695dcf71
JQ
871/* This function is only used for old state version 1 and 2 */
872static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
d592d303
FB
873{
874 APICState *s = opaque;
875 int i;
876
e6cf6a8c 877 if (version_id > 2)
d592d303
FB
878 return -EINVAL;
879
880 /* XXX: what if the base changes? (registered memory regions) */
881 qemu_get_be32s(f, &s->apicbase);
882 qemu_get_8s(f, &s->id);
883 qemu_get_8s(f, &s->arb_id);
884 qemu_get_8s(f, &s->tpr);
885 qemu_get_be32s(f, &s->spurious_vec);
886 qemu_get_8s(f, &s->log_dest);
887 qemu_get_8s(f, &s->dest_mode);
888 for (i = 0; i < 8; i++) {
889 qemu_get_be32s(f, &s->isr[i]);
890 qemu_get_be32s(f, &s->tmr[i]);
891 qemu_get_be32s(f, &s->irr[i]);
892 }
893 for (i = 0; i < APIC_LVT_NB; i++) {
894 qemu_get_be32s(f, &s->lvt[i]);
895 }
896 qemu_get_be32s(f, &s->esr);
897 qemu_get_be32s(f, &s->icr[0]);
898 qemu_get_be32s(f, &s->icr[1]);
899 qemu_get_be32s(f, &s->divide_conf);
bee8d684 900 s->count_shift=qemu_get_be32(f);
d592d303 901 qemu_get_be32s(f, &s->initial_count);
bee8d684
TS
902 s->initial_count_load_time=qemu_get_be64(f);
903 s->next_time=qemu_get_be64(f);
e6cf6a8c
FB
904
905 if (version_id >= 2)
906 qemu_get_timer(f, s->timer);
d592d303
FB
907 return 0;
908}
574bbf7b 909
695dcf71
JQ
910static const VMStateDescription vmstate_apic = {
911 .name = "apic",
912 .version_id = 3,
913 .minimum_version_id = 3,
914 .minimum_version_id_old = 1,
915 .load_state_old = apic_load_old,
916 .fields = (VMStateField []) {
917 VMSTATE_UINT32(apicbase, APICState),
918 VMSTATE_UINT8(id, APICState),
919 VMSTATE_UINT8(arb_id, APICState),
920 VMSTATE_UINT8(tpr, APICState),
921 VMSTATE_UINT32(spurious_vec, APICState),
922 VMSTATE_UINT8(log_dest, APICState),
923 VMSTATE_UINT8(dest_mode, APICState),
924 VMSTATE_UINT32_ARRAY(isr, APICState, 8),
925 VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
926 VMSTATE_UINT32_ARRAY(irr, APICState, 8),
927 VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
928 VMSTATE_UINT32(esr, APICState),
929 VMSTATE_UINT32_ARRAY(icr, APICState, 2),
930 VMSTATE_UINT32(divide_conf, APICState),
931 VMSTATE_INT32(count_shift, APICState),
932 VMSTATE_UINT32(initial_count, APICState),
933 VMSTATE_INT64(initial_count_load_time, APICState),
934 VMSTATE_INT64(next_time, APICState),
935 VMSTATE_TIMER(timer, APICState),
936 VMSTATE_END_OF_LIST()
937 }
938};
939
8546b099 940static void apic_reset(DeviceState *d)
d592d303 941{
8546b099 942 APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
4c0960c0 943 int bsp;
fec5fa02 944
4c0960c0 945 bsp = cpu_is_bsp(s->cpu_env);
fec5fa02 946 s->apicbase = 0xfee00000 |
678e12cc 947 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
fec5fa02 948
92a16d7a 949 apic_init_reset(d);
0e21e12b 950
678e12cc 951 if (bsp) {
a5b38b51
AJ
952 /*
953 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
954 * time typically by BIOS, so PIC interrupt can be delivered to the
955 * processor when local APIC is enabled.
956 */
957 s->lvt[APIC_LVT_LINT0] = 0x700;
958 }
d592d303 959}
574bbf7b 960
d60efc6b 961static CPUReadMemoryFunc * const apic_mem_read[3] = {
574bbf7b
FB
962 apic_mem_readb,
963 apic_mem_readw,
964 apic_mem_readl,
965};
966
d60efc6b 967static CPUWriteMemoryFunc * const apic_mem_write[3] = {
574bbf7b
FB
968 apic_mem_writeb,
969 apic_mem_writew,
970 apic_mem_writel,
971};
972
8546b099
BS
973static int apic_init1(SysBusDevice *dev)
974{
975 APICState *s = FROM_SYSBUS(APICState, dev);
976 int apic_io_memory;
977 static int last_apic_idx;
978
979 if (last_apic_idx >= MAX_APICS) {
980 return -1;
981 }
982 apic_io_memory = cpu_register_io_memory(apic_mem_read,
2507c12a
AG
983 apic_mem_write, NULL,
984 DEVICE_NATIVE_ENDIAN);
8546b099
BS
985 sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
986
987 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
988 s->idx = last_apic_idx++;
989 local_apics[s->idx] = s;
990 return 0;
991}
992
993static SysBusDeviceInfo apic_info = {
994 .init = apic_init1,
995 .qdev.name = "apic",
996 .qdev.size = sizeof(APICState),
997 .qdev.vmsd = &vmstate_apic,
998 .qdev.reset = apic_reset,
999 .qdev.no_user = 1,
1000 .qdev.props = (Property[]) {
1001 DEFINE_PROP_UINT8("id", APICState, id, -1),
1002 DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1003 DEFINE_PROP_END_OF_LIST(),
1004 }
1005};
1006
1007static void apic_register_devices(void)
1008{
1009 sysbus_register_withprop(&apic_info);
1010}
1011
1012device_init(apic_register_devices)