[mirror_qemu.git] / hw / arm / allwinner-a10.c

/*
 * Allwinner A10 SoC emulation
 *
 * Copyright (C) 2013 Li Guang
 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/char/serial.h"
#include "hw/sysbus.h"
#include "hw/arm/allwinner-a10.h"
#include "hw/misc/unimp.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/loader.h"
#include "target/arm/cpu-qom.h"

#define AW_A10_SRAM_A_BASE      0x00000000
#define AW_A10_DRAMC_BASE       0x01c01000
#define AW_A10_MMC0_BASE        0x01c0f000
#define AW_A10_CCM_BASE         0x01c20000
#define AW_A10_PIC_REG_BASE     0x01c20400
#define AW_A10_PIT_REG_BASE     0x01c20c00
#define AW_A10_UART0_REG_BASE   0x01c28000
#define AW_A10_EMAC_BASE        0x01c0b000
#define AW_A10_EHCI_BASE        0x01c14000
#define AW_A10_OHCI_BASE        0x01c14400
#define AW_A10_SATA_BASE        0x01c18000
#define AW_A10_WDT_BASE         0x01c20c90
#define AW_A10_RTC_BASE         0x01c20d00
#define AW_A10_I2C0_BASE        0x01c2ac00

void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
{
    const int64_t rom_size = 32 * KiB;
    g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);

    if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
        error_setg(&error_fatal, "%s: failed to read BlockBackend data",
                   __func__);
        return;
    }

    rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
                  rom_size, AW_A10_SRAM_A_BASE,
                  NULL, NULL, NULL, NULL, false);
}

static void aw_a10_init(Object *obj)
{
    AwA10State *s = AW_A10(obj);

    object_initialize_child(obj, "cpu", &s->cpu,
                            ARM_CPU_TYPE_NAME("cortex-a8"));

    object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);

    object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);

    object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);

    object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);

    object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);

    object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);

    object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);

    for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
        object_initialize_child(obj, "ehci[*]", &s->ehci[i],
                                TYPE_PLATFORM_EHCI);
        object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
    }

    object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);

    object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);

    object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
}

static void aw_a10_realize(DeviceState *dev, Error **errp)
{
    AwA10State *s = AW_A10(dev);
    SysBusDevice *sysbusdev;

    if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
        return;
    }

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
        return;
    }
    sysbusdev = SYS_BUS_DEVICE(&s->intc);
    sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
    sysbus_connect_irq(sysbusdev, 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(sysbusdev, 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
    qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
        return;
    }
    sysbusdev = SYS_BUS_DEVICE(&s->timer);
    sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
    sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
    sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
    sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
    sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
    sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
    sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));

    memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
                           &error_fatal);
    memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
    create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);

    /* Clock Control Module */
    sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);

    /* DRAM Control Module */
    sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);

    /* FIXME use qdev NIC properties instead of nd_table[] */
    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
    }
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
        return;
    }
    sysbusdev = SYS_BUS_DEVICE(&s->emac);
    sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
    sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));

    /* FIXME use a qdev chardev prop instead of serial_hd() */
    serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
                   qdev_get_gpio_in(dev, 1),
                   115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);

    for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
        g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);

        object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
                                 true, &error_fatal);
        sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                        AW_A10_EHCI_BASE + i * 0x8000);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                           qdev_get_gpio_in(dev, 39 + i));

        object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
                                &error_fatal);
        sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
                        AW_A10_OHCI_BASE + i * 0x8000);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
                           qdev_get_gpio_in(dev, 64 + i));
    }

    /* SD/MMC */
    object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
                             OBJECT(get_system_memory()), &error_fatal);
    sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
    object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
                              "sd-bus");

    /* RTC */
    sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);

    /* I2C */
    sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));

    /* WDT */
    sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
}

static void aw_a10_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = aw_a10_realize;
    /* Reason: Uses serial_hds and nd_table in realize function */
    dc->user_creatable = false;
}

static const TypeInfo aw_a10_type_info = {
    .name = TYPE_AW_A10,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(AwA10State),
    .instance_init = aw_a10_init,
    .class_init = aw_a10_class_init,
};

static void aw_a10_register_types(void)
{
    type_register_static(&aw_a10_type_info);
}

type_init(aw_a10_register_types)
Commit	Line	Data
9158fa54 LG	1	/*
	2	* Allwinner A10 SoC emulation
	3	*
	4	* Copyright (C) 2013 Li Guang
	5	* Written by Li Guang <lig.fnst@cn.fujitsu.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
0b8fa32f	20	#include "qemu/module.h"
21215482	21	#include "hw/char/serial.h"
9158fa54	22	#include "hw/sysbus.h"
9158fa54	23	#include "hw/arm/allwinner-a10.h"
ead07aa4	24	#include "hw/misc/unimp.h"
46517dd4	25	#include "sysemu/sysemu.h"
7abc8cab GR	26	#include "hw/boards.h"
7abc8cab GR	27	#include "hw/usb/hcd-ohci.h"
bb9271ca	28	#include "hw/loader.h"
d780d056	29	#include "target/arm/cpu-qom.h"
9158fa54	30
bb9271ca	31	#define AW_A10_SRAM_A_BASE 0x00000000
edd3a59d	32	#define AW_A10_DRAMC_BASE 0x01c01000
82e48382	33	#define AW_A10_MMC0_BASE 0x01c0f000
423ec28b	34	#define AW_A10_CCM_BASE 0x01c20000
7f0ec989 PMD	35	#define AW_A10_PIC_REG_BASE 0x01c20400
	36	#define AW_A10_PIT_REG_BASE 0x01c20c00
	37	#define AW_A10_UART0_REG_BASE 0x01c28000
	38	#define AW_A10_EMAC_BASE 0x01c0b000
7abc8cab GR	39	#define AW_A10_EHCI_BASE 0x01c14000
7abc8cab GR	40	#define AW_A10_OHCI_BASE 0x01c14400
7f0ec989	41	#define AW_A10_SATA_BASE 0x01c18000
470f9f2d	42	#define AW_A10_WDT_BASE 0x01c20c90
a9ad9e73	43	#define AW_A10_RTC_BASE 0x01c20d00
9be8a82c	44	#define AW_A10_I2C0_BASE 0x01c2ac00
7f0ec989	45
bb9271ca SJ	46	void allwinner_a10_bootrom_setup(AwA10State s, BlockBackend blk)
	47	{
	48	const int64_t rom_size = 32 * KiB;
	49	g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
	50
	51	if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
	52	error_setg(&error_fatal, "%s: failed to read BlockBackend data",
	53	__func__);
	54	return;
	55	}
	56
	57	rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
	58	rom_size, AW_A10_SRAM_A_BASE,
	59	NULL, NULL, NULL, NULL, false);
	60	}
	61
9158fa54 LG	62	static void aw_a10_init(Object *obj)
	63	{
	64	AwA10State *s = AW_A10(obj);
	65
9fc7fc4d MA	66	object_initialize_child(obj, "cpu", &s->cpu,
9fc7fc4d MA	67	ARM_CPU_TYPE_NAME("cortex-a8"));
9158fa54	68
db873cc5	69	object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
9158fa54	70
db873cc5	71	object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
db7dfd4c	72
423ec28b SJ	73	object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
423ec28b SJ	74
edd3a59d SJ	75	object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
edd3a59d SJ	76
db873cc5	77	object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
dca62576	78
db873cc5	79	object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
7abc8cab	80
9be8a82c SJ	81	object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
9be8a82c SJ	82
58aa3a0b PMD	83	for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
	84	object_initialize_child(obj, "ehci[*]", &s->ehci[i],
	85	TYPE_PLATFORM_EHCI);
	86	object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
7abc8cab	87	}
82e48382	88
db873cc5	89	object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
a9ad9e73	90
db873cc5	91	object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
470f9f2d SJ	92
470f9f2d SJ	93	object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
9158fa54 LG	94	}
	95
	96	static void aw_a10_realize(DeviceState dev, Error *errp)
	97	{
	98	AwA10State *s = AW_A10(dev);
	99	SysBusDevice *sysbusdev;
9158fa54	100
668f62ec	101	if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
9158fa54 LG	102	return;
9158fa54 LG	103	}
9158fa54	104
668f62ec	105	if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
9158fa54 LG	106	return;
	107	}
	108	sysbusdev = SYS_BUS_DEVICE(&s->intc);
	109	sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
af4ba4ed PMD	110	sysbus_connect_irq(sysbusdev, 0,
	111	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	112	sysbus_connect_irq(sysbusdev, 1,
	113	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
f8a865d3	114	qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
9158fa54	115
668f62ec	116	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
9158fa54 LG	117	return;
	118	}
	119	sysbusdev = SYS_BUS_DEVICE(&s->timer);
	120	sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
f8a865d3 PMD	121	sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
	122	sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
	123	sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
	124	sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
	125	sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
	126	sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
9158fa54	127
ead07aa4 PMD	128	memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
	129	&error_fatal);
	130	memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
	131	create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
	132
423ec28b SJ	133	/* Clock Control Module */
	134	sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
	135	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
	136
edd3a59d SJ	137	/* DRAM Control Module */
	138	sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
	139	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
	140
8aabc543 TH	141	/* FIXME use qdev NIC properties instead of nd_table[] */
	142	if (nd_table[0].used) {
	143	qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
	144	qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
	145	}
668f62ec	146	if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
db7dfd4c BG	147	return;
	148	}
	149	sysbusdev = SYS_BUS_DEVICE(&s->emac);
	150	sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
f8a865d3	151	sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
db7dfd4c	152
668f62ec	153	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
dca62576 PC	154	return;
	155	}
	156	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
f8a865d3	157	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
dca62576	158
9bca0edb	159	/* FIXME use a qdev chardev prop instead of serial_hd() */
f8a865d3 PMD	160	serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
f8a865d3 PMD	161	qdev_get_gpio_in(dev, 1),
9bca0edb	162	115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
7abc8cab	163
58aa3a0b PMD	164	for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
	165	g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
	166
	167	object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
	168	true, &error_fatal);
	169	sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
	170	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	171	AW_A10_EHCI_BASE + i * 0x8000);
	172	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	173	qdev_get_gpio_in(dev, 39 + i));
	174
	175	object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
	176	&error_fatal);
	177	sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
	178	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
	179	AW_A10_OHCI_BASE + i * 0x8000);
	180	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
	181	qdev_get_gpio_in(dev, 64 + i));
7abc8cab	182	}
82e48382 NL	183
82e48382 NL	184	/* SD/MMC */
b3aec952 PMD	185	object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
b3aec952 PMD	186	OBJECT(get_system_memory()), &error_fatal);
db873cc5	187	sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
82e48382 NL	188	sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
	189	sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
	190	object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
d2623129	191	"sd-bus");
a9ad9e73 NL	192
a9ad9e73 NL	193	/* RTC */
db873cc5	194	sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
a9ad9e73	195	sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
9be8a82c SJ	196
	197	/* I2C */
	198	sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
	199	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
	200	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
470f9f2d SJ	201
	202	/* WDT */
	203	sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
	204	sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
9158fa54 LG	205	}
	206
	207	static void aw_a10_class_init(ObjectClass oc, void data)
	208	{
	209	DeviceClass *dc = DEVICE_CLASS(oc);
	210
	211	dc->realize = aw_a10_realize;
8aabc543	212	/* Reason: Uses serial_hds and nd_table in realize function */
dc89a180	213	dc->user_creatable = false;
9158fa54 LG	214	}
	215
	216	static const TypeInfo aw_a10_type_info = {
	217	.name = TYPE_AW_A10,
	218	.parent = TYPE_DEVICE,
	219	.instance_size = sizeof(AwA10State),
	220	.instance_init = aw_a10_init,
	221	.class_init = aw_a10_class_init,
	222	};
	223
	224	static void aw_a10_register_types(void)
	225	{
	226	type_register_static(&aw_a10_type_info);
	227	}
	228
	229	type_init(aw_a10_register_types)