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Commit | Line | Data |
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9e5e54d1 | 1 | /* |
93dbd103 | 2 | * Arm SSE (Subsystems for Embedded): IoTKit |
9e5e54d1 PM |
3 | * |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
13 | #include "qemu/log.h" | |
14 | #include "qapi/error.h" | |
15 | #include "trace.h" | |
16 | #include "hw/sysbus.h" | |
17 | #include "hw/registerfields.h" | |
6eee5d24 | 18 | #include "hw/arm/armsse.h" |
9e5e54d1 PM |
19 | #include "hw/arm/arm.h" |
20 | ||
dde0c491 PM |
21 | /* Format of the System Information block SYS_CONFIG register */ |
22 | typedef enum SysConfigFormat { | |
23 | IoTKitFormat, | |
24 | SSE200Format, | |
25 | } SysConfigFormat; | |
26 | ||
4c3690b5 PM |
27 | struct ARMSSEInfo { |
28 | const char *name; | |
f0cab7fe | 29 | int sram_banks; |
91c1e9fc | 30 | int num_cpus; |
dde0c491 PM |
31 | uint32_t sys_version; |
32 | SysConfigFormat sys_config_format; | |
f8574705 | 33 | bool has_mhus; |
e0b00f1b | 34 | bool has_ppus; |
2357bca5 | 35 | bool has_cachectrl; |
c1f57257 | 36 | bool has_cpusecctrl; |
ade67dcd | 37 | bool has_cpuid; |
4c3690b5 PM |
38 | }; |
39 | ||
40 | static const ARMSSEInfo armsse_variants[] = { | |
41 | { | |
42 | .name = TYPE_IOTKIT, | |
f0cab7fe | 43 | .sram_banks = 1, |
91c1e9fc | 44 | .num_cpus = 1, |
dde0c491 PM |
45 | .sys_version = 0x41743, |
46 | .sys_config_format = IoTKitFormat, | |
f8574705 | 47 | .has_mhus = false, |
e0b00f1b | 48 | .has_ppus = false, |
2357bca5 | 49 | .has_cachectrl = false, |
c1f57257 | 50 | .has_cpusecctrl = false, |
ade67dcd | 51 | .has_cpuid = false, |
4c3690b5 | 52 | }, |
0829d24e PM |
53 | { |
54 | .name = TYPE_SSE200, | |
55 | .sram_banks = 4, | |
56 | .num_cpus = 2, | |
57 | .sys_version = 0x22041743, | |
58 | .sys_config_format = SSE200Format, | |
59 | .has_mhus = true, | |
60 | .has_ppus = true, | |
61 | .has_cachectrl = true, | |
62 | .has_cpusecctrl = true, | |
63 | .has_cpuid = true, | |
64 | }, | |
4c3690b5 PM |
65 | }; |
66 | ||
dde0c491 PM |
67 | static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) |
68 | { | |
69 | /* Return the SYS_CONFIG value for this SSE */ | |
70 | uint32_t sys_config; | |
71 | ||
72 | switch (info->sys_config_format) { | |
73 | case IoTKitFormat: | |
74 | sys_config = 0; | |
75 | sys_config = deposit32(sys_config, 0, 4, info->sram_banks); | |
76 | sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); | |
77 | break; | |
78 | case SSE200Format: | |
79 | sys_config = 0; | |
80 | sys_config = deposit32(sys_config, 0, 4, info->sram_banks); | |
81 | sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); | |
82 | sys_config = deposit32(sys_config, 24, 4, 2); | |
83 | if (info->num_cpus > 1) { | |
84 | sys_config = deposit32(sys_config, 10, 1, 1); | |
85 | sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); | |
86 | sys_config = deposit32(sys_config, 28, 4, 2); | |
87 | } | |
88 | break; | |
89 | default: | |
90 | g_assert_not_reached(); | |
91 | } | |
92 | return sys_config; | |
93 | } | |
94 | ||
d61e4e1f PM |
95 | /* Clock frequency in HZ of the 32KHz "slow clock" */ |
96 | #define S32KCLK (32 * 1000) | |
97 | ||
91c1e9fc PM |
98 | /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ |
99 | static bool irq_is_common[32] = { | |
100 | [0 ... 5] = true, | |
101 | /* 6, 7: per-CPU MHU interrupts */ | |
102 | [8 ... 12] = true, | |
103 | /* 13: per-CPU icache interrupt */ | |
104 | /* 14: reserved */ | |
105 | [15 ... 20] = true, | |
106 | /* 21: reserved */ | |
107 | [22 ... 26] = true, | |
108 | /* 27: reserved */ | |
109 | /* 28, 29: per-CPU CTI interrupts */ | |
110 | /* 30, 31: reserved */ | |
111 | }; | |
112 | ||
9e5e54d1 PM |
113 | /* Create an alias region of @size bytes starting at @base |
114 | * which mirrors the memory starting at @orig. | |
115 | */ | |
93dbd103 | 116 | static void make_alias(ARMSSE *s, MemoryRegion *mr, const char *name, |
9e5e54d1 PM |
117 | hwaddr base, hwaddr size, hwaddr orig) |
118 | { | |
119 | memory_region_init_alias(mr, NULL, name, &s->container, orig, size); | |
120 | /* The alias is even lower priority than unimplemented_device regions */ | |
121 | memory_region_add_subregion_overlap(&s->container, base, mr, -1500); | |
122 | } | |
123 | ||
9e5e54d1 PM |
124 | static void irq_status_forwarder(void *opaque, int n, int level) |
125 | { | |
126 | qemu_irq destirq = opaque; | |
127 | ||
128 | qemu_set_irq(destirq, level); | |
129 | } | |
130 | ||
131 | static void nsccfg_handler(void *opaque, int n, int level) | |
132 | { | |
93dbd103 | 133 | ARMSSE *s = ARMSSE(opaque); |
9e5e54d1 PM |
134 | |
135 | s->nsccfg = level; | |
136 | } | |
137 | ||
13628891 | 138 | static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) |
9e5e54d1 PM |
139 | { |
140 | /* Each of the 4 AHB and 4 APB PPCs that might be present in a | |
93dbd103 | 141 | * system using the ARMSSE has a collection of control lines which |
9e5e54d1 | 142 | * are provided by the security controller and which we want to |
93dbd103 PM |
143 | * expose as control lines on the ARMSSE device itself, so the |
144 | * code using the ARMSSE can wire them up to the PPCs. | |
9e5e54d1 PM |
145 | */ |
146 | SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; | |
13628891 | 147 | DeviceState *armssedev = DEVICE(s); |
9e5e54d1 PM |
148 | DeviceState *dev_secctl = DEVICE(&s->secctl); |
149 | DeviceState *dev_splitter = DEVICE(splitter); | |
150 | char *name; | |
151 | ||
152 | name = g_strdup_printf("%s_nonsec", ppcname); | |
13628891 | 153 | qdev_pass_gpios(dev_secctl, armssedev, name); |
9e5e54d1 PM |
154 | g_free(name); |
155 | name = g_strdup_printf("%s_ap", ppcname); | |
13628891 | 156 | qdev_pass_gpios(dev_secctl, armssedev, name); |
9e5e54d1 PM |
157 | g_free(name); |
158 | name = g_strdup_printf("%s_irq_enable", ppcname); | |
13628891 | 159 | qdev_pass_gpios(dev_secctl, armssedev, name); |
9e5e54d1 PM |
160 | g_free(name); |
161 | name = g_strdup_printf("%s_irq_clear", ppcname); | |
13628891 | 162 | qdev_pass_gpios(dev_secctl, armssedev, name); |
9e5e54d1 PM |
163 | g_free(name); |
164 | ||
165 | /* irq_status is a little more tricky, because we need to | |
166 | * split it so we can send it both to the security controller | |
167 | * and to our OR gate for the NVIC interrupt line. | |
168 | * Connect up the splitter's outputs, and create a GPIO input | |
169 | * which will pass the line state to the input splitter. | |
170 | */ | |
171 | name = g_strdup_printf("%s_irq_status", ppcname); | |
172 | qdev_connect_gpio_out(dev_splitter, 0, | |
173 | qdev_get_gpio_in_named(dev_secctl, | |
174 | name, 0)); | |
175 | qdev_connect_gpio_out(dev_splitter, 1, | |
176 | qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); | |
177 | s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); | |
13628891 | 178 | qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, |
9e5e54d1 PM |
179 | s->irq_status_in[ppcnum], name, 1); |
180 | g_free(name); | |
181 | } | |
182 | ||
13628891 | 183 | static void armsse_forward_sec_resp_cfg(ARMSSE *s) |
9e5e54d1 PM |
184 | { |
185 | /* Forward the 3rd output from the splitter device as a | |
13628891 | 186 | * named GPIO output of the armsse object. |
9e5e54d1 PM |
187 | */ |
188 | DeviceState *dev = DEVICE(s); | |
189 | DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); | |
190 | ||
191 | qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); | |
192 | s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, | |
193 | s->sec_resp_cfg, 1); | |
194 | qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); | |
195 | } | |
196 | ||
13628891 | 197 | static void armsse_init(Object *obj) |
9e5e54d1 | 198 | { |
93dbd103 | 199 | ARMSSE *s = ARMSSE(obj); |
f0cab7fe PM |
200 | ARMSSEClass *asc = ARMSSE_GET_CLASS(obj); |
201 | const ARMSSEInfo *info = asc->info; | |
9e5e54d1 PM |
202 | int i; |
203 | ||
f0cab7fe | 204 | assert(info->sram_banks <= MAX_SRAM_BANKS); |
91c1e9fc | 205 | assert(info->num_cpus <= SSE_MAX_CPUS); |
f0cab7fe | 206 | |
13628891 | 207 | memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); |
9e5e54d1 | 208 | |
91c1e9fc | 209 | for (i = 0; i < info->num_cpus; i++) { |
7cd3a2e0 PM |
210 | /* |
211 | * We put each CPU in its own cluster as they are logically | |
212 | * distinct and may be configured differently. | |
213 | */ | |
214 | char *name; | |
215 | ||
216 | name = g_strdup_printf("cluster%d", i); | |
217 | object_initialize_child(obj, name, &s->cluster[i], | |
218 | sizeof(s->cluster[i]), TYPE_CPU_CLUSTER, | |
219 | &error_abort, NULL); | |
220 | qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); | |
221 | g_free(name); | |
222 | ||
223 | name = g_strdup_printf("armv7m%d", i); | |
224 | sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, | |
225 | &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7M); | |
91c1e9fc PM |
226 | qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", |
227 | ARM_CPU_TYPE_NAME("cortex-m33")); | |
228 | g_free(name); | |
d847ca51 PM |
229 | name = g_strdup_printf("arm-sse-cpu-container%d", i); |
230 | memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); | |
231 | g_free(name); | |
232 | if (i > 0) { | |
233 | name = g_strdup_printf("arm-sse-container-alias%d", i); | |
234 | memory_region_init_alias(&s->container_alias[i - 1], obj, | |
235 | name, &s->container, 0, UINT64_MAX); | |
236 | g_free(name); | |
237 | } | |
91c1e9fc | 238 | } |
9e5e54d1 | 239 | |
955cbc6b TH |
240 | sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), |
241 | TYPE_IOTKIT_SECCTL); | |
242 | sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), | |
243 | TYPE_TZ_PPC); | |
244 | sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), | |
245 | TYPE_TZ_PPC); | |
f0cab7fe PM |
246 | for (i = 0; i < info->sram_banks; i++) { |
247 | char *name = g_strdup_printf("mpc%d", i); | |
248 | sysbus_init_child_obj(obj, name, &s->mpc[i], | |
249 | sizeof(s->mpc[i]), TYPE_TZ_MPC); | |
250 | g_free(name); | |
251 | } | |
955cbc6b TH |
252 | object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, |
253 | sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, | |
254 | &error_abort, NULL); | |
255 | ||
f0cab7fe | 256 | for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { |
bb75e16d PM |
257 | char *name = g_strdup_printf("mpc-irq-splitter-%d", i); |
258 | SplitIRQ *splitter = &s->mpc_irq_splitter[i]; | |
259 | ||
955cbc6b TH |
260 | object_initialize_child(obj, name, splitter, sizeof(*splitter), |
261 | TYPE_SPLIT_IRQ, &error_abort, NULL); | |
bb75e16d PM |
262 | g_free(name); |
263 | } | |
955cbc6b TH |
264 | sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0), |
265 | TYPE_CMSDK_APB_TIMER); | |
266 | sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1), | |
267 | TYPE_CMSDK_APB_TIMER); | |
e2d203ba PM |
268 | sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), |
269 | TYPE_CMSDK_APB_TIMER); | |
955cbc6b | 270 | sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), |
017d069d | 271 | TYPE_CMSDK_APB_DUALTIMER); |
d61e4e1f PM |
272 | sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog, |
273 | sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG); | |
274 | sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog, | |
275 | sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG); | |
276 | sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog, | |
277 | sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG); | |
13628891 | 278 | sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl, |
06e65af3 | 279 | sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); |
13628891 | 280 | sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, |
06e65af3 | 281 | sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); |
f8574705 PM |
282 | if (info->has_mhus) { |
283 | sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), | |
284 | TYPE_UNIMPLEMENTED_DEVICE); | |
285 | sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), | |
286 | TYPE_UNIMPLEMENTED_DEVICE); | |
287 | } | |
e0b00f1b PM |
288 | if (info->has_ppus) { |
289 | for (i = 0; i < info->num_cpus; i++) { | |
290 | char *name = g_strdup_printf("CPU%dCORE_PPU", i); | |
291 | int ppuidx = CPU0CORE_PPU + i; | |
292 | ||
293 | sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], | |
294 | sizeof(s->ppu[ppuidx]), | |
295 | TYPE_UNIMPLEMENTED_DEVICE); | |
296 | g_free(name); | |
297 | } | |
298 | sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], | |
299 | sizeof(s->ppu[DBG_PPU]), | |
300 | TYPE_UNIMPLEMENTED_DEVICE); | |
301 | for (i = 0; i < info->sram_banks; i++) { | |
302 | char *name = g_strdup_printf("RAM%d_PPU", i); | |
303 | int ppuidx = RAM0_PPU + i; | |
304 | ||
305 | sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], | |
306 | sizeof(s->ppu[ppuidx]), | |
307 | TYPE_UNIMPLEMENTED_DEVICE); | |
308 | g_free(name); | |
309 | } | |
310 | } | |
2357bca5 PM |
311 | if (info->has_cachectrl) { |
312 | for (i = 0; i < info->num_cpus; i++) { | |
313 | char *name = g_strdup_printf("cachectrl%d", i); | |
314 | ||
315 | sysbus_init_child_obj(obj, name, &s->cachectrl[i], | |
316 | sizeof(s->cachectrl[i]), | |
317 | TYPE_UNIMPLEMENTED_DEVICE); | |
318 | g_free(name); | |
319 | } | |
320 | } | |
c1f57257 PM |
321 | if (info->has_cpusecctrl) { |
322 | for (i = 0; i < info->num_cpus; i++) { | |
323 | char *name = g_strdup_printf("cpusecctrl%d", i); | |
324 | ||
325 | sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], | |
326 | sizeof(s->cpusecctrl[i]), | |
327 | TYPE_UNIMPLEMENTED_DEVICE); | |
328 | g_free(name); | |
329 | } | |
330 | } | |
ade67dcd PM |
331 | if (info->has_cpuid) { |
332 | for (i = 0; i < info->num_cpus; i++) { | |
333 | char *name = g_strdup_printf("cpuid%d", i); | |
334 | ||
335 | sysbus_init_child_obj(obj, name, &s->cpuid[i], | |
336 | sizeof(s->cpuid[i]), | |
337 | TYPE_ARMSSE_CPUID); | |
338 | g_free(name); | |
339 | } | |
340 | } | |
d61e4e1f PM |
341 | object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, |
342 | sizeof(s->nmi_orgate), TYPE_OR_IRQ, | |
343 | &error_abort, NULL); | |
955cbc6b TH |
344 | object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, |
345 | sizeof(s->ppc_irq_orgate), TYPE_OR_IRQ, | |
346 | &error_abort, NULL); | |
347 | object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, | |
348 | sizeof(s->sec_resp_splitter), TYPE_SPLIT_IRQ, | |
349 | &error_abort, NULL); | |
9e5e54d1 PM |
350 | for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { |
351 | char *name = g_strdup_printf("ppc-irq-splitter-%d", i); | |
352 | SplitIRQ *splitter = &s->ppc_irq_splitter[i]; | |
353 | ||
955cbc6b TH |
354 | object_initialize_child(obj, name, splitter, sizeof(*splitter), |
355 | TYPE_SPLIT_IRQ, &error_abort, NULL); | |
356 | g_free(name); | |
9e5e54d1 | 357 | } |
91c1e9fc PM |
358 | if (info->num_cpus > 1) { |
359 | for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { | |
360 | if (irq_is_common[i]) { | |
361 | char *name = g_strdup_printf("cpu-irq-splitter%d", i); | |
362 | SplitIRQ *splitter = &s->cpu_irq_splitter[i]; | |
363 | ||
364 | object_initialize_child(obj, name, splitter, sizeof(*splitter), | |
365 | TYPE_SPLIT_IRQ, &error_abort, NULL); | |
366 | g_free(name); | |
367 | } | |
368 | } | |
369 | } | |
9e5e54d1 PM |
370 | } |
371 | ||
13628891 | 372 | static void armsse_exp_irq(void *opaque, int n, int level) |
9e5e54d1 | 373 | { |
91c1e9fc | 374 | qemu_irq *irqarray = opaque; |
9e5e54d1 | 375 | |
91c1e9fc | 376 | qemu_set_irq(irqarray[n], level); |
9e5e54d1 PM |
377 | } |
378 | ||
13628891 | 379 | static void armsse_mpcexp_status(void *opaque, int n, int level) |
bb75e16d | 380 | { |
93dbd103 | 381 | ARMSSE *s = ARMSSE(opaque); |
bb75e16d PM |
382 | qemu_set_irq(s->mpcexp_status_in[n], level); |
383 | } | |
384 | ||
91c1e9fc PM |
385 | static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) |
386 | { | |
387 | /* | |
388 | * Return a qemu_irq which can be used to signal IRQ n to | |
389 | * all CPUs in the SSE. | |
390 | */ | |
391 | ARMSSEClass *asc = ARMSSE_GET_CLASS(s); | |
392 | const ARMSSEInfo *info = asc->info; | |
393 | ||
394 | assert(irq_is_common[irqno]); | |
395 | ||
396 | if (info->num_cpus == 1) { | |
397 | /* Only one CPU -- just connect directly to it */ | |
398 | return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); | |
399 | } else { | |
400 | /* Connect to the splitter which feeds all CPUs */ | |
401 | return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); | |
402 | } | |
403 | } | |
404 | ||
e0b00f1b PM |
405 | static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) |
406 | { | |
407 | /* Map a PPU unimplemented device stub */ | |
408 | DeviceState *dev = DEVICE(&s->ppu[ppuidx]); | |
409 | ||
410 | qdev_prop_set_string(dev, "name", name); | |
411 | qdev_prop_set_uint64(dev, "size", 0x1000); | |
412 | qdev_init_nofail(dev); | |
413 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); | |
414 | } | |
415 | ||
13628891 | 416 | static void armsse_realize(DeviceState *dev, Error **errp) |
9e5e54d1 | 417 | { |
93dbd103 | 418 | ARMSSE *s = ARMSSE(dev); |
f0cab7fe PM |
419 | ARMSSEClass *asc = ARMSSE_GET_CLASS(dev); |
420 | const ARMSSEInfo *info = asc->info; | |
9e5e54d1 PM |
421 | int i; |
422 | MemoryRegion *mr; | |
423 | Error *err = NULL; | |
424 | SysBusDevice *sbd_apb_ppc0; | |
425 | SysBusDevice *sbd_secctl; | |
426 | DeviceState *dev_apb_ppc0; | |
427 | DeviceState *dev_apb_ppc1; | |
428 | DeviceState *dev_secctl; | |
429 | DeviceState *dev_splitter; | |
4b635cf7 | 430 | uint32_t addr_width_max; |
9e5e54d1 PM |
431 | |
432 | if (!s->board_memory) { | |
433 | error_setg(errp, "memory property was not set"); | |
434 | return; | |
435 | } | |
436 | ||
437 | if (!s->mainclk_frq) { | |
438 | error_setg(errp, "MAINCLK property was not set"); | |
439 | return; | |
440 | } | |
441 | ||
4b635cf7 PM |
442 | /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ |
443 | assert(is_power_of_2(info->sram_banks)); | |
444 | addr_width_max = 24 - ctz32(info->sram_banks); | |
445 | if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { | |
446 | error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", | |
447 | addr_width_max); | |
448 | return; | |
449 | } | |
450 | ||
9e5e54d1 PM |
451 | /* Handling of which devices should be available only to secure |
452 | * code is usually done differently for M profile than for A profile. | |
453 | * Instead of putting some devices only into the secure address space, | |
454 | * devices exist in both address spaces but with hard-wired security | |
455 | * permissions that will cause the CPU to fault for non-secure accesses. | |
456 | * | |
93dbd103 | 457 | * The ARMSSE has an IDAU (Implementation Defined Access Unit), |
9e5e54d1 | 458 | * which specifies hard-wired security permissions for different |
93dbd103 | 459 | * areas of the physical address space. For the ARMSSE IDAU, the |
9e5e54d1 PM |
460 | * top 4 bits of the physical address are the IDAU region ID, and |
461 | * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS | |
462 | * region, otherwise it is an S region. | |
463 | * | |
464 | * The various devices and RAMs are generally all mapped twice, | |
465 | * once into a region that the IDAU defines as secure and once | |
466 | * into a non-secure region. They sit behind either a Memory | |
467 | * Protection Controller (for RAM) or a Peripheral Protection | |
468 | * Controller (for devices), which allow a more fine grained | |
469 | * configuration of whether non-secure accesses are permitted. | |
470 | * | |
471 | * (The other place that guest software can configure security | |
472 | * permissions is in the architected SAU (Security Attribution | |
473 | * Unit), which is entirely inside the CPU. The IDAU can upgrade | |
474 | * the security attributes for a region to more restrictive than | |
475 | * the SAU specifies, but cannot downgrade them.) | |
476 | * | |
477 | * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff | |
478 | * 0x20000000..0x2007ffff 32KB FPGA block RAM | |
479 | * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff | |
480 | * 0x40000000..0x4000ffff base peripheral region 1 | |
93dbd103 | 481 | * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) |
9e5e54d1 PM |
482 | * 0x40020000..0x4002ffff system control element peripherals |
483 | * 0x40080000..0x400fffff base peripheral region 2 | |
484 | * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff | |
485 | */ | |
486 | ||
d847ca51 | 487 | memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); |
9e5e54d1 | 488 | |
91c1e9fc PM |
489 | for (i = 0; i < info->num_cpus; i++) { |
490 | DeviceState *cpudev = DEVICE(&s->armv7m[i]); | |
491 | Object *cpuobj = OBJECT(&s->armv7m[i]); | |
492 | int j; | |
493 | char *gpioname; | |
494 | ||
495 | qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); | |
496 | /* | |
497 | * In real hardware the initial Secure VTOR is set from the INITSVTOR0 | |
498 | * register in the IoT Kit System Control Register block, and the | |
499 | * initial value of that is in turn specifiable by the FPGA that | |
500 | * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, | |
501 | * and simply set the CPU's init-svtor to the IoT Kit default value. | |
502 | * In SSE-200 the situation is similar, except that the default value | |
503 | * is a reset-time signal input. Typically a board using the SSE-200 | |
504 | * will have a system control processor whose boot firmware initializes | |
505 | * the INITSVTOR* registers before powering up the CPUs in any case, | |
506 | * so the hardware's default value doesn't matter. QEMU doesn't emulate | |
507 | * the control processor, so instead we behave in the way that the | |
508 | * firmware does. All boards currently known about have firmware that | |
509 | * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, like the | |
510 | * IoTKit default. We can make this more configurable if necessary. | |
511 | */ | |
512 | qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000); | |
513 | /* | |
514 | * Start all CPUs except CPU0 powered down. In real hardware it is | |
515 | * a configurable property of the SSE-200 which CPUs start powered up | |
516 | * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all | |
517 | * the boards we care about start CPU0 and leave CPU1 powered off, | |
518 | * we hard-code that for now. We can add QOM properties for this | |
519 | * later if necessary. | |
520 | */ | |
521 | if (i > 0) { | |
522 | object_property_set_bool(cpuobj, true, "start-powered-off", &err); | |
523 | if (err) { | |
524 | error_propagate(errp, err); | |
525 | return; | |
526 | } | |
527 | } | |
d847ca51 PM |
528 | |
529 | if (i > 0) { | |
530 | memory_region_add_subregion_overlap(&s->cpu_container[i], 0, | |
531 | &s->container_alias[i - 1], -1); | |
532 | } else { | |
533 | memory_region_add_subregion_overlap(&s->cpu_container[i], 0, | |
534 | &s->container, -1); | |
535 | } | |
536 | object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), | |
537 | "memory", &err); | |
91c1e9fc PM |
538 | if (err) { |
539 | error_propagate(errp, err); | |
540 | return; | |
541 | } | |
542 | object_property_set_link(cpuobj, OBJECT(s), "idau", &err); | |
543 | if (err) { | |
544 | error_propagate(errp, err); | |
545 | return; | |
546 | } | |
547 | object_property_set_bool(cpuobj, true, "realized", &err); | |
548 | if (err) { | |
549 | error_propagate(errp, err); | |
550 | return; | |
551 | } | |
7cd3a2e0 PM |
552 | /* |
553 | * The cluster must be realized after the armv7m container, as | |
554 | * the container's CPU object is only created on realize, and the | |
555 | * CPU must exist and have been parented into the cluster before | |
556 | * the cluster is realized. | |
557 | */ | |
558 | object_property_set_bool(OBJECT(&s->cluster[i]), | |
559 | true, "realized", &err); | |
560 | if (err) { | |
561 | error_propagate(errp, err); | |
562 | return; | |
563 | } | |
91c1e9fc PM |
564 | |
565 | /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ | |
566 | s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); | |
567 | for (j = 0; j < s->exp_numirq; j++) { | |
5007c904 | 568 | s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); |
91c1e9fc PM |
569 | } |
570 | if (i == 0) { | |
571 | gpioname = g_strdup("EXP_IRQ"); | |
572 | } else { | |
573 | gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); | |
574 | } | |
575 | qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, | |
576 | s->exp_irqs[i], | |
577 | gpioname, s->exp_numirq); | |
578 | g_free(gpioname); | |
9e5e54d1 PM |
579 | } |
580 | ||
91c1e9fc PM |
581 | /* Wire up the splitters that connect common IRQs to all CPUs */ |
582 | if (info->num_cpus > 1) { | |
583 | for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { | |
584 | if (irq_is_common[i]) { | |
585 | Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); | |
586 | DeviceState *devs = DEVICE(splitter); | |
587 | int cpunum; | |
588 | ||
589 | object_property_set_int(splitter, info->num_cpus, | |
590 | "num-lines", &err); | |
591 | if (err) { | |
592 | error_propagate(errp, err); | |
593 | return; | |
594 | } | |
595 | object_property_set_bool(splitter, true, "realized", &err); | |
596 | if (err) { | |
597 | error_propagate(errp, err); | |
598 | return; | |
599 | } | |
600 | for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { | |
601 | DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); | |
602 | ||
603 | qdev_connect_gpio_out(devs, cpunum, | |
604 | qdev_get_gpio_in(cpudev, i)); | |
605 | } | |
606 | } | |
607 | } | |
9e5e54d1 | 608 | } |
9e5e54d1 PM |
609 | |
610 | /* Set up the big aliases first */ | |
611 | make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x00000000); | |
612 | make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x20000000); | |
613 | /* The 0x50000000..0x5fffffff region is not a pure alias: it has | |
614 | * a few extra devices that only appear there (generally the | |
615 | * control interfaces for the protection controllers). | |
616 | * We implement this by mapping those devices over the top of this | |
617 | * alias MR at a higher priority. | |
618 | */ | |
619 | make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x40000000); | |
620 | ||
9e5e54d1 PM |
621 | |
622 | /* Security controller */ | |
623 | object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); | |
624 | if (err) { | |
625 | error_propagate(errp, err); | |
626 | return; | |
627 | } | |
628 | sbd_secctl = SYS_BUS_DEVICE(&s->secctl); | |
629 | dev_secctl = DEVICE(&s->secctl); | |
630 | sysbus_mmio_map(sbd_secctl, 0, 0x50080000); | |
631 | sysbus_mmio_map(sbd_secctl, 1, 0x40080000); | |
632 | ||
633 | s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); | |
634 | qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); | |
635 | ||
636 | /* The sec_resp_cfg output from the security controller must be split into | |
93dbd103 PM |
637 | * multiple lines, one for each of the PPCs within the ARMSSE and one |
638 | * that will be an output from the ARMSSE to the system. | |
9e5e54d1 PM |
639 | */ |
640 | object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, | |
641 | "num-lines", &err); | |
642 | if (err) { | |
643 | error_propagate(errp, err); | |
644 | return; | |
645 | } | |
646 | object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, | |
647 | "realized", &err); | |
648 | if (err) { | |
649 | error_propagate(errp, err); | |
650 | return; | |
651 | } | |
652 | dev_splitter = DEVICE(&s->sec_resp_splitter); | |
653 | qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, | |
654 | qdev_get_gpio_in(dev_splitter, 0)); | |
655 | ||
f0cab7fe PM |
656 | /* Each SRAM bank lives behind its own Memory Protection Controller */ |
657 | for (i = 0; i < info->sram_banks; i++) { | |
658 | char *ramname = g_strdup_printf("armsse.sram%d", i); | |
659 | SysBusDevice *sbd_mpc; | |
4b635cf7 | 660 | uint32_t sram_bank_size = 1 << s->sram_addr_width; |
f0cab7fe | 661 | |
4b635cf7 PM |
662 | memory_region_init_ram(&s->sram[i], NULL, ramname, |
663 | sram_bank_size, &err); | |
f0cab7fe PM |
664 | g_free(ramname); |
665 | if (err) { | |
666 | error_propagate(errp, err); | |
667 | return; | |
668 | } | |
669 | object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), | |
670 | "downstream", &err); | |
671 | if (err) { | |
672 | error_propagate(errp, err); | |
673 | return; | |
674 | } | |
675 | object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err); | |
676 | if (err) { | |
677 | error_propagate(errp, err); | |
678 | return; | |
679 | } | |
680 | /* Map the upstream end of the MPC into the right place... */ | |
681 | sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); | |
4b635cf7 PM |
682 | memory_region_add_subregion(&s->container, |
683 | 0x20000000 + i * sram_bank_size, | |
f0cab7fe PM |
684 | sysbus_mmio_get_region(sbd_mpc, 1)); |
685 | /* ...and its register interface */ | |
686 | memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, | |
687 | sysbus_mmio_get_region(sbd_mpc, 0)); | |
af60b291 | 688 | } |
af60b291 | 689 | |
bb75e16d PM |
690 | /* We must OR together lines from the MPC splitters to go to the NVIC */ |
691 | object_property_set_int(OBJECT(&s->mpc_irq_orgate), | |
f0cab7fe PM |
692 | IOTS_NUM_EXP_MPC + info->sram_banks, |
693 | "num-lines", &err); | |
bb75e16d PM |
694 | if (err) { |
695 | error_propagate(errp, err); | |
696 | return; | |
697 | } | |
698 | object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true, | |
699 | "realized", &err); | |
700 | if (err) { | |
701 | error_propagate(errp, err); | |
702 | return; | |
703 | } | |
704 | qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, | |
91c1e9fc | 705 | armsse_get_common_irq_in(s, 9)); |
bb75e16d | 706 | |
9e5e54d1 PM |
707 | /* Devices behind APB PPC0: |
708 | * 0x40000000: timer0 | |
709 | * 0x40001000: timer1 | |
710 | * 0x40002000: dual timer | |
f8574705 PM |
711 | * 0x40003000: MHU0 (SSE-200 only) |
712 | * 0x40004000: MHU1 (SSE-200 only) | |
9e5e54d1 PM |
713 | * We must configure and realize each downstream device and connect |
714 | * it to the appropriate PPC port; then we can realize the PPC and | |
715 | * map its upstream ends to the right place in the container. | |
716 | */ | |
717 | qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); | |
718 | object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); | |
719 | if (err) { | |
720 | error_propagate(errp, err); | |
721 | return; | |
722 | } | |
723 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, | |
91c1e9fc | 724 | armsse_get_common_irq_in(s, 3)); |
9e5e54d1 PM |
725 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); |
726 | object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); | |
727 | if (err) { | |
728 | error_propagate(errp, err); | |
729 | return; | |
730 | } | |
731 | ||
732 | qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); | |
733 | object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); | |
734 | if (err) { | |
735 | error_propagate(errp, err); | |
736 | return; | |
737 | } | |
738 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, | |
91c1e9fc | 739 | armsse_get_common_irq_in(s, 4)); |
9e5e54d1 PM |
740 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); |
741 | object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); | |
742 | if (err) { | |
743 | error_propagate(errp, err); | |
744 | return; | |
745 | } | |
746 | ||
017d069d PM |
747 | |
748 | qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); | |
9e5e54d1 PM |
749 | object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); |
750 | if (err) { | |
751 | error_propagate(errp, err); | |
752 | return; | |
753 | } | |
017d069d | 754 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, |
91c1e9fc | 755 | armsse_get_common_irq_in(s, 5)); |
9e5e54d1 PM |
756 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); |
757 | object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); | |
758 | if (err) { | |
759 | error_propagate(errp, err); | |
760 | return; | |
761 | } | |
762 | ||
f8574705 PM |
763 | if (info->has_mhus) { |
764 | for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { | |
765 | char *name = g_strdup_printf("MHU%d", i); | |
766 | char *port = g_strdup_printf("port[%d]", i + 3); | |
767 | ||
768 | qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name); | |
769 | qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000); | |
770 | object_property_set_bool(OBJECT(&s->mhu[i]), true, | |
771 | "realized", &err); | |
772 | if (err) { | |
773 | error_propagate(errp, err); | |
774 | return; | |
775 | } | |
776 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0); | |
777 | object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), | |
778 | port, &err); | |
779 | if (err) { | |
780 | error_propagate(errp, err); | |
781 | return; | |
782 | } | |
783 | g_free(name); | |
784 | g_free(port); | |
785 | } | |
786 | } | |
787 | ||
9e5e54d1 PM |
788 | object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); |
789 | if (err) { | |
790 | error_propagate(errp, err); | |
791 | return; | |
792 | } | |
793 | ||
794 | sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); | |
795 | dev_apb_ppc0 = DEVICE(&s->apb_ppc0); | |
796 | ||
797 | mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); | |
798 | memory_region_add_subregion(&s->container, 0x40000000, mr); | |
799 | mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); | |
800 | memory_region_add_subregion(&s->container, 0x40001000, mr); | |
801 | mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); | |
802 | memory_region_add_subregion(&s->container, 0x40002000, mr); | |
f8574705 PM |
803 | if (info->has_mhus) { |
804 | mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); | |
805 | memory_region_add_subregion(&s->container, 0x40003000, mr); | |
806 | mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); | |
807 | memory_region_add_subregion(&s->container, 0x40004000, mr); | |
808 | } | |
9e5e54d1 PM |
809 | for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { |
810 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, | |
811 | qdev_get_gpio_in_named(dev_apb_ppc0, | |
812 | "cfg_nonsec", i)); | |
813 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, | |
814 | qdev_get_gpio_in_named(dev_apb_ppc0, | |
815 | "cfg_ap", i)); | |
816 | } | |
817 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, | |
818 | qdev_get_gpio_in_named(dev_apb_ppc0, | |
819 | "irq_enable", 0)); | |
820 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, | |
821 | qdev_get_gpio_in_named(dev_apb_ppc0, | |
822 | "irq_clear", 0)); | |
823 | qdev_connect_gpio_out(dev_splitter, 0, | |
824 | qdev_get_gpio_in_named(dev_apb_ppc0, | |
825 | "cfg_sec_resp", 0)); | |
826 | ||
827 | /* All the PPC irq lines (from the 2 internal PPCs and the 8 external | |
828 | * ones) are sent individually to the security controller, and also | |
829 | * ORed together to give a single combined PPC interrupt to the NVIC. | |
830 | */ | |
831 | object_property_set_int(OBJECT(&s->ppc_irq_orgate), | |
832 | NUM_PPCS, "num-lines", &err); | |
833 | if (err) { | |
834 | error_propagate(errp, err); | |
835 | return; | |
836 | } | |
837 | object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, | |
838 | "realized", &err); | |
839 | if (err) { | |
840 | error_propagate(errp, err); | |
841 | return; | |
842 | } | |
843 | qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, | |
91c1e9fc | 844 | armsse_get_common_irq_in(s, 10)); |
9e5e54d1 | 845 | |
2357bca5 PM |
846 | /* |
847 | * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): | |
848 | * private per-CPU region (all these devices are SSE-200 only): | |
849 | * 0x50010000: L1 icache control registers | |
850 | * 0x50011000: CPUSECCTRL (CPU local security control registers) | |
851 | * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block | |
852 | */ | |
853 | if (info->has_cachectrl) { | |
854 | for (i = 0; i < info->num_cpus; i++) { | |
855 | char *name = g_strdup_printf("cachectrl%d", i); | |
856 | MemoryRegion *mr; | |
857 | ||
858 | qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); | |
859 | g_free(name); | |
860 | qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); | |
861 | object_property_set_bool(OBJECT(&s->cachectrl[i]), true, | |
862 | "realized", &err); | |
863 | if (err) { | |
864 | error_propagate(errp, err); | |
865 | return; | |
866 | } | |
867 | ||
868 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); | |
869 | memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); | |
870 | } | |
871 | } | |
c1f57257 PM |
872 | if (info->has_cpusecctrl) { |
873 | for (i = 0; i < info->num_cpus; i++) { | |
874 | char *name = g_strdup_printf("CPUSECCTRL%d", i); | |
875 | MemoryRegion *mr; | |
876 | ||
877 | qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); | |
878 | g_free(name); | |
879 | qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); | |
880 | object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, | |
881 | "realized", &err); | |
882 | if (err) { | |
883 | error_propagate(errp, err); | |
884 | return; | |
885 | } | |
886 | ||
887 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); | |
888 | memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); | |
889 | } | |
890 | } | |
ade67dcd PM |
891 | if (info->has_cpuid) { |
892 | for (i = 0; i < info->num_cpus; i++) { | |
893 | MemoryRegion *mr; | |
894 | ||
895 | qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); | |
896 | object_property_set_bool(OBJECT(&s->cpuid[i]), true, | |
897 | "realized", &err); | |
898 | if (err) { | |
899 | error_propagate(errp, err); | |
900 | return; | |
901 | } | |
902 | ||
903 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); | |
904 | memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); | |
905 | } | |
906 | } | |
9e5e54d1 | 907 | |
93dbd103 | 908 | /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ |
9e5e54d1 PM |
909 | /* Devices behind APB PPC1: |
910 | * 0x4002f000: S32K timer | |
911 | */ | |
e2d203ba | 912 | qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); |
9e5e54d1 PM |
913 | object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); |
914 | if (err) { | |
915 | error_propagate(errp, err); | |
916 | return; | |
917 | } | |
e2d203ba | 918 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, |
91c1e9fc | 919 | armsse_get_common_irq_in(s, 2)); |
9e5e54d1 PM |
920 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); |
921 | object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); | |
922 | if (err) { | |
923 | error_propagate(errp, err); | |
924 | return; | |
925 | } | |
926 | ||
927 | object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); | |
928 | if (err) { | |
929 | error_propagate(errp, err); | |
930 | return; | |
931 | } | |
932 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); | |
933 | memory_region_add_subregion(&s->container, 0x4002f000, mr); | |
934 | ||
935 | dev_apb_ppc1 = DEVICE(&s->apb_ppc1); | |
936 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, | |
937 | qdev_get_gpio_in_named(dev_apb_ppc1, | |
938 | "cfg_nonsec", 0)); | |
939 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, | |
940 | qdev_get_gpio_in_named(dev_apb_ppc1, | |
941 | "cfg_ap", 0)); | |
942 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, | |
943 | qdev_get_gpio_in_named(dev_apb_ppc1, | |
944 | "irq_enable", 0)); | |
945 | qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, | |
946 | qdev_get_gpio_in_named(dev_apb_ppc1, | |
947 | "irq_clear", 0)); | |
948 | qdev_connect_gpio_out(dev_splitter, 1, | |
949 | qdev_get_gpio_in_named(dev_apb_ppc1, | |
950 | "cfg_sec_resp", 0)); | |
951 | ||
dde0c491 PM |
952 | object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, |
953 | "SYS_VERSION", &err); | |
954 | if (err) { | |
955 | error_propagate(errp, err); | |
956 | return; | |
957 | } | |
958 | object_property_set_int(OBJECT(&s->sysinfo), | |
959 | armsse_sys_config_value(s, info), | |
960 | "SYS_CONFIG", &err); | |
961 | if (err) { | |
962 | error_propagate(errp, err); | |
963 | return; | |
964 | } | |
06e65af3 PM |
965 | object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err); |
966 | if (err) { | |
967 | error_propagate(errp, err); | |
968 | return; | |
969 | } | |
970 | /* System information registers */ | |
971 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); | |
972 | /* System control registers */ | |
973 | object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); | |
974 | if (err) { | |
975 | error_propagate(errp, err); | |
976 | return; | |
977 | } | |
978 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); | |
d61e4e1f | 979 | |
e0b00f1b PM |
980 | if (info->has_ppus) { |
981 | /* CPUnCORE_PPU for each CPU */ | |
982 | for (i = 0; i < info->num_cpus; i++) { | |
983 | char *name = g_strdup_printf("CPU%dCORE_PPU", i); | |
984 | ||
985 | map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); | |
986 | /* | |
987 | * We don't support CPU debug so don't create the | |
988 | * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. | |
989 | */ | |
990 | g_free(name); | |
991 | } | |
992 | map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); | |
993 | ||
994 | for (i = 0; i < info->sram_banks; i++) { | |
995 | char *name = g_strdup_printf("RAM%d_PPU", i); | |
996 | ||
997 | map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); | |
998 | g_free(name); | |
999 | } | |
1000 | } | |
1001 | ||
d61e4e1f PM |
1002 | /* This OR gate wires together outputs from the secure watchdogs to NMI */ |
1003 | object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); | |
1004 | if (err) { | |
1005 | error_propagate(errp, err); | |
1006 | return; | |
1007 | } | |
1008 | object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err); | |
1009 | if (err) { | |
1010 | error_propagate(errp, err); | |
1011 | return; | |
1012 | } | |
1013 | qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, | |
1014 | qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); | |
1015 | ||
1016 | qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); | |
1017 | object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err); | |
1018 | if (err) { | |
1019 | error_propagate(errp, err); | |
1020 | return; | |
1021 | } | |
1022 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, | |
1023 | qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); | |
1024 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); | |
9e5e54d1 | 1025 | |
93dbd103 | 1026 | /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ |
9e5e54d1 | 1027 | |
d61e4e1f PM |
1028 | qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); |
1029 | object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err); | |
1030 | if (err) { | |
1031 | error_propagate(errp, err); | |
1032 | return; | |
1033 | } | |
1034 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, | |
91c1e9fc | 1035 | armsse_get_common_irq_in(s, 1)); |
d61e4e1f PM |
1036 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); |
1037 | ||
1038 | qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); | |
1039 | object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err); | |
1040 | if (err) { | |
1041 | error_propagate(errp, err); | |
1042 | return; | |
1043 | } | |
1044 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, | |
1045 | qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); | |
1046 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); | |
9e5e54d1 | 1047 | |
9e5e54d1 PM |
1048 | for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { |
1049 | Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); | |
1050 | ||
1051 | object_property_set_int(splitter, 2, "num-lines", &err); | |
1052 | if (err) { | |
1053 | error_propagate(errp, err); | |
1054 | return; | |
1055 | } | |
1056 | object_property_set_bool(splitter, true, "realized", &err); | |
1057 | if (err) { | |
1058 | error_propagate(errp, err); | |
1059 | return; | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { | |
1064 | char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); | |
1065 | ||
13628891 | 1066 | armsse_forward_ppc(s, ppcname, i); |
9e5e54d1 PM |
1067 | g_free(ppcname); |
1068 | } | |
1069 | ||
1070 | for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { | |
1071 | char *ppcname = g_strdup_printf("apb_ppcexp%d", i); | |
1072 | ||
13628891 | 1073 | armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); |
9e5e54d1 PM |
1074 | g_free(ppcname); |
1075 | } | |
1076 | ||
1077 | for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { | |
1078 | /* Wire up IRQ splitter for internal PPCs */ | |
1079 | DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); | |
1080 | char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", | |
1081 | i - NUM_EXTERNAL_PPCS); | |
1082 | TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; | |
1083 | ||
1084 | qdev_connect_gpio_out(devs, 0, | |
1085 | qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); | |
1086 | qdev_connect_gpio_out(devs, 1, | |
1087 | qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); | |
1088 | qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, | |
1089 | qdev_get_gpio_in(devs, 0)); | |
7a35383a | 1090 | g_free(gpioname); |
9e5e54d1 PM |
1091 | } |
1092 | ||
bb75e16d | 1093 | /* Wire up the splitters for the MPC IRQs */ |
f0cab7fe | 1094 | for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { |
bb75e16d PM |
1095 | SplitIRQ *splitter = &s->mpc_irq_splitter[i]; |
1096 | DeviceState *dev_splitter = DEVICE(splitter); | |
1097 | ||
1098 | object_property_set_int(OBJECT(splitter), 2, "num-lines", &err); | |
1099 | if (err) { | |
1100 | error_propagate(errp, err); | |
1101 | return; | |
1102 | } | |
1103 | object_property_set_bool(OBJECT(splitter), true, "realized", &err); | |
1104 | if (err) { | |
1105 | error_propagate(errp, err); | |
1106 | return; | |
1107 | } | |
1108 | ||
1109 | if (i < IOTS_NUM_EXP_MPC) { | |
1110 | /* Splitter input is from GPIO input line */ | |
1111 | s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); | |
1112 | qdev_connect_gpio_out(dev_splitter, 0, | |
1113 | qdev_get_gpio_in_named(dev_secctl, | |
1114 | "mpcexp_status", i)); | |
1115 | } else { | |
1116 | /* Splitter input is from our own MPC */ | |
f0cab7fe PM |
1117 | qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), |
1118 | "irq", 0, | |
bb75e16d PM |
1119 | qdev_get_gpio_in(dev_splitter, 0)); |
1120 | qdev_connect_gpio_out(dev_splitter, 0, | |
1121 | qdev_get_gpio_in_named(dev_secctl, | |
1122 | "mpc_status", 0)); | |
1123 | } | |
1124 | ||
1125 | qdev_connect_gpio_out(dev_splitter, 1, | |
1126 | qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); | |
1127 | } | |
1128 | /* Create GPIO inputs which will pass the line state for our | |
1129 | * mpcexp_irq inputs to the correct splitter devices. | |
1130 | */ | |
13628891 | 1131 | qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", |
bb75e16d PM |
1132 | IOTS_NUM_EXP_MPC); |
1133 | ||
13628891 | 1134 | armsse_forward_sec_resp_cfg(s); |
9e5e54d1 | 1135 | |
132b475a PM |
1136 | /* Forward the MSC related signals */ |
1137 | qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); | |
1138 | qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); | |
1139 | qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); | |
1140 | qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, | |
91c1e9fc | 1141 | armsse_get_common_irq_in(s, 11)); |
132b475a PM |
1142 | |
1143 | /* | |
1144 | * Expose our container region to the board model; this corresponds | |
1145 | * to the AHB Slave Expansion ports which allow bus master devices | |
1146 | * (eg DMA controllers) in the board model to make transactions into | |
93dbd103 | 1147 | * devices in the ARMSSE. |
132b475a PM |
1148 | */ |
1149 | sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); | |
1150 | ||
9e5e54d1 PM |
1151 | system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; |
1152 | } | |
1153 | ||
13628891 | 1154 | static void armsse_idau_check(IDAUInterface *ii, uint32_t address, |
9e5e54d1 PM |
1155 | int *iregion, bool *exempt, bool *ns, bool *nsc) |
1156 | { | |
93dbd103 PM |
1157 | /* |
1158 | * For ARMSSE systems the IDAU responses are simple logical functions | |
9e5e54d1 PM |
1159 | * of the address bits. The NSC attribute is guest-adjustable via the |
1160 | * NSCCFG register in the security controller. | |
1161 | */ | |
93dbd103 | 1162 | ARMSSE *s = ARMSSE(ii); |
9e5e54d1 PM |
1163 | int region = extract32(address, 28, 4); |
1164 | ||
1165 | *ns = !(region & 1); | |
1166 | *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); | |
1167 | /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | |
1168 | *exempt = (address & 0xeff00000) == 0xe0000000; | |
1169 | *iregion = region; | |
1170 | } | |
1171 | ||
13628891 | 1172 | static const VMStateDescription armsse_vmstate = { |
9e5e54d1 PM |
1173 | .name = "iotkit", |
1174 | .version_id = 1, | |
1175 | .minimum_version_id = 1, | |
1176 | .fields = (VMStateField[]) { | |
93dbd103 | 1177 | VMSTATE_UINT32(nsccfg, ARMSSE), |
9e5e54d1 PM |
1178 | VMSTATE_END_OF_LIST() |
1179 | } | |
1180 | }; | |
1181 | ||
13628891 | 1182 | static Property armsse_properties[] = { |
93dbd103 | 1183 | DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, |
9e5e54d1 | 1184 | MemoryRegion *), |
93dbd103 PM |
1185 | DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), |
1186 | DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), | |
4b635cf7 | 1187 | DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), |
9e5e54d1 PM |
1188 | DEFINE_PROP_END_OF_LIST() |
1189 | }; | |
1190 | ||
13628891 | 1191 | static void armsse_reset(DeviceState *dev) |
9e5e54d1 | 1192 | { |
93dbd103 | 1193 | ARMSSE *s = ARMSSE(dev); |
9e5e54d1 PM |
1194 | |
1195 | s->nsccfg = 0; | |
1196 | } | |
1197 | ||
13628891 | 1198 | static void armsse_class_init(ObjectClass *klass, void *data) |
9e5e54d1 PM |
1199 | { |
1200 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1201 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); | |
4c3690b5 | 1202 | ARMSSEClass *asc = ARMSSE_CLASS(klass); |
9e5e54d1 | 1203 | |
13628891 PM |
1204 | dc->realize = armsse_realize; |
1205 | dc->vmsd = &armsse_vmstate; | |
1206 | dc->props = armsse_properties; | |
1207 | dc->reset = armsse_reset; | |
1208 | iic->check = armsse_idau_check; | |
4c3690b5 | 1209 | asc->info = data; |
9e5e54d1 PM |
1210 | } |
1211 | ||
4c3690b5 | 1212 | static const TypeInfo armsse_info = { |
93dbd103 | 1213 | .name = TYPE_ARMSSE, |
9e5e54d1 | 1214 | .parent = TYPE_SYS_BUS_DEVICE, |
93dbd103 | 1215 | .instance_size = sizeof(ARMSSE), |
13628891 | 1216 | .instance_init = armsse_init, |
4c3690b5 | 1217 | .abstract = true, |
9e5e54d1 PM |
1218 | .interfaces = (InterfaceInfo[]) { |
1219 | { TYPE_IDAU_INTERFACE }, | |
1220 | { } | |
1221 | } | |
1222 | }; | |
1223 | ||
4c3690b5 | 1224 | static void armsse_register_types(void) |
9e5e54d1 | 1225 | { |
4c3690b5 PM |
1226 | int i; |
1227 | ||
1228 | type_register_static(&armsse_info); | |
1229 | ||
1230 | for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { | |
1231 | TypeInfo ti = { | |
1232 | .name = armsse_variants[i].name, | |
1233 | .parent = TYPE_ARMSSE, | |
13628891 | 1234 | .class_init = armsse_class_init, |
4c3690b5 PM |
1235 | .class_data = (void *)&armsse_variants[i], |
1236 | }; | |
1237 | type_register(&ti); | |
1238 | } | |
9e5e54d1 PM |
1239 | } |
1240 | ||
4c3690b5 | 1241 | type_init(armsse_register_types); |