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327d8e4e AJ |
1 | /* |
2 | * OpenPOWER Palmetto BMC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
da34e65c | 13 | #include "qapi/error.h" |
4771d756 PB |
14 | #include "qemu-common.h" |
15 | #include "cpu.h" | |
327d8e4e AJ |
16 | #include "exec/address-spaces.h" |
17 | #include "hw/arm/arm.h" | |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
327d8e4e | 19 | #include "hw/boards.h" |
03dd024f | 20 | #include "qemu/log.h" |
e1ad9bc4 CLG |
21 | #include "sysemu/block-backend.h" |
22 | #include "sysemu/blockdev.h" | |
327d8e4e | 23 | |
74fb1f38 | 24 | static struct arm_boot_info aspeed_board_binfo = { |
b033271f | 25 | .board_id = -1, /* device-tree-only board */ |
327d8e4e AJ |
26 | .nb_cpus = 1, |
27 | }; | |
28 | ||
74fb1f38 | 29 | typedef struct AspeedBoardState { |
ff90606f | 30 | AspeedSoCState soc; |
327d8e4e | 31 | MemoryRegion ram; |
74fb1f38 | 32 | } AspeedBoardState; |
327d8e4e | 33 | |
c3ba99f7 CLG |
34 | typedef struct AspeedBoardConfig { |
35 | const char *soc_name; | |
36 | uint32_t hw_strap1; | |
6a0e947b CLG |
37 | const char *fmc_model; |
38 | const char *spi_model; | |
c3ba99f7 CLG |
39 | } AspeedBoardConfig; |
40 | ||
41 | enum { | |
42 | PALMETTO_BMC, | |
9a7c1750 | 43 | AST2500_EVB, |
c3ba99f7 CLG |
44 | }; |
45 | ||
8da33ef7 CLG |
46 | #define PALMETTO_BMC_HW_STRAP1 ( \ |
47 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ | |
48 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ | |
49 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
50 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
51 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
52 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
53 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
54 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
55 | SCU_HW_STRAP_SPI_WIDTH | \ | |
56 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
57 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
58 | ||
9a7c1750 CLG |
59 | #define AST2500_EVB_HW_STRAP1 (( \ |
60 | AST2500_HW_STRAP1_DEFAULTS | \ | |
61 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
62 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
63 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
64 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
65 | SCU_HW_STRAP_MAC1_RGMII | \ | |
66 | SCU_HW_STRAP_MAC0_RGMII) & \ | |
67 | ~SCU_HW_STRAP_2ND_BOOT_WDT) | |
68 | ||
c3ba99f7 | 69 | static const AspeedBoardConfig aspeed_boards[] = { |
6a0e947b CLG |
70 | [PALMETTO_BMC] = { |
71 | .soc_name = "ast2400-a0", | |
72 | .hw_strap1 = PALMETTO_BMC_HW_STRAP1, | |
73 | .fmc_model = "n25q256a", | |
74 | .spi_model = "mx25l25635e", | |
75 | }, | |
76 | [AST2500_EVB] = { | |
77 | .soc_name = "ast2500-a1", | |
78 | .hw_strap1 = AST2500_EVB_HW_STRAP1, | |
79 | .fmc_model = "n25q256a", | |
80 | .spi_model = "mx25l25635e", | |
81 | }, | |
c3ba99f7 CLG |
82 | }; |
83 | ||
74fb1f38 | 84 | static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
e1ad9bc4 CLG |
85 | Error **errp) |
86 | { | |
87 | int i ; | |
88 | ||
89 | for (i = 0; i < s->num_cs; ++i) { | |
90 | AspeedSMCFlash *fl = &s->flashes[i]; | |
91 | DriveInfo *dinfo = drive_get_next(IF_MTD); | |
92 | qemu_irq cs_line; | |
93 | ||
94 | /* | |
95 | * FIXME: check that we are not using a flash module exceeding | |
96 | * the controller segment size | |
97 | */ | |
98 | fl->flash = ssi_create_slave_no_init(s->spi, flashtype); | |
99 | if (dinfo) { | |
100 | qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), | |
101 | errp); | |
102 | } | |
103 | qdev_init_nofail(fl->flash); | |
104 | ||
105 | cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); | |
106 | sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); | |
107 | } | |
108 | } | |
109 | ||
c3ba99f7 CLG |
110 | static void aspeed_board_init(MachineState *machine, |
111 | const AspeedBoardConfig *cfg) | |
327d8e4e | 112 | { |
74fb1f38 | 113 | AspeedBoardState *bmc; |
b033271f | 114 | AspeedSoCClass *sc; |
327d8e4e | 115 | |
74fb1f38 | 116 | bmc = g_new0(AspeedBoardState, 1); |
c3ba99f7 | 117 | object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name); |
327d8e4e AJ |
118 | object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc), |
119 | &error_abort); | |
120 | ||
b033271f CLG |
121 | sc = ASPEED_SOC_GET_CLASS(&bmc->soc); |
122 | ||
c6c7cfb0 CLG |
123 | object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size", |
124 | &error_abort); | |
c3ba99f7 | 125 | object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", |
87e79af0 | 126 | &error_abort); |
327d8e4e AJ |
127 | object_property_set_bool(OBJECT(&bmc->soc), true, "realized", |
128 | &error_abort); | |
129 | ||
de46f5f4 CLG |
130 | /* |
131 | * Allocate RAM after the memory controller has checked the size | |
132 | * was valid. If not, a default value is used. | |
133 | */ | |
134 | ram_size = object_property_get_int(OBJECT(&bmc->soc), "ram-size", | |
135 | &error_abort); | |
136 | ||
137 | memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); | |
138 | memory_region_add_subregion(get_system_memory(), sc->info->sdram_base, | |
139 | &bmc->ram); | |
140 | object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), | |
141 | &error_abort); | |
142 | ||
6a0e947b CLG |
143 | aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); |
144 | aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); | |
74fb1f38 CLG |
145 | |
146 | aspeed_board_binfo.kernel_filename = machine->kernel_filename; | |
147 | aspeed_board_binfo.initrd_filename = machine->initrd_filename; | |
148 | aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline; | |
149 | aspeed_board_binfo.ram_size = ram_size; | |
150 | aspeed_board_binfo.loader_start = sc->info->sdram_base; | |
e1ad9bc4 | 151 | |
74fb1f38 CLG |
152 | arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); |
153 | } | |
b033271f | 154 | |
74fb1f38 CLG |
155 | static void palmetto_bmc_init(MachineState *machine) |
156 | { | |
c3ba99f7 | 157 | aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]); |
327d8e4e AJ |
158 | } |
159 | ||
74fb1f38 | 160 | static void palmetto_bmc_class_init(ObjectClass *oc, void *data) |
327d8e4e | 161 | { |
74fb1f38 CLG |
162 | MachineClass *mc = MACHINE_CLASS(oc); |
163 | ||
164 | mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; | |
327d8e4e AJ |
165 | mc->init = palmetto_bmc_init; |
166 | mc->max_cpus = 1; | |
167 | mc->no_sdcard = 1; | |
168 | mc->no_floppy = 1; | |
169 | mc->no_cdrom = 1; | |
327d8e4e AJ |
170 | mc->no_parallel = 1; |
171 | } | |
172 | ||
74fb1f38 CLG |
173 | static const TypeInfo palmetto_bmc_type = { |
174 | .name = MACHINE_TYPE_NAME("palmetto-bmc"), | |
175 | .parent = TYPE_MACHINE, | |
176 | .class_init = palmetto_bmc_class_init, | |
177 | }; | |
178 | ||
9a7c1750 CLG |
179 | static void ast2500_evb_init(MachineState *machine) |
180 | { | |
181 | aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]); | |
182 | } | |
183 | ||
184 | static void ast2500_evb_class_init(ObjectClass *oc, void *data) | |
185 | { | |
186 | MachineClass *mc = MACHINE_CLASS(oc); | |
187 | ||
188 | mc->desc = "Aspeed AST2500 EVB (ARM1176)"; | |
189 | mc->init = ast2500_evb_init; | |
190 | mc->max_cpus = 1; | |
191 | mc->no_sdcard = 1; | |
192 | mc->no_floppy = 1; | |
193 | mc->no_cdrom = 1; | |
194 | mc->no_parallel = 1; | |
195 | } | |
196 | ||
197 | static const TypeInfo ast2500_evb_type = { | |
198 | .name = MACHINE_TYPE_NAME("ast2500-evb"), | |
199 | .parent = TYPE_MACHINE, | |
200 | .class_init = ast2500_evb_class_init, | |
201 | }; | |
202 | ||
74fb1f38 CLG |
203 | static void aspeed_machine_init(void) |
204 | { | |
205 | type_register_static(&palmetto_bmc_type); | |
9a7c1750 | 206 | type_register_static(&ast2500_evb_type); |
74fb1f38 CLG |
207 | } |
208 | ||
209 | type_init(aspeed_machine_init) |