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356b230e SL |
1 | /* |
2 | * ASPEED Ast10x0 SoC | |
3 | * | |
4 | * Copyright (C) 2022 ASPEED Technology Inc. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | * Implementation extracted from the AST2600 and adapted for Ast10x0. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
13 | #include "qapi/error.h" | |
14 | #include "exec/address-spaces.h" | |
15 | #include "sysemu/sysemu.h" | |
16 | #include "hw/qdev-clock.h" | |
17 | #include "hw/misc/unimp.h" | |
356b230e SL |
18 | #include "hw/arm/aspeed_soc.h" |
19 | ||
20 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
21 | ||
22 | static const hwaddr aspeed_soc_ast1030_memmap[] = { | |
23 | [ASPEED_DEV_SRAM] = 0x00000000, | |
24 | [ASPEED_DEV_SBC] = 0x79000000, | |
25 | [ASPEED_DEV_IOMEM] = 0x7E600000, | |
26 | [ASPEED_DEV_PWM] = 0x7E610000, | |
27 | [ASPEED_DEV_FMC] = 0x7E620000, | |
28 | [ASPEED_DEV_SPI1] = 0x7E630000, | |
29 | [ASPEED_DEV_SPI2] = 0x7E640000, | |
30 | [ASPEED_DEV_SCU] = 0x7E6E2000, | |
31 | [ASPEED_DEV_ADC] = 0x7E6E9000, | |
32 | [ASPEED_DEV_SBC] = 0x7E6F2000, | |
33 | [ASPEED_DEV_GPIO] = 0x7E780000, | |
34 | [ASPEED_DEV_TIMER1] = 0x7E782000, | |
ab5e8605 PD |
35 | [ASPEED_DEV_UART1] = 0x7E783000, |
36 | [ASPEED_DEV_UART2] = 0x7E78D000, | |
37 | [ASPEED_DEV_UART3] = 0x7E78E000, | |
38 | [ASPEED_DEV_UART4] = 0x7E78F000, | |
356b230e | 39 | [ASPEED_DEV_UART5] = 0x7E784000, |
ab5e8605 PD |
40 | [ASPEED_DEV_UART6] = 0x7E790000, |
41 | [ASPEED_DEV_UART7] = 0x7E790100, | |
42 | [ASPEED_DEV_UART8] = 0x7E790200, | |
43 | [ASPEED_DEV_UART9] = 0x7E790300, | |
44 | [ASPEED_DEV_UART10] = 0x7E790400, | |
45 | [ASPEED_DEV_UART11] = 0x7E790500, | |
46 | [ASPEED_DEV_UART12] = 0x7E790600, | |
47 | [ASPEED_DEV_UART13] = 0x7E790700, | |
356b230e SL |
48 | [ASPEED_DEV_WDT] = 0x7E785000, |
49 | [ASPEED_DEV_LPC] = 0x7E789000, | |
50 | [ASPEED_DEV_I2C] = 0x7E7B0000, | |
51 | }; | |
52 | ||
53 | static const int aspeed_soc_ast1030_irqmap[] = { | |
ab5e8605 PD |
54 | [ASPEED_DEV_UART1] = 47, |
55 | [ASPEED_DEV_UART2] = 48, | |
56 | [ASPEED_DEV_UART3] = 49, | |
57 | [ASPEED_DEV_UART4] = 50, | |
356b230e | 58 | [ASPEED_DEV_UART5] = 8, |
ab5e8605 PD |
59 | [ASPEED_DEV_UART6] = 57, |
60 | [ASPEED_DEV_UART7] = 58, | |
61 | [ASPEED_DEV_UART8] = 59, | |
62 | [ASPEED_DEV_UART9] = 60, | |
63 | [ASPEED_DEV_UART10] = 61, | |
64 | [ASPEED_DEV_UART11] = 62, | |
65 | [ASPEED_DEV_UART12] = 63, | |
66 | [ASPEED_DEV_UART13] = 64, | |
356b230e SL |
67 | [ASPEED_DEV_GPIO] = 11, |
68 | [ASPEED_DEV_TIMER1] = 16, | |
69 | [ASPEED_DEV_TIMER2] = 17, | |
70 | [ASPEED_DEV_TIMER3] = 18, | |
71 | [ASPEED_DEV_TIMER4] = 19, | |
72 | [ASPEED_DEV_TIMER5] = 20, | |
73 | [ASPEED_DEV_TIMER6] = 21, | |
74 | [ASPEED_DEV_TIMER7] = 22, | |
75 | [ASPEED_DEV_TIMER8] = 23, | |
76 | [ASPEED_DEV_WDT] = 24, | |
77 | [ASPEED_DEV_LPC] = 35, | |
78 | [ASPEED_DEV_FMC] = 39, | |
79 | [ASPEED_DEV_PWM] = 44, | |
80 | [ASPEED_DEV_ADC] = 46, | |
81 | [ASPEED_DEV_SPI1] = 65, | |
82 | [ASPEED_DEV_SPI2] = 66, | |
83 | [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ | |
84 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ | |
85 | }; | |
86 | ||
699db715 | 87 | static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) |
356b230e SL |
88 | { |
89 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
90 | ||
699db715 | 91 | return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); |
356b230e SL |
92 | } |
93 | ||
94 | static void aspeed_soc_ast1030_init(Object *obj) | |
95 | { | |
96 | AspeedSoCState *s = ASPEED_SOC(obj); | |
97 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
98 | char socname[8]; | |
99 | char typename[64]; | |
100 | int i; | |
101 | ||
102 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
103 | g_assert_not_reached(); | |
104 | } | |
105 | ||
106 | object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); | |
107 | ||
108 | s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); | |
109 | ||
110 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
111 | object_initialize_child(obj, "scu", &s->scu, typename); | |
112 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); | |
113 | ||
114 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); | |
115 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); | |
116 | ||
4c70ab16 TL |
117 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
118 | object_initialize_child(obj, "i2c", &s->i2c, typename); | |
119 | ||
356b230e SL |
120 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
121 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); | |
122 | ||
123 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); | |
124 | object_initialize_child(obj, "adc", &s->adc, typename); | |
125 | ||
126 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
127 | object_initialize_child(obj, "fmc", &s->fmc, typename); | |
128 | ||
129 | for (i = 0; i < sc->spis_num; i++) { | |
130 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
131 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); | |
132 | } | |
133 | ||
134 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
135 | ||
136 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); | |
137 | ||
138 | for (i = 0; i < sc->wdts_num; i++) { | |
139 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
140 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); | |
141 | } | |
17075ef2 JL |
142 | |
143 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
144 | object_initialize_child(obj, "gpio", &s->gpio, typename); | |
356b230e SL |
145 | } |
146 | ||
147 | static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | |
148 | { | |
149 | AspeedSoCState *s = ASPEED_SOC(dev_soc); | |
150 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
151 | MemoryRegion *system_memory = get_system_memory(); | |
152 | DeviceState *armv7m; | |
153 | Error *err = NULL; | |
154 | int i; | |
155 | ||
156 | if (!clock_has_source(s->sysclk)) { | |
157 | error_setg(errp, "sysclk clock must be wired up by the board code"); | |
158 | return; | |
159 | } | |
160 | ||
161 | /* General I/O memory space to catch all unimplemented device */ | |
162 | create_unimplemented_device("aspeed.sbc", | |
163 | sc->memmap[ASPEED_DEV_SBC], | |
164 | 0x40000); | |
165 | create_unimplemented_device("aspeed.io", | |
166 | sc->memmap[ASPEED_DEV_IOMEM], | |
167 | ASPEED_SOC_IOMEM_SIZE); | |
168 | ||
169 | /* AST1030 CPU Core */ | |
170 | armv7m = DEVICE(&s->armv7m); | |
171 | qdev_prop_set_uint32(armv7m, "num-irq", 256); | |
172 | qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); | |
173 | qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); | |
174 | object_property_set_link(OBJECT(&s->armv7m), "memory", | |
175 | OBJECT(system_memory), &error_abort); | |
176 | sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); | |
177 | ||
178 | /* Internal SRAM */ | |
179 | memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err); | |
180 | if (err != NULL) { | |
181 | error_propagate(errp, err); | |
182 | return; | |
183 | } | |
184 | memory_region_add_subregion(system_memory, | |
185 | sc->memmap[ASPEED_DEV_SRAM], | |
186 | &s->sram); | |
187 | ||
188 | /* SCU */ | |
189 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { | |
190 | return; | |
191 | } | |
192 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); | |
193 | ||
4c70ab16 TL |
194 | /* I2C */ |
195 | ||
196 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), | |
197 | &error_abort); | |
198 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { | |
199 | return; | |
200 | } | |
201 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); | |
202 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { | |
203 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), | |
204 | sc->irqmap[ASPEED_DEV_I2C] + i); | |
205 | /* The AST1030 I2C controller has one IRQ per bus. */ | |
206 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
207 | } | |
208 | ||
356b230e SL |
209 | /* LPC */ |
210 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
211 | return; | |
212 | } | |
213 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
214 | ||
215 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
216 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, | |
217 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
218 | ||
219 | /* | |
220 | * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. | |
221 | */ | |
222 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
223 | qdev_get_gpio_in(DEVICE(&s->armv7m), | |
224 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | |
225 | ||
226 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
227 | qdev_get_gpio_in(DEVICE(&s->armv7m), | |
228 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | |
229 | ||
230 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
231 | qdev_get_gpio_in(DEVICE(&s->armv7m), | |
232 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | |
233 | ||
234 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
235 | qdev_get_gpio_in(DEVICE(&s->armv7m), | |
236 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | |
237 | ||
470253b6 PD |
238 | /* UART */ |
239 | aspeed_soc_uart_init(s); | |
356b230e SL |
240 | |
241 | /* Timer */ | |
242 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), | |
243 | &error_abort); | |
244 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { | |
245 | return; | |
246 | } | |
247 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | |
248 | sc->memmap[ASPEED_DEV_TIMER1]); | |
249 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | |
250 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); | |
251 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
252 | } | |
253 | ||
254 | /* ADC */ | |
255 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
256 | return; | |
257 | } | |
258 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); | |
259 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | |
260 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
261 | ||
262 | /* FMC, The number of CS is set at the board level */ | |
263 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), | |
264 | &error_abort); | |
265 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { | |
266 | return; | |
267 | } | |
268 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); | |
269 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, | |
270 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); | |
271 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | |
272 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); | |
273 | ||
274 | /* SPI */ | |
275 | for (i = 0; i < sc->spis_num; i++) { | |
276 | object_property_set_link(OBJECT(&s->spi[i]), "dram", | |
277 | OBJECT(&s->sram), &error_abort); | |
278 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { | |
279 | return; | |
280 | } | |
281 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
282 | sc->memmap[ASPEED_DEV_SPI1 + i]); | |
283 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | |
284 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); | |
285 | } | |
286 | ||
287 | /* Secure Boot Controller */ | |
288 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { | |
289 | return; | |
290 | } | |
291 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); | |
292 | ||
293 | /* Watch dog */ | |
294 | for (i = 0; i < sc->wdts_num; i++) { | |
295 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
296 | ||
297 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), | |
298 | &error_abort); | |
299 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { | |
300 | return; | |
301 | } | |
302 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
303 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); | |
304 | } | |
17075ef2 JL |
305 | |
306 | /* GPIO */ | |
307 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { | |
308 | return; | |
309 | } | |
310 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); | |
311 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | |
312 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); | |
356b230e SL |
313 | } |
314 | ||
315 | static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) | |
316 | { | |
317 | DeviceClass *dc = DEVICE_CLASS(klass); | |
318 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); | |
319 | ||
320 | dc->realize = aspeed_soc_ast1030_realize; | |
321 | ||
322 | sc->name = "ast1030-a1"; | |
323 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); | |
324 | sc->silicon_rev = AST1030_A1_SILICON_REV; | |
325 | sc->sram_size = 0xc0000; | |
326 | sc->spis_num = 2; | |
327 | sc->ehcis_num = 0; | |
328 | sc->wdts_num = 4; | |
329 | sc->macs_num = 1; | |
c5e1bdb9 | 330 | sc->uarts_num = 13; |
356b230e SL |
331 | sc->irqmap = aspeed_soc_ast1030_irqmap; |
332 | sc->memmap = aspeed_soc_ast1030_memmap; | |
333 | sc->num_cpus = 1; | |
699db715 | 334 | sc->get_irq = aspeed_soc_ast1030_get_irq; |
356b230e SL |
335 | } |
336 | ||
337 | static const TypeInfo aspeed_soc_ast1030_type_info = { | |
338 | .name = "ast1030-a1", | |
339 | .parent = TYPE_ASPEED_SOC, | |
340 | .instance_size = sizeof(AspeedSoCState), | |
341 | .instance_init = aspeed_soc_ast1030_init, | |
342 | .class_init = aspeed_soc_ast1030_class_init, | |
343 | .class_size = sizeof(AspeedSoCClass), | |
344 | }; | |
345 | ||
346 | static void aspeed_soc_register_types(void) | |
347 | { | |
348 | type_register_static(&aspeed_soc_ast1030_type_info); | |
349 | } | |
350 | ||
351 | type_init(aspeed_soc_register_types) |