[mirror_qemu.git] / hw / arm / aspeed_ast2600.c

/*
 * ASPEED SoC 2600 family
 *
 * Copyright (c) 2016-2019, IBM Corporation.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"

#define ASPEED_SOC_IOMEM_SIZE       0x00200000

static const hwaddr aspeed_soc_ast2600_memmap[] = {
    [ASPEED_SRAM]      = 0x10000000,
    /* 0x16000000     0x17FFFFFF : AHB BUS do LPC Bus bridge */
    [ASPEED_IOMEM]     = 0x1E600000,
    [ASPEED_PWM]       = 0x1E610000,
    [ASPEED_FMC]       = 0x1E620000,
    [ASPEED_SPI1]      = 0x1E630000,
    [ASPEED_SPI2]      = 0x1E641000,
    [ASPEED_EHCI1]     = 0x1E6A1000,
    [ASPEED_EHCI2]     = 0x1E6A3000,
    [ASPEED_MII1]      = 0x1E650000,
    [ASPEED_MII2]      = 0x1E650008,
    [ASPEED_MII3]      = 0x1E650010,
    [ASPEED_MII4]      = 0x1E650018,
    [ASPEED_ETH1]      = 0x1E660000,
    [ASPEED_ETH3]      = 0x1E670000,
    [ASPEED_ETH2]      = 0x1E680000,
    [ASPEED_ETH4]      = 0x1E690000,
    [ASPEED_VIC]       = 0x1E6C0000,
    [ASPEED_SDMC]      = 0x1E6E0000,
    [ASPEED_SCU]       = 0x1E6E2000,
    [ASPEED_XDMA]      = 0x1E6E7000,
    [ASPEED_ADC]       = 0x1E6E9000,
    [ASPEED_VIDEO]     = 0x1E700000,
    [ASPEED_SDHCI]     = 0x1E740000,
    [ASPEED_EMMC]      = 0x1E750000,
    [ASPEED_GPIO]      = 0x1E780000,
    [ASPEED_GPIO_1_8V] = 0x1E780800,
    [ASPEED_RTC]       = 0x1E781000,
    [ASPEED_TIMER1]    = 0x1E782000,
    [ASPEED_WDT]       = 0x1E785000,
    [ASPEED_LPC]       = 0x1E789000,
    [ASPEED_IBT]       = 0x1E789140,
    [ASPEED_I2C]       = 0x1E78A000,
    [ASPEED_UART1]     = 0x1E783000,
    [ASPEED_UART5]     = 0x1E784000,
    [ASPEED_VUART]     = 0x1E787000,
    [ASPEED_SDRAM]     = 0x80000000,
};

#define ASPEED_A7MPCORE_ADDR 0x40460000

#define ASPEED_SOC_AST2600_MAX_IRQ 128

/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
    [ASPEED_UART1]     = 47,
    [ASPEED_UART2]     = 48,
    [ASPEED_UART3]     = 49,
    [ASPEED_UART4]     = 50,
    [ASPEED_UART5]     = 8,
    [ASPEED_VUART]     = 8,
    [ASPEED_FMC]       = 39,
    [ASPEED_SDMC]      = 0,
    [ASPEED_SCU]       = 12,
    [ASPEED_ADC]       = 78,
    [ASPEED_XDMA]      = 6,
    [ASPEED_SDHCI]     = 43,
    [ASPEED_EHCI1]     = 5,
    [ASPEED_EHCI2]     = 9,
    [ASPEED_EMMC]      = 15,
    [ASPEED_GPIO]      = 40,
    [ASPEED_GPIO_1_8V] = 11,
    [ASPEED_RTC]       = 13,
    [ASPEED_TIMER1]    = 16,
    [ASPEED_TIMER2]    = 17,
    [ASPEED_TIMER3]    = 18,
    [ASPEED_TIMER4]    = 19,
    [ASPEED_TIMER5]    = 20,
    [ASPEED_TIMER6]    = 21,
    [ASPEED_TIMER7]    = 22,
    [ASPEED_TIMER8]    = 23,
    [ASPEED_WDT]       = 24,
    [ASPEED_PWM]       = 44,
    [ASPEED_LPC]       = 35,
    [ASPEED_IBT]       = 35,    /* LPC */
    [ASPEED_I2C]       = 110,   /* 110 -> 125 */
    [ASPEED_ETH1]      = 2,
    [ASPEED_ETH2]      = 3,
    [ASPEED_ETH3]      = 32,
    [ASPEED_ETH4]      = 33,

};

static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
{
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
}

static void aspeed_soc_ast2600_init(Object *obj)
{
    AspeedSoCState *s = ASPEED_SOC(obj);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int i;
    char socname[8];
    char typename[64];

    if (sscanf(sc->name, "%7s", socname) != 1) {
        g_assert_not_reached();
    }

    for (i = 0; i < sc->num_cpus; i++) {
        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
    }

    snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
    sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), typename);
    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
                         sc->silicon_rev);
    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                              "hw-strap1");
    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
                              "hw-strap2");
    object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                              "hw-prot-key");

    sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
                          sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);

    sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
                          TYPE_ASPEED_RTC);

    snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
    sysbus_init_child_obj(obj, "timerctrl", &s->timerctrl,
                          sizeof(s->timerctrl), typename);

    snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
    sysbus_init_child_obj(obj, "i2c", &s->i2c, sizeof(s->i2c), typename);

    snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
    sysbus_init_child_obj(obj, "fmc", &s->fmc, sizeof(s->fmc), typename);
    object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");

    for (i = 0; i < sc->spis_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
        sysbus_init_child_obj(obj, "spi[*]", &s->spi[i],
                              sizeof(s->spi[i]), typename);
    }

    for (i = 0; i < sc->ehcis_num; i++) {
        sysbus_init_child_obj(obj, "ehci[*]", &s->ehci[i],
                              sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
    }

    snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
    sysbus_init_child_obj(obj, "sdmc", &s->sdmc, sizeof(s->sdmc), typename);
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                              "ram-size");
    object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
                              "max-ram-size");

    for (i = 0; i < sc->wdts_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
        sysbus_init_child_obj(obj, "wdt[*]", &s->wdt[i],
                              sizeof(s->wdt[i]), typename);
    }

    for (i = 0; i < sc->macs_num; i++) {
        sysbus_init_child_obj(obj, "ftgmac100[*]", &s->ftgmac100[i],
                              sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);

        sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
                              TYPE_ASPEED_MII);
    }

    sysbus_init_child_obj(obj, "xdma", &s->xdma, sizeof(s->xdma),
                          TYPE_ASPEED_XDMA);

    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
    sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), typename);

    snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
    sysbus_init_child_obj(obj, "gpio_1_8v", &s->gpio_1_8v,
                          sizeof(s->gpio_1_8v), typename);

    sysbus_init_child_obj(obj, "sd-controller", &s->sdhci,
                          sizeof(s->sdhci), TYPE_ASPEED_SDHCI);

    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);

    /* Init sd card slot class here so that they're under the correct parent */
    for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
        sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
                              &s->sdhci.slots[i],
                              sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
    }

    sysbus_init_child_obj(obj, "emmc-controller", &s->emmc,
                          sizeof(s->emmc), TYPE_ASPEED_SDHCI);

    object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);

    sysbus_init_child_obj(obj, "emmc-controller.sdhci",
                          &s->emmc.slots[0], sizeof(s->emmc.slots[0]),
                          TYPE_SYSBUS_SDHCI);
}

/*
 * ASPEED ast2600 has 0xf as cluster ID
 *
 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
 */
static uint64_t aspeed_calc_affinity(int cpu)
{
    return (0xf << ARM_AFF1_SHIFT) | cpu;
}

static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
{
    int i;
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    Error *err = NULL, *local_err = NULL;
    qemu_irq irq;

    /* IO space */
    create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
                                ASPEED_SOC_IOMEM_SIZE);

    /* Video engine stub */
    create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
                                0x1000);

    /* CPU */
    for (i = 0; i < sc->num_cpus; i++) {
        object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);
        if (sc->num_cpus > 1) {
            object_property_set_int(OBJECT(&s->cpu[i]),
                                    ASPEED_A7MPCORE_ADDR,
                                    "reset-cbar", &error_abort);
        }
        object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
                                "mp-affinity", &error_abort);

        object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
                                &error_abort);

        /*
         * TODO: the secondary CPUs are started and a boot helper
         * is needed when using -kernel
         */

        object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    /* A7MPCORE */
    object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu",
                            &error_abort);
    object_property_set_int(OBJECT(&s->a7mpcore),
                            ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
                            "num-irq", &error_abort);

    object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
                             &error_abort);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);

    for (i = 0; i < sc->num_cpus; i++) {
        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
        DeviceState  *d   = DEVICE(qemu_get_cpu(i));

        irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
        sysbus_connect_irq(sbd, i, irq);
        irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
        sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
        irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
        sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
        irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
        sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
    }

    /* SRAM */
    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
                           sc->sram_size, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(),
                                sc->memmap[ASPEED_SRAM], &s->sram);

    /* SCU */
    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);

    /* RTC */
    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
                       aspeed_soc_get_irq(s, ASPEED_RTC));

    /* Timer */
    object_property_set_link(OBJECT(&s->timerctrl),
                             OBJECT(&s->scu), "scu", &error_abort);
    object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
                    sc->memmap[ASPEED_TIMER1]);
    for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
        qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
    }

    /* UART - attach an 8250 to the IO space as our UART5 */
    if (serial_hd(0)) {
        qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
        serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
                       uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
    }

    /* I2C */
    object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
    for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                        sc->irqmap[ASPEED_I2C] + i);
        /*
         * The AST2600 SoC has one IRQ per I2C bus. Skip the common
         * IRQ (AST2400 and AST2500) and connect all bussses.
         */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
    }

    /* FMC, The number of CS is set at the board level */
    object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
                            "sdram-base", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
                    s->fmc.ctrl->flash_window_base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
                       aspeed_soc_get_irq(s, ASPEED_FMC));

    /* SPI */
    for (i = 0; i < sc->spis_num; i++) {
        object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr),
                                 "dram", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
                        sc->memmap[ASPEED_SPI1 + i]);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
                        s->spi[i].ctrl->flash_window_base);
    }

    /* EHCI */
    for (i = 0; i < sc->ehcis_num; i++) {
        object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                        sc->memmap[ASPEED_EHCI1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
    }

    /* SDMC - SDRAM Memory Controller */
    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);

    /* Watch dog */
    for (i = 0; i < sc->wdts_num; i++) {
        AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);

        object_property_set_link(OBJECT(&s->wdt[i]),
                                 OBJECT(&s->scu), "scu", &error_abort);
        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
                        sc->memmap[ASPEED_WDT] + i * awc->offset);
    }

    /* Net */
    for (i = 0; i < sc->macs_num; i++) {
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
                                 &err);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
           return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                        sc->memmap[ASPEED_ETH1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_ETH1 + i));

        object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
                                 "nic", &error_abort);
        object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
                        sc->memmap[ASPEED_MII1 + i]);
    }

    /* XDMA */
    object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
                    sc->memmap[ASPEED_XDMA]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
                       aspeed_soc_get_irq(s, ASPEED_XDMA));

    /* GPIO */
    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                       aspeed_soc_get_irq(s, ASPEED_GPIO));

    object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
                    sc->memmap[ASPEED_GPIO_1_8V]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
                       aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));

    /* SDHCI */
    object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
                    sc->memmap[ASPEED_SDHCI]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                       aspeed_soc_get_irq(s, ASPEED_SDHCI));

    /* eMMC */
    object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
                       aspeed_soc_get_irq(s, ASPEED_EMMC));
}

static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    dc->realize      = aspeed_soc_ast2600_realize;

    sc->name         = "ast2600-a1";
    sc->cpu_type     = ARM_CPU_TYPE_NAME("cortex-a7");
    sc->silicon_rev  = AST2600_A1_SILICON_REV;
    sc->sram_size    = 0x10000;
    sc->spis_num     = 2;
    sc->ehcis_num    = 2;
    sc->wdts_num     = 4;
    sc->macs_num     = 4;
    sc->irqmap       = aspeed_soc_ast2600_irqmap;
    sc->memmap       = aspeed_soc_ast2600_memmap;
    sc->num_cpus     = 2;
}

static const TypeInfo aspeed_soc_ast2600_type_info = {
    .name           = "ast2600-a1",
    .parent         = TYPE_ASPEED_SOC,
    .instance_size  = sizeof(AspeedSoCState),
    .instance_init  = aspeed_soc_ast2600_init,
    .class_init     = aspeed_soc_ast2600_class_init,
    .class_size     = sizeof(AspeedSoCClass),
};

static void aspeed_soc_register_types(void)
{
    type_register_static(&aspeed_soc_ast2600_type_info);
};

type_init(aspeed_soc_register_types)
Commit	Line	Data
f25c0ae1 CLG	1	/*
	2	* ASPEED SoC 2600 family
	3	*
	4	* Copyright (c) 2016-2019, IBM Corporation.
	5	*
	6	* This code is licensed under the GPL version 2 or later. See
	7	* the COPYING file in the top-level directory.
	8	*/
	9
	10	#include "qemu/osdep.h"
	11	#include "qapi/error.h"
	12	#include "cpu.h"
	13	#include "exec/address-spaces.h"
	14	#include "hw/misc/unimp.h"
	15	#include "hw/arm/aspeed_soc.h"
	16	#include "hw/char/serial.h"
	17	#include "qemu/log.h"
	18	#include "qemu/module.h"
	19	#include "qemu/error-report.h"
	20	#include "hw/i2c/aspeed_i2c.h"
	21	#include "net/net.h"
	22	#include "sysemu/sysemu.h"
	23
	24	#define ASPEED_SOC_IOMEM_SIZE 0x00200000
	25
	26	static const hwaddr aspeed_soc_ast2600_memmap[] = {
	27	[ASPEED_SRAM] = 0x10000000,
	28	/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
	29	[ASPEED_IOMEM] = 0x1E600000,
	30	[ASPEED_PWM] = 0x1E610000,
	31	[ASPEED_FMC] = 0x1E620000,
	32	[ASPEED_SPI1] = 0x1E630000,
	33	[ASPEED_SPI2] = 0x1E641000,
917940ce GR	34	[ASPEED_EHCI1] = 0x1E6A1000,
917940ce GR	35	[ASPEED_EHCI2] = 0x1E6A3000,
289251b0 CLG	36	[ASPEED_MII1] = 0x1E650000,
	37	[ASPEED_MII2] = 0x1E650008,
	38	[ASPEED_MII3] = 0x1E650010,
	39	[ASPEED_MII4] = 0x1E650018,
f25c0ae1	40	[ASPEED_ETH1] = 0x1E660000,
d300db02	41	[ASPEED_ETH3] = 0x1E670000,
f25c0ae1	42	[ASPEED_ETH2] = 0x1E680000,
d300db02	43	[ASPEED_ETH4] = 0x1E690000,
f25c0ae1 CLG	44	[ASPEED_VIC] = 0x1E6C0000,
	45	[ASPEED_SDMC] = 0x1E6E0000,
	46	[ASPEED_SCU] = 0x1E6E2000,
	47	[ASPEED_XDMA] = 0x1E6E7000,
	48	[ASPEED_ADC] = 0x1E6E9000,
514bcf6f	49	[ASPEED_VIDEO] = 0x1E700000,
f25c0ae1	50	[ASPEED_SDHCI] = 0x1E740000,
a29e3e12	51	[ASPEED_EMMC] = 0x1E750000,
f25c0ae1 CLG	52	[ASPEED_GPIO] = 0x1E780000,
	53	[ASPEED_GPIO_1_8V] = 0x1E780800,
	54	[ASPEED_RTC] = 0x1E781000,
	55	[ASPEED_TIMER1] = 0x1E782000,
	56	[ASPEED_WDT] = 0x1E785000,
	57	[ASPEED_LPC] = 0x1E789000,
	58	[ASPEED_IBT] = 0x1E789140,
	59	[ASPEED_I2C] = 0x1E78A000,
	60	[ASPEED_UART1] = 0x1E783000,
	61	[ASPEED_UART5] = 0x1E784000,
	62	[ASPEED_VUART] = 0x1E787000,
	63	[ASPEED_SDRAM] = 0x80000000,
	64	};
	65
	66	#define ASPEED_A7MPCORE_ADDR 0x40460000
	67
	68	#define ASPEED_SOC_AST2600_MAX_IRQ 128
	69
a29e3e12	70	/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
f25c0ae1 CLG	71	static const int aspeed_soc_ast2600_irqmap[] = {
	72	[ASPEED_UART1] = 47,
	73	[ASPEED_UART2] = 48,
	74	[ASPEED_UART3] = 49,
	75	[ASPEED_UART4] = 50,
	76	[ASPEED_UART5] = 8,
	77	[ASPEED_VUART] = 8,
	78	[ASPEED_FMC] = 39,
	79	[ASPEED_SDMC] = 0,
	80	[ASPEED_SCU] = 12,
	81	[ASPEED_ADC] = 78,
	82	[ASPEED_XDMA] = 6,
	83	[ASPEED_SDHCI] = 43,
917940ce GR	84	[ASPEED_EHCI1] = 5,
917940ce GR	85	[ASPEED_EHCI2] = 9,
a29e3e12	86	[ASPEED_EMMC] = 15,
f25c0ae1 CLG	87	[ASPEED_GPIO] = 40,
	88	[ASPEED_GPIO_1_8V] = 11,
	89	[ASPEED_RTC] = 13,
	90	[ASPEED_TIMER1] = 16,
	91	[ASPEED_TIMER2] = 17,
	92	[ASPEED_TIMER3] = 18,
	93	[ASPEED_TIMER4] = 19,
	94	[ASPEED_TIMER5] = 20,
	95	[ASPEED_TIMER6] = 21,
	96	[ASPEED_TIMER7] = 22,
	97	[ASPEED_TIMER8] = 23,
	98	[ASPEED_WDT] = 24,
	99	[ASPEED_PWM] = 44,
	100	[ASPEED_LPC] = 35,
	101	[ASPEED_IBT] = 35, /* LPC */
	102	[ASPEED_I2C] = 110, /* 110 -> 125 */
	103	[ASPEED_ETH1] = 2,
	104	[ASPEED_ETH2] = 3,
d300db02 JS	105	[ASPEED_ETH3] = 32,
	106	[ASPEED_ETH4] = 33,
	107
f25c0ae1 CLG	108	};
	109
	110	static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
	111	{
	112	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	113
	114	return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
	115	}
	116
	117	static void aspeed_soc_ast2600_init(Object *obj)
	118	{
	119	AspeedSoCState *s = ASPEED_SOC(obj);
	120	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	121	int i;
	122	char socname[8];
	123	char typename[64];
	124
	125	if (sscanf(sc->name, "%7s", socname) != 1) {
	126	g_assert_not_reached();
	127	}
	128
	129	for (i = 0; i < sc->num_cpus; i++) {
9fc7fc4d	130	object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
f25c0ae1 CLG	131	}
	132
	133	snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
9bdee7f4	134	sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), typename);
f25c0ae1 CLG	135	qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
	136	sc->silicon_rev);
	137	object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
d2623129	138	"hw-strap1");
f25c0ae1	139	object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
d2623129	140	"hw-strap2");
f25c0ae1	141	object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
d2623129	142	"hw-prot-key");
f25c0ae1 CLG	143
	144	sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
	145	sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
	146
9bdee7f4	147	sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
f25c0ae1 CLG	148	TYPE_ASPEED_RTC);
	149
	150	snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
9bdee7f4	151	sysbus_init_child_obj(obj, "timerctrl", &s->timerctrl,
f25c0ae1	152	sizeof(s->timerctrl), typename);
f25c0ae1 CLG	153
f25c0ae1 CLG	154	snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
9bdee7f4	155	sysbus_init_child_obj(obj, "i2c", &s->i2c, sizeof(s->i2c), typename);
f25c0ae1 CLG	156
f25c0ae1 CLG	157	snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
9bdee7f4	158	sysbus_init_child_obj(obj, "fmc", &s->fmc, sizeof(s->fmc), typename);
d2623129	159	object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
f25c0ae1 CLG	160
	161	for (i = 0; i < sc->spis_num; i++) {
	162	snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
9bdee7f4	163	sysbus_init_child_obj(obj, "spi[*]", &s->spi[i],
f25c0ae1 CLG	164	sizeof(s->spi[i]), typename);
	165	}
	166
917940ce	167	for (i = 0; i < sc->ehcis_num; i++) {
9bdee7f4	168	sysbus_init_child_obj(obj, "ehci[*]", &s->ehci[i],
917940ce GR	169	sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
	170	}
	171
f25c0ae1	172	snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
9bdee7f4	173	sysbus_init_child_obj(obj, "sdmc", &s->sdmc, sizeof(s->sdmc), typename);
f25c0ae1	174	object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
d2623129	175	"ram-size");
f25c0ae1	176	object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
d2623129	177	"max-ram-size");
f25c0ae1 CLG	178
	179	for (i = 0; i < sc->wdts_num; i++) {
	180	snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
9bdee7f4	181	sysbus_init_child_obj(obj, "wdt[*]", &s->wdt[i],
f25c0ae1	182	sizeof(s->wdt[i]), typename);
f25c0ae1 CLG	183	}
f25c0ae1 CLG	184
d300db02	185	for (i = 0; i < sc->macs_num; i++) {
9bdee7f4	186	sysbus_init_child_obj(obj, "ftgmac100[*]", &s->ftgmac100[i],
f25c0ae1	187	sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
289251b0 CLG	188
	189	sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
	190	TYPE_ASPEED_MII);
f25c0ae1 CLG	191	}
f25c0ae1 CLG	192
9bdee7f4	193	sysbus_init_child_obj(obj, "xdma", &s->xdma, sizeof(s->xdma),
f25c0ae1 CLG	194	TYPE_ASPEED_XDMA);
	195
	196	snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
9bdee7f4	197	sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), typename);
f25c0ae1 CLG	198
f25c0ae1 CLG	199	snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
9bdee7f4	200	sysbus_init_child_obj(obj, "gpio_1_8v", &s->gpio_1_8v,
f25c0ae1 CLG	201	sizeof(s->gpio_1_8v), typename);
f25c0ae1 CLG	202
9bdee7f4	203	sysbus_init_child_obj(obj, "sd-controller", &s->sdhci,
a29e3e12	204	sizeof(s->sdhci), TYPE_ASPEED_SDHCI);
f25c0ae1	205
0e2c24c6 AJ	206	object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
0e2c24c6 AJ	207
f25c0ae1 CLG	208	/* Init sd card slot class here so that they're under the correct parent */
f25c0ae1 CLG	209	for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
a29e3e12	210	sysbus_init_child_obj(obj, "sd-controller.sdhci[*]",
9bdee7f4	211	&s->sdhci.slots[i],
f25c0ae1 CLG	212	sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
f25c0ae1 CLG	213	}
a29e3e12	214
9bdee7f4	215	sysbus_init_child_obj(obj, "emmc-controller", &s->emmc,
a29e3e12 AJ	216	sizeof(s->emmc), TYPE_ASPEED_SDHCI);
	217
	218	object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort);
	219
	220	sysbus_init_child_obj(obj, "emmc-controller.sdhci",
9bdee7f4	221	&s->emmc.slots[0], sizeof(s->emmc.slots[0]),
a29e3e12	222	TYPE_SYSBUS_SDHCI);
f25c0ae1 CLG	223	}
	224
	225	/*
	226	* ASPEED ast2600 has 0xf as cluster ID
	227	*
	228	* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
	229	*/
	230	static uint64_t aspeed_calc_affinity(int cpu)
	231	{
	232	return (0xf << ARM_AFF1_SHIFT) \| cpu;
	233	}
	234
	235	static void aspeed_soc_ast2600_realize(DeviceState dev, Error *errp)
	236	{
	237	int i;
	238	AspeedSoCState *s = ASPEED_SOC(dev);
	239	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	240	Error err = NULL, local_err = NULL;
	241	qemu_irq irq;
	242
	243	/* IO space */
	244	create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
	245	ASPEED_SOC_IOMEM_SIZE);
	246
514bcf6f JS	247	/* Video engine stub */
	248	create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
	249	0x1000);
	250
f25c0ae1	251	/* CPU */
b7f1a0cb	252	for (i = 0; i < sc->num_cpus; i++) {
f25c0ae1 CLG	253	object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f25c0ae1 CLG	254	"psci-conduit", &error_abort);
b7f1a0cb	255	if (sc->num_cpus > 1) {
f25c0ae1 CLG	256	object_property_set_int(OBJECT(&s->cpu[i]),
	257	ASPEED_A7MPCORE_ADDR,
	258	"reset-cbar", &error_abort);
	259	}
	260	object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
	261	"mp-affinity", &error_abort);
	262
058d0955 AJ	263	object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq",
	264	&error_abort);
	265
f25c0ae1 CLG	266	/*
	267	* TODO: the secondary CPUs are started and a boot helper
	268	* is needed when using -kernel
	269	*/
	270
	271	object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
	272	if (err) {
	273	error_propagate(errp, err);
	274	return;
	275	}
	276	}
	277
	278	/* A7MPCORE */
b7f1a0cb	279	object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu",
f25c0ae1 CLG	280	&error_abort);
	281	object_property_set_int(OBJECT(&s->a7mpcore),
	282	ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
	283	"num-irq", &error_abort);
	284
	285	object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
	286	&error_abort);
	287	sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
	288
b7f1a0cb	289	for (i = 0; i < sc->num_cpus; i++) {
f25c0ae1 CLG	290	SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
	291	DeviceState *d = DEVICE(qemu_get_cpu(i));
	292
	293	irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
	294	sysbus_connect_irq(sbd, i, irq);
	295	irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
b7f1a0cb	296	sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
f25c0ae1	297	irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
b7f1a0cb	298	sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
f25c0ae1	299	irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
b7f1a0cb	300	sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
f25c0ae1 CLG	301	}
	302
	303	/* SRAM */
	304	memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
	305	sc->sram_size, &err);
	306	if (err) {
	307	error_propagate(errp, err);
	308	return;
	309	}
	310	memory_region_add_subregion(get_system_memory(),
	311	sc->memmap[ASPEED_SRAM], &s->sram);
	312
	313	/* SCU */
	314	object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
	315	if (err) {
	316	error_propagate(errp, err);
	317	return;
	318	}
	319	sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
	320
	321	/* RTC */
	322	object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
	323	if (err) {
	324	error_propagate(errp, err);
	325	return;
	326	}
	327	sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
	328	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
	329	aspeed_soc_get_irq(s, ASPEED_RTC));
	330
	331	/* Timer */
2ec11f23 CLG	332	object_property_set_link(OBJECT(&s->timerctrl),
2ec11f23 CLG	333	OBJECT(&s->scu), "scu", &error_abort);
f25c0ae1 CLG	334	object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
	335	if (err) {
	336	error_propagate(errp, err);
	337	return;
	338	}
	339	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
	340	sc->memmap[ASPEED_TIMER1]);
	341	for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
	342	qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
	343	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
	344	}
	345
	346	/* UART - attach an 8250 to the IO space as our UART5 */
	347	if (serial_hd(0)) {
	348	qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
	349	serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
	350	uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
	351	}
	352
	353	/* I2C */
545d6bef CLG	354	object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
	355	if (err) {
	356	error_propagate(errp, err);
	357	return;
	358	}
f25c0ae1 CLG	359	object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
	360	if (err) {
	361	error_propagate(errp, err);
	362	return;
	363	}
	364	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
	365	for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
	366	qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
	367	sc->irqmap[ASPEED_I2C] + i);
	368	/*
	369	* The AST2600 SoC has one IRQ per I2C bus. Skip the common
	370	* IRQ (AST2400 and AST2500) and connect all bussses.
	371	*/
	372	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
	373	}
	374
	375	/* FMC, The number of CS is set at the board level */
95b56e17 CLG	376	object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
	377	if (err) {
	378	error_propagate(errp, err);
	379	return;
	380	}
f25c0ae1 CLG	381	object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
	382	"sdram-base", &err);
	383	if (err) {
	384	error_propagate(errp, err);
	385	return;
	386	}
	387	object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
	388	if (err) {
	389	error_propagate(errp, err);
	390	return;
	391	}
	392	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
	393	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
	394	s->fmc.ctrl->flash_window_base);
	395	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
	396	aspeed_soc_get_irq(s, ASPEED_FMC));
	397
	398	/* SPI */
	399	for (i = 0; i < sc->spis_num; i++) {
4dabf395 CLG	400	object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr),
	401	"dram", &err);
	402	if (err) {
	403	error_propagate(errp, err);
	404	return;
	405	}
f25c0ae1 CLG	406	object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
	407	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
	408	&local_err);
	409	error_propagate(&err, local_err);
	410	if (err) {
	411	error_propagate(errp, err);
	412	return;
	413	}
	414	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
	415	sc->memmap[ASPEED_SPI1 + i]);
	416	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
	417	s->spi[i].ctrl->flash_window_base);
	418	}
	419
917940ce GR	420	/* EHCI */
	421	for (i = 0; i < sc->ehcis_num; i++) {
	422	object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
	423	if (err) {
	424	error_propagate(errp, err);
	425	return;
	426	}
	427	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	428	sc->memmap[ASPEED_EHCI1 + i]);
	429	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	430	aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
	431	}
	432
f25c0ae1 CLG	433	/* SDMC - SDRAM Memory Controller */
	434	object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
	435	if (err) {
	436	error_propagate(errp, err);
	437	return;
	438	}
	439	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
	440
	441	/* Watch dog */
	442	for (i = 0; i < sc->wdts_num; i++) {
	443	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
	444
2ec11f23 CLG	445	object_property_set_link(OBJECT(&s->wdt[i]),
2ec11f23 CLG	446	OBJECT(&s->scu), "scu", &error_abort);
f25c0ae1 CLG	447	object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
	448	if (err) {
	449	error_propagate(errp, err);
	450	return;
	451	}
	452	sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
	453	sc->memmap[ASPEED_WDT] + i * awc->offset);
	454	}
	455
	456	/* Net */
d3bad7e7	457	for (i = 0; i < sc->macs_num; i++) {
f25c0ae1 CLG	458	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
	459	&err);
	460	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
	461	&local_err);
	462	error_propagate(&err, local_err);
	463	if (err) {
	464	error_propagate(errp, err);
	465	return;
	466	}
	467	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
	468	sc->memmap[ASPEED_ETH1 + i]);
	469	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
	470	aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
289251b0	471
ccb88bf2 CLG	472	object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]),
ccb88bf2 CLG	473	"nic", &error_abort);
289251b0 CLG	474	object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
	475	&err);
	476	if (err) {
	477	error_propagate(errp, err);
	478	return;
	479	}
	480
	481	sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
	482	sc->memmap[ASPEED_MII1 + i]);
f25c0ae1 CLG	483	}
	484
	485	/* XDMA */
	486	object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
	487	if (err) {
	488	error_propagate(errp, err);
	489	return;
	490	}
	491	sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
	492	sc->memmap[ASPEED_XDMA]);
	493	sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
	494	aspeed_soc_get_irq(s, ASPEED_XDMA));
	495
	496	/* GPIO */
	497	object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
	498	if (err) {
	499	error_propagate(errp, err);
	500	return;
	501	}
	502	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
	503	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
	504	aspeed_soc_get_irq(s, ASPEED_GPIO));
	505
	506	object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
	507	if (err) {
	508	error_propagate(errp, err);
	509	return;
	510	}
	511	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
	512	sc->memmap[ASPEED_GPIO_1_8V]);
	513	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
	514	aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
	515
	516	/* SDHCI */
	517	object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
	518	if (err) {
	519	error_propagate(errp, err);
	520	return;
	521	}
	522	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
	523	sc->memmap[ASPEED_SDHCI]);
	524	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
	525	aspeed_soc_get_irq(s, ASPEED_SDHCI));
a29e3e12 AJ	526
	527	/* eMMC */
	528	object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err);
	529	if (err) {
	530	error_propagate(errp, err);
	531	return;
	532	}
	533	sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]);
	534	sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
	535	aspeed_soc_get_irq(s, ASPEED_EMMC));
f25c0ae1 CLG	536	}
	537
	538	static void aspeed_soc_ast2600_class_init(ObjectClass oc, void data)
	539	{
	540	DeviceClass *dc = DEVICE_CLASS(oc);
	541	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
	542
	543	dc->realize = aspeed_soc_ast2600_realize;
	544
7582591a	545	sc->name = "ast2600-a1";
f25c0ae1	546	sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
7582591a	547	sc->silicon_rev = AST2600_A1_SILICON_REV;
f25c0ae1 CLG	548	sc->sram_size = 0x10000;
f25c0ae1 CLG	549	sc->spis_num = 2;
917940ce	550	sc->ehcis_num = 2;
f25c0ae1	551	sc->wdts_num = 4;
d300db02	552	sc->macs_num = 4;
f25c0ae1 CLG	553	sc->irqmap = aspeed_soc_ast2600_irqmap;
	554	sc->memmap = aspeed_soc_ast2600_memmap;
	555	sc->num_cpus = 2;
	556	}
	557
	558	static const TypeInfo aspeed_soc_ast2600_type_info = {
7582591a	559	.name = "ast2600-a1",
f25c0ae1 CLG	560	.parent = TYPE_ASPEED_SOC,
	561	.instance_size = sizeof(AspeedSoCState),
	562	.instance_init = aspeed_soc_ast2600_init,
	563	.class_init = aspeed_soc_ast2600_class_init,
	564	.class_size = sizeof(AspeedSoCClass),
	565	};
	566
	567	static void aspeed_soc_register_types(void)
	568	{
	569	type_register_static(&aspeed_soc_ast2600_type_info);
	570	};
	571
	572	type_init(aspeed_soc_register_types)