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[mirror_qemu.git] / hw / arm / aspeed_ast2600.c
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f25c0ae1
CLG		 1/*
2 * ASPEED SoC 2600 family
3 *
4 * Copyright (c) 2016-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "cpu.h"
13#include "exec/address-spaces.h"
14#include "hw/misc/unimp.h"
15#include "hw/arm/aspeed_soc.h"
16#include "hw/char/serial.h"
17#include "qemu/log.h"
18#include "qemu/module.h"
19#include "qemu/error-report.h"
20#include "hw/i2c/aspeed_i2c.h"
21#include "net/net.h"
22#include "sysemu/sysemu.h"
23
24#define ASPEED_SOC_IOMEM_SIZE 0x00200000
25
26static const hwaddr aspeed_soc_ast2600_memmap[] = {
27 [ASPEED_SRAM] = 0x10000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_IOMEM] = 0x1E600000,
30 [ASPEED_PWM] = 0x1E610000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_SPI2] = 0x1E641000,
34 [ASPEED_ETH1] = 0x1E660000,
35 [ASPEED_ETH2] = 0x1E680000,
36 [ASPEED_VIC] = 0x1E6C0000,
37 [ASPEED_SDMC] = 0x1E6E0000,
38 [ASPEED_SCU] = 0x1E6E2000,
39 [ASPEED_XDMA] = 0x1E6E7000,
40 [ASPEED_ADC] = 0x1E6E9000,
41 [ASPEED_SDHCI] = 0x1E740000,
42 [ASPEED_GPIO] = 0x1E780000,
43 [ASPEED_GPIO_1_8V] = 0x1E780800,
44 [ASPEED_RTC] = 0x1E781000,
45 [ASPEED_TIMER1] = 0x1E782000,
46 [ASPEED_WDT] = 0x1E785000,
47 [ASPEED_LPC] = 0x1E789000,
48 [ASPEED_IBT] = 0x1E789140,
49 [ASPEED_I2C] = 0x1E78A000,
50 [ASPEED_UART1] = 0x1E783000,
51 [ASPEED_UART5] = 0x1E784000,
52 [ASPEED_VUART] = 0x1E787000,
53 [ASPEED_SDRAM] = 0x80000000,
54};
55
56#define ASPEED_A7MPCORE_ADDR 0x40460000
57
58#define ASPEED_SOC_AST2600_MAX_IRQ 128
59
60static const int aspeed_soc_ast2600_irqmap[] = {
61 [ASPEED_UART1] = 47,
62 [ASPEED_UART2] = 48,
63 [ASPEED_UART3] = 49,
64 [ASPEED_UART4] = 50,
65 [ASPEED_UART5] = 8,
66 [ASPEED_VUART] = 8,
67 [ASPEED_FMC] = 39,
68 [ASPEED_SDMC] = 0,
69 [ASPEED_SCU] = 12,
70 [ASPEED_ADC] = 78,
71 [ASPEED_XDMA] = 6,
72 [ASPEED_SDHCI] = 43,
73 [ASPEED_GPIO] = 40,
74 [ASPEED_GPIO_1_8V] = 11,
75 [ASPEED_RTC] = 13,
76 [ASPEED_TIMER1] = 16,
77 [ASPEED_TIMER2] = 17,
78 [ASPEED_TIMER3] = 18,
79 [ASPEED_TIMER4] = 19,
80 [ASPEED_TIMER5] = 20,
81 [ASPEED_TIMER6] = 21,
82 [ASPEED_TIMER7] = 22,
83 [ASPEED_TIMER8] = 23,
84 [ASPEED_WDT] = 24,
85 [ASPEED_PWM] = 44,
86 [ASPEED_LPC] = 35,
87 [ASPEED_IBT] = 35, /* LPC */
88 [ASPEED_I2C] = 110, /* 110 -> 125 */
89 [ASPEED_ETH1] = 2,
90 [ASPEED_ETH2] = 3,
91};
92
93static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
94{
95 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
96
97 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]);
98}
99
100static void aspeed_soc_ast2600_init(Object *obj)
101{
102 AspeedSoCState *s = ASPEED_SOC(obj);
103 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
104 int i;
105 char socname[8];
106 char typename[64];
107
108 if (sscanf(sc->name, "%7s", socname) != 1) {
109 g_assert_not_reached();
110 }
111
112 for (i = 0; i < sc->num_cpus; i++) {
113 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
114 sizeof(s->cpu[i]), sc->cpu_type,
115 &error_abort, NULL);
116 }
117
118 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
119 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
120 typename);
121 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
122 sc->silicon_rev);
123 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
124 "hw-strap1", &error_abort);
125 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
126 "hw-strap2", &error_abort);
127 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
128 "hw-prot-key", &error_abort);
129
130 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore,
131 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV);
132
133 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
134 TYPE_ASPEED_RTC);
135
136 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
137 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
138 sizeof(s->timerctrl), typename);
139 object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
140 OBJECT(&s->scu), &error_abort);
141
142 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
143 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
144 typename);
145
146 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
147 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
148 typename);
149 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
150 &error_abort);
151 object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
152 &error_abort);
153
154 for (i = 0; i < sc->spis_num; i++) {
155 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
156 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
157 sizeof(s->spi[i]), typename);
158 }
159
160 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
161 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
162 typename);
163 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
164 "ram-size", &error_abort);
165 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
166 "max-ram-size", &error_abort);
167
168 for (i = 0; i < sc->wdts_num; i++) {
169 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
170 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
171 sizeof(s->wdt[i]), typename);
172 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
173 OBJECT(&s->scu), &error_abort);
174 }
175
176 for (i = 0; i < ASPEED_MACS_NUM; i++) {
177 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
178 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
179 }
180
181 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
182 TYPE_ASPEED_XDMA);
183
184 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
185 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
186 typename);
187
188 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
189 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v),
190 sizeof(s->gpio_1_8v), typename);
191
192 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
193 TYPE_ASPEED_SDHCI);
194
195 /* Init sd card slot class here so that they're under the correct parent */
196 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
197 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
198 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
199 }
200}
201
202/*
203 * ASPEED ast2600 has 0xf as cluster ID
204 *
205 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
206 */
207static uint64_t aspeed_calc_affinity(int cpu)
208{
209 return (0xf << ARM_AFF1_SHIFT) | cpu;
210}
211
212static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
213{
214 int i;
215 AspeedSoCState *s = ASPEED_SOC(dev);
216 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
217 Error *err = NULL, *local_err = NULL;
218 qemu_irq irq;
219
220 /* IO space */
221 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
222 ASPEED_SOC_IOMEM_SIZE);
223
224 if (s->num_cpus > sc->num_cpus) {
225 warn_report("%s: invalid number of CPUs %d, using default %d",
226 sc->name, s->num_cpus, sc->num_cpus);
227 s->num_cpus = sc->num_cpus;
228 }
229
230 /* CPU */
231 for (i = 0; i < s->num_cpus; i++) {
232 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
233 "psci-conduit", &error_abort);
234 if (s->num_cpus > 1) {
235 object_property_set_int(OBJECT(&s->cpu[i]),
236 ASPEED_A7MPCORE_ADDR,
237 "reset-cbar", &error_abort);
238 }
239 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i),
240 "mp-affinity", &error_abort);
241
242 /*
243 * TODO: the secondary CPUs are started and a boot helper
244 * is needed when using -kernel
245 */
246
247 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
248 if (err) {
249 error_propagate(errp, err);
250 return;
251 }
252 }
253
254 /* A7MPCORE */
255 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu",
256 &error_abort);
257 object_property_set_int(OBJECT(&s->a7mpcore),
258 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
259 "num-irq", &error_abort);
260
261 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
262 &error_abort);
263 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
264
265 for (i = 0; i < s->num_cpus; i++) {
266 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
267 DeviceState *d = DEVICE(qemu_get_cpu(i));
268
269 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
270 sysbus_connect_irq(sbd, i, irq);
271 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
272 sysbus_connect_irq(sbd, i + s->num_cpus, irq);
273 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
274 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq);
275 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
276 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq);
277 }
278
279 /* SRAM */
280 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
281 sc->sram_size, &err);
282 if (err) {
283 error_propagate(errp, err);
284 return;
285 }
286 memory_region_add_subregion(get_system_memory(),
287 sc->memmap[ASPEED_SRAM], &s->sram);
288
289 /* SCU */
290 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
291 if (err) {
292 error_propagate(errp, err);
293 return;
294 }
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
296
297 /* RTC */
298 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
299 if (err) {
300 error_propagate(errp, err);
301 return;
302 }
303 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
305 aspeed_soc_get_irq(s, ASPEED_RTC));
306
307 /* Timer */
308 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
309 if (err) {
310 error_propagate(errp, err);
311 return;
312 }
313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
314 sc->memmap[ASPEED_TIMER1]);
315 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
316 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
317 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
318 }
319
320 /* UART - attach an 8250 to the IO space as our UART5 */
321 if (serial_hd(0)) {
322 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
323 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
324 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
325 }
326
327 /* I2C */
328 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
329 if (err) {
330 error_propagate(errp, err);
331 return;
332 }
333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
334 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
335 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
336 sc->irqmap[ASPEED_I2C] + i);
337 /*
338 * The AST2600 SoC has one IRQ per I2C bus. Skip the common
339 * IRQ (AST2400 and AST2500) and connect all bussses.
340 */
341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq);
342 }
343
344 /* FMC, The number of CS is set at the board level */
345 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
346 "sdram-base", &err);
347 if (err) {
348 error_propagate(errp, err);
349 return;
350 }
351 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
352 if (err) {
353 error_propagate(errp, err);
354 return;
355 }
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
357 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
358 s->fmc.ctrl->flash_window_base);
359 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
360 aspeed_soc_get_irq(s, ASPEED_FMC));
361
362 /* SPI */
363 for (i = 0; i < sc->spis_num; i++) {
364 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
365 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
366 &local_err);
367 error_propagate(&err, local_err);
368 if (err) {
369 error_propagate(errp, err);
370 return;
371 }
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
373 sc->memmap[ASPEED_SPI1 + i]);
374 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
375 s->spi[i].ctrl->flash_window_base);
376 }
377
378 /* SDMC - SDRAM Memory Controller */
379 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
380 if (err) {
381 error_propagate(errp, err);
382 return;
383 }
384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
385
386 /* Watch dog */
387 for (i = 0; i < sc->wdts_num; i++) {
388 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
389
390 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
391 if (err) {
392 error_propagate(errp, err);
393 return;
394 }
395 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
396 sc->memmap[ASPEED_WDT] + i * awc->offset);
397 }
398
399 /* Net */
400 for (i = 0; i < nb_nics; i++) {
401 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
402 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
403 &err);
404 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
405 &local_err);
406 error_propagate(&err, local_err);
407 if (err) {
408 error_propagate(errp, err);
409 return;
410 }
411 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
412 sc->memmap[ASPEED_ETH1 + i]);
413 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
414 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
415 }
416
417 /* XDMA */
418 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
419 if (err) {
420 error_propagate(errp, err);
421 return;
422 }
423 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
424 sc->memmap[ASPEED_XDMA]);
425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
426 aspeed_soc_get_irq(s, ASPEED_XDMA));
427
428 /* GPIO */
429 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
430 if (err) {
431 error_propagate(errp, err);
432 return;
433 }
434 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
435 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
436 aspeed_soc_get_irq(s, ASPEED_GPIO));
437
438 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err);
439 if (err) {
440 error_propagate(errp, err);
441 return;
442 }
443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
444 sc->memmap[ASPEED_GPIO_1_8V]);
445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
446 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V));
447
448 /* SDHCI */
449 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
450 if (err) {
451 error_propagate(errp, err);
452 return;
453 }
454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
455 sc->memmap[ASPEED_SDHCI]);
456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
457 aspeed_soc_get_irq(s, ASPEED_SDHCI));
458}
459
460static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
461{
462 DeviceClass *dc = DEVICE_CLASS(oc);
463 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
464
465 dc->realize = aspeed_soc_ast2600_realize;
466
467 sc->name = "ast2600-a0";
468 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
469 sc->silicon_rev = AST2600_A0_SILICON_REV;
470 sc->sram_size = 0x10000;
471 sc->spis_num = 2;
472 sc->wdts_num = 4;
473 sc->irqmap = aspeed_soc_ast2600_irqmap;
474 sc->memmap = aspeed_soc_ast2600_memmap;
475 sc->num_cpus = 2;
476}
477
478static const TypeInfo aspeed_soc_ast2600_type_info = {
479 .name = "ast2600-a0",
480 .parent = TYPE_ASPEED_SOC,
481 .instance_size = sizeof(AspeedSoCState),
482 .instance_init = aspeed_soc_ast2600_init,
483 .class_init = aspeed_soc_ast2600_class_init,
484 .class_size = sizeof(AspeedSoCClass),
485};
486
487static void aspeed_soc_register_types(void)
488{
489 type_register_static(&aspeed_soc_ast2600_type_info);
490};
491
492type_init(aspeed_soc_register_types)
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