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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "cpu.h" |
43e3346e | 16 | #include "exec/address-spaces.h" |
c7c3c9f8 | 17 | #include "hw/misc/unimp.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 19 | #include "hw/char/serial.h" |
03dd024f | 20 | #include "qemu/log.h" |
0b8fa32f | 21 | #include "qemu/module.h" |
16020011 | 22 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 23 | #include "net/net.h" |
43e3346e | 24 | |
ff90606f CLG |
25 | #define ASPEED_SOC_UART_5_BASE 0x00184000 |
26 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
27 | #define ASPEED_SOC_IOMEM_BASE 0x1E600000 | |
28 | #define ASPEED_SOC_FMC_BASE 0x1E620000 | |
29 | #define ASPEED_SOC_SPI_BASE 0x1E630000 | |
6dc52326 | 30 | #define ASPEED_SOC_SPI2_BASE 0x1E631000 |
ff90606f CLG |
31 | #define ASPEED_SOC_VIC_BASE 0x1E6C0000 |
32 | #define ASPEED_SOC_SDMC_BASE 0x1E6E0000 | |
33 | #define ASPEED_SOC_SCU_BASE 0x1E6E2000 | |
74af4eec | 34 | #define ASPEED_SOC_SRAM_BASE 0x1E720000 |
ff90606f | 35 | #define ASPEED_SOC_TIMER_BASE 0x1E782000 |
013befe1 | 36 | #define ASPEED_SOC_WDT_BASE 0x1E785000 |
ff90606f | 37 | #define ASPEED_SOC_I2C_BASE 0x1E78A000 |
ea337c65 CLG |
38 | #define ASPEED_SOC_ETH1_BASE 0x1E660000 |
39 | #define ASPEED_SOC_ETH2_BASE 0x1E680000 | |
ff90606f | 40 | |
43e3346e AJ |
41 | static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; |
42 | static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; | |
43 | ||
b033271f | 44 | #define AST2400_SDRAM_BASE 0x40000000 |
365aff1e | 45 | #define AST2500_SDRAM_BASE 0x80000000 |
b033271f | 46 | |
dbcabeeb | 47 | static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE }; |
6dc52326 | 48 | static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" }; |
dbcabeeb | 49 | |
6dc52326 CLG |
50 | static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE, |
51 | ASPEED_SOC_SPI2_BASE}; | |
52 | static const char *aspeed_soc_ast2500_typenames[] = { | |
53 | "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" }; | |
dbcabeeb | 54 | |
b033271f | 55 | static const AspeedSoCInfo aspeed_socs[] = { |
74af4eec CLG |
56 | { |
57 | .name = "ast2400-a0", | |
ba1ba5cc | 58 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
74af4eec CLG |
59 | .silicon_rev = AST2400_A0_SILICON_REV, |
60 | .sdram_base = AST2400_SDRAM_BASE, | |
61 | .sram_size = 0x8000, | |
62 | .spis_num = 1, | |
63 | .spi_bases = aspeed_soc_ast2400_spi_bases, | |
64 | .fmc_typename = "aspeed.smc.fmc", | |
65 | .spi_typename = aspeed_soc_ast2400_typenames, | |
f986ee1d | 66 | .wdts_num = 2, |
6efbac90 CLG |
67 | }, { |
68 | .name = "ast2400-a1", | |
ba1ba5cc | 69 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
6efbac90 CLG |
70 | .silicon_rev = AST2400_A1_SILICON_REV, |
71 | .sdram_base = AST2400_SDRAM_BASE, | |
72 | .sram_size = 0x8000, | |
73 | .spis_num = 1, | |
74 | .spi_bases = aspeed_soc_ast2400_spi_bases, | |
75 | .fmc_typename = "aspeed.smc.fmc", | |
76 | .spi_typename = aspeed_soc_ast2400_typenames, | |
f986ee1d | 77 | .wdts_num = 2, |
74af4eec CLG |
78 | }, { |
79 | .name = "ast2400", | |
ba1ba5cc | 80 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
74af4eec CLG |
81 | .silicon_rev = AST2400_A0_SILICON_REV, |
82 | .sdram_base = AST2400_SDRAM_BASE, | |
83 | .sram_size = 0x8000, | |
84 | .spis_num = 1, | |
85 | .spi_bases = aspeed_soc_ast2400_spi_bases, | |
86 | .fmc_typename = "aspeed.smc.fmc", | |
87 | .spi_typename = aspeed_soc_ast2400_typenames, | |
f986ee1d | 88 | .wdts_num = 2, |
74af4eec CLG |
89 | }, { |
90 | .name = "ast2500-a1", | |
ba1ba5cc | 91 | .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), |
74af4eec CLG |
92 | .silicon_rev = AST2500_A1_SILICON_REV, |
93 | .sdram_base = AST2500_SDRAM_BASE, | |
94 | .sram_size = 0x9000, | |
95 | .spis_num = 2, | |
96 | .spi_bases = aspeed_soc_ast2500_spi_bases, | |
97 | .fmc_typename = "aspeed.smc.ast2500-fmc", | |
98 | .spi_typename = aspeed_soc_ast2500_typenames, | |
f986ee1d | 99 | .wdts_num = 3, |
74af4eec | 100 | }, |
b033271f CLG |
101 | }; |
102 | ||
ff90606f | 103 | static void aspeed_soc_init(Object *obj) |
43e3346e | 104 | { |
ff90606f | 105 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 106 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 107 | int i; |
43e3346e | 108 | |
1b0ad567 PMD |
109 | object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu), |
110 | sc->info->cpu_type, &error_abort, NULL); | |
43e3346e | 111 | |
1b0ad567 PMD |
112 | sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), |
113 | TYPE_ASPEED_SCU); | |
334973bb | 114 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
b033271f | 115 | sc->info->silicon_rev); |
334973bb AJ |
116 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
117 | "hw-strap1", &error_abort); | |
118 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | |
119 | "hw-strap2", &error_abort); | |
b6e70d1d JS |
120 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
121 | "hw-prot-key", &error_abort); | |
7c1c69bc | 122 | |
1b0ad567 PMD |
123 | sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic), |
124 | TYPE_ASPEED_VIC); | |
e2a11ca8 | 125 | |
1b0ad567 PMD |
126 | sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), |
127 | sizeof(s->timerctrl), TYPE_ASPEED_TIMER); | |
9b945a9e CLG |
128 | object_property_add_const_link(OBJECT(&s->timerctrl), "scu", |
129 | OBJECT(&s->scu), &error_abort); | |
e2a11ca8 | 130 | |
1b0ad567 PMD |
131 | sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), |
132 | TYPE_ASPEED_I2C); | |
e2a11ca8 | 133 | |
1b0ad567 PMD |
134 | sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), |
135 | sc->info->fmc_typename); | |
26d5df95 CLG |
136 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", |
137 | &error_abort); | |
7c1c69bc | 138 | |
dbcabeeb | 139 | for (i = 0; i < sc->info->spis_num; i++) { |
1b0ad567 PMD |
140 | sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), |
141 | sizeof(s->spi[i]), sc->info->spi_typename[i]); | |
dbcabeeb | 142 | } |
c2da8a8b | 143 | |
1b0ad567 PMD |
144 | sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), |
145 | TYPE_ASPEED_SDMC); | |
c2da8a8b | 146 | qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", |
b033271f | 147 | sc->info->silicon_rev); |
c6c7cfb0 CLG |
148 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
149 | "ram-size", &error_abort); | |
ebe31c0a CLG |
150 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
151 | "max-ram-size", &error_abort); | |
013befe1 | 152 | |
f986ee1d | 153 | for (i = 0; i < sc->info->wdts_num; i++) { |
1b0ad567 PMD |
154 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), |
155 | sizeof(s->wdt[i]), TYPE_ASPEED_WDT); | |
429789cc AJ |
156 | qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", |
157 | sc->info->silicon_rev); | |
f986ee1d | 158 | } |
ea337c65 | 159 | |
1b0ad567 PMD |
160 | sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100), |
161 | sizeof(s->ftgmac100), TYPE_FTGMAC100); | |
43e3346e AJ |
162 | } |
163 | ||
ff90606f | 164 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
165 | { |
166 | int i; | |
ff90606f | 167 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 168 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
7c1c69bc | 169 | Error *err = NULL, *local_err = NULL; |
43e3346e AJ |
170 | |
171 | /* IO space */ | |
c7c3c9f8 PMD |
172 | create_unimplemented_device("aspeed_soc.io", |
173 | ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE); | |
43e3346e | 174 | |
2d105bd6 CLG |
175 | /* CPU */ |
176 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | |
177 | if (err) { | |
178 | error_propagate(errp, err); | |
179 | return; | |
180 | } | |
181 | ||
74af4eec | 182 | /* SRAM */ |
a2e9989c | 183 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", |
74af4eec CLG |
184 | sc->info->sram_size, &err); |
185 | if (err) { | |
186 | error_propagate(errp, err); | |
187 | return; | |
188 | } | |
74af4eec CLG |
189 | memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE, |
190 | &s->sram); | |
191 | ||
e2a11ca8 CLG |
192 | /* SCU */ |
193 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
194 | if (err) { | |
195 | error_propagate(errp, err); | |
196 | return; | |
197 | } | |
198 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); | |
199 | ||
43e3346e AJ |
200 | /* VIC */ |
201 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | |
202 | if (err) { | |
203 | error_propagate(errp, err); | |
204 | return; | |
205 | } | |
ff90606f | 206 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE); |
43e3346e | 207 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 208 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 209 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 210 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e AJ |
211 | |
212 | /* Timer */ | |
213 | object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | |
214 | if (err) { | |
215 | error_propagate(errp, err); | |
216 | return; | |
217 | } | |
ff90606f | 218 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE); |
43e3346e AJ |
219 | for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) { |
220 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]); | |
221 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
222 | } | |
223 | ||
224 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
9bca0edb | 225 | if (serial_hd(0)) { |
43e3346e | 226 | qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); |
022d72d0 PMD |
227 | serial_mm_init(get_system_memory(), |
228 | ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, | |
9bca0edb | 229 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); |
43e3346e | 230 | } |
16020011 CLG |
231 | |
232 | /* I2C */ | |
233 | object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); | |
234 | if (err) { | |
235 | error_propagate(errp, err); | |
236 | return; | |
237 | } | |
ff90606f | 238 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE); |
16020011 CLG |
239 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
240 | qdev_get_gpio_in(DEVICE(&s->vic), 12)); | |
7c1c69bc | 241 | |
26d5df95 CLG |
242 | /* FMC, The number of CS is set at the board level */ |
243 | object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); | |
7c1c69bc CLG |
244 | if (err) { |
245 | error_propagate(errp, err); | |
246 | return; | |
247 | } | |
0e5803df | 248 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE); |
dcb83444 CLG |
249 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
250 | s->fmc.ctrl->flash_window_base); | |
0e5803df | 251 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
7c1c69bc CLG |
252 | qdev_get_gpio_in(DEVICE(&s->vic), 19)); |
253 | ||
254 | /* SPI */ | |
dbcabeeb CLG |
255 | for (i = 0; i < sc->info->spis_num; i++) { |
256 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | |
257 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | |
258 | &local_err); | |
259 | error_propagate(&err, local_err); | |
260 | if (err) { | |
261 | error_propagate(errp, err); | |
262 | return; | |
263 | } | |
264 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]); | |
265 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | |
266 | s->spi[i].ctrl->flash_window_base); | |
7c1c69bc | 267 | } |
c2da8a8b CLG |
268 | |
269 | /* SDMC - SDRAM Memory Controller */ | |
270 | object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); | |
271 | if (err) { | |
272 | error_propagate(errp, err); | |
273 | return; | |
274 | } | |
ff90606f | 275 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); |
013befe1 CLG |
276 | |
277 | /* Watch dog */ | |
f986ee1d JS |
278 | for (i = 0; i < sc->info->wdts_num; i++) { |
279 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | |
280 | if (err) { | |
281 | error_propagate(errp, err); | |
282 | return; | |
283 | } | |
284 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
285 | ASPEED_SOC_WDT_BASE + i * 0x20); | |
013befe1 | 286 | } |
ea337c65 CLG |
287 | |
288 | /* Net */ | |
289 | qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]); | |
290 | object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err); | |
291 | object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized", | |
292 | &local_err); | |
293 | error_propagate(&err, local_err); | |
294 | if (err) { | |
295 | error_propagate(errp, err); | |
296 | return; | |
297 | } | |
298 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE); | |
299 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, | |
300 | qdev_get_gpio_in(DEVICE(&s->vic), 2)); | |
43e3346e AJ |
301 | } |
302 | ||
ff90606f | 303 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
304 | { |
305 | DeviceClass *dc = DEVICE_CLASS(oc); | |
b033271f | 306 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
43e3346e | 307 | |
b033271f | 308 | sc->info = (AspeedSoCInfo *) data; |
ff90606f | 309 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
310 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
311 | dc->user_creatable = false; | |
43e3346e AJ |
312 | } |
313 | ||
ff90606f | 314 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
315 | .name = TYPE_ASPEED_SOC, |
316 | .parent = TYPE_DEVICE, | |
317 | .instance_init = aspeed_soc_init, | |
318 | .instance_size = sizeof(AspeedSoCState), | |
319 | .class_size = sizeof(AspeedSoCClass), | |
320 | .abstract = true, | |
43e3346e AJ |
321 | }; |
322 | ||
ff90606f | 323 | static void aspeed_soc_register_types(void) |
43e3346e | 324 | { |
b033271f CLG |
325 | int i; |
326 | ||
ff90606f | 327 | type_register_static(&aspeed_soc_type_info); |
b033271f CLG |
328 | for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) { |
329 | TypeInfo ti = { | |
330 | .name = aspeed_socs[i].name, | |
331 | .parent = TYPE_ASPEED_SOC, | |
332 | .class_init = aspeed_soc_class_init, | |
333 | .class_data = (void *) &aspeed_socs[i], | |
334 | }; | |
335 | type_register(&ti); | |
336 | } | |
43e3346e AJ |
337 | } |
338 | ||
ff90606f | 339 | type_init(aspeed_soc_register_types) |