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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 PB |
15 | #include "qemu-common.h" |
16 | #include "cpu.h" | |
43e3346e | 17 | #include "exec/address-spaces.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 19 | #include "hw/char/serial.h" |
03dd024f | 20 | #include "qemu/log.h" |
16020011 | 21 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 22 | #include "net/net.h" |
43e3346e | 23 | |
ff90606f CLG |
24 | #define ASPEED_SOC_UART_5_BASE 0x00184000 |
25 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
26 | #define ASPEED_SOC_IOMEM_BASE 0x1E600000 | |
27 | #define ASPEED_SOC_FMC_BASE 0x1E620000 | |
28 | #define ASPEED_SOC_SPI_BASE 0x1E630000 | |
6dc52326 | 29 | #define ASPEED_SOC_SPI2_BASE 0x1E631000 |
ff90606f CLG |
30 | #define ASPEED_SOC_VIC_BASE 0x1E6C0000 |
31 | #define ASPEED_SOC_SDMC_BASE 0x1E6E0000 | |
32 | #define ASPEED_SOC_SCU_BASE 0x1E6E2000 | |
74af4eec | 33 | #define ASPEED_SOC_SRAM_BASE 0x1E720000 |
ff90606f | 34 | #define ASPEED_SOC_TIMER_BASE 0x1E782000 |
013befe1 | 35 | #define ASPEED_SOC_WDT_BASE 0x1E785000 |
ff90606f | 36 | #define ASPEED_SOC_I2C_BASE 0x1E78A000 |
ea337c65 CLG |
37 | #define ASPEED_SOC_ETH1_BASE 0x1E660000 |
38 | #define ASPEED_SOC_ETH2_BASE 0x1E680000 | |
ff90606f | 39 | |
43e3346e AJ |
40 | static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; |
41 | static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; | |
42 | ||
b033271f | 43 | #define AST2400_SDRAM_BASE 0x40000000 |
365aff1e | 44 | #define AST2500_SDRAM_BASE 0x80000000 |
b033271f | 45 | |
dbcabeeb | 46 | static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE }; |
6dc52326 | 47 | static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" }; |
dbcabeeb | 48 | |
6dc52326 CLG |
49 | static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE, |
50 | ASPEED_SOC_SPI2_BASE}; | |
51 | static const char *aspeed_soc_ast2500_typenames[] = { | |
52 | "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" }; | |
dbcabeeb | 53 | |
b033271f | 54 | static const AspeedSoCInfo aspeed_socs[] = { |
74af4eec CLG |
55 | { |
56 | .name = "ast2400-a0", | |
ba1ba5cc | 57 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
74af4eec CLG |
58 | .silicon_rev = AST2400_A0_SILICON_REV, |
59 | .sdram_base = AST2400_SDRAM_BASE, | |
60 | .sram_size = 0x8000, | |
61 | .spis_num = 1, | |
62 | .spi_bases = aspeed_soc_ast2400_spi_bases, | |
63 | .fmc_typename = "aspeed.smc.fmc", | |
64 | .spi_typename = aspeed_soc_ast2400_typenames, | |
f986ee1d | 65 | .wdts_num = 2, |
6efbac90 CLG |
66 | }, { |
67 | .name = "ast2400-a1", | |
ba1ba5cc | 68 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
6efbac90 CLG |
69 | .silicon_rev = AST2400_A1_SILICON_REV, |
70 | .sdram_base = AST2400_SDRAM_BASE, | |
71 | .sram_size = 0x8000, | |
72 | .spis_num = 1, | |
73 | .spi_bases = aspeed_soc_ast2400_spi_bases, | |
74 | .fmc_typename = "aspeed.smc.fmc", | |
75 | .spi_typename = aspeed_soc_ast2400_typenames, | |
f986ee1d | 76 | .wdts_num = 2, |
74af4eec CLG |
77 | }, { |
78 | .name = "ast2400", | |
ba1ba5cc | 79 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
74af4eec CLG |
80 | .silicon_rev = AST2400_A0_SILICON_REV, |
81 | .sdram_base = AST2400_SDRAM_BASE, | |
82 | .sram_size = 0x8000, | |
83 | .spis_num = 1, | |
84 | .spi_bases = aspeed_soc_ast2400_spi_bases, | |
85 | .fmc_typename = "aspeed.smc.fmc", | |
86 | .spi_typename = aspeed_soc_ast2400_typenames, | |
f986ee1d | 87 | .wdts_num = 2, |
74af4eec CLG |
88 | }, { |
89 | .name = "ast2500-a1", | |
ba1ba5cc | 90 | .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), |
74af4eec CLG |
91 | .silicon_rev = AST2500_A1_SILICON_REV, |
92 | .sdram_base = AST2500_SDRAM_BASE, | |
93 | .sram_size = 0x9000, | |
94 | .spis_num = 2, | |
95 | .spi_bases = aspeed_soc_ast2500_spi_bases, | |
96 | .fmc_typename = "aspeed.smc.ast2500-fmc", | |
97 | .spi_typename = aspeed_soc_ast2500_typenames, | |
f986ee1d | 98 | .wdts_num = 3, |
74af4eec | 99 | }, |
b033271f CLG |
100 | }; |
101 | ||
43e3346e AJ |
102 | /* |
103 | * IO handlers: simply catch any reads/writes to IO addresses that aren't | |
104 | * handled by a device mapping. | |
105 | */ | |
106 | ||
ff90606f | 107 | static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size) |
43e3346e AJ |
108 | { |
109 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | |
110 | __func__, offset, size); | |
111 | return 0; | |
112 | } | |
113 | ||
ff90606f | 114 | static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value, |
43e3346e AJ |
115 | unsigned size) |
116 | { | |
117 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", | |
118 | __func__, offset, value, size); | |
119 | } | |
120 | ||
ff90606f CLG |
121 | static const MemoryRegionOps aspeed_soc_io_ops = { |
122 | .read = aspeed_soc_io_read, | |
123 | .write = aspeed_soc_io_write, | |
43e3346e AJ |
124 | .endianness = DEVICE_LITTLE_ENDIAN, |
125 | }; | |
126 | ||
ff90606f | 127 | static void aspeed_soc_init(Object *obj) |
43e3346e | 128 | { |
ff90606f | 129 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 130 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 131 | int i; |
43e3346e | 132 | |
ba1ba5cc | 133 | object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type); |
2d105bd6 | 134 | object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); |
43e3346e AJ |
135 | |
136 | object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); | |
137 | object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); | |
138 | qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); | |
139 | ||
140 | object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER); | |
141 | object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL); | |
142 | qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); | |
16020011 CLG |
143 | |
144 | object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C); | |
145 | object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL); | |
146 | qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default()); | |
334973bb AJ |
147 | |
148 | object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU); | |
149 | object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL); | |
150 | qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); | |
151 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", | |
b033271f | 152 | sc->info->silicon_rev); |
334973bb AJ |
153 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
154 | "hw-strap1", &error_abort); | |
155 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | |
156 | "hw-strap2", &error_abort); | |
b6e70d1d JS |
157 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
158 | "hw-prot-key", &error_abort); | |
7c1c69bc | 159 | |
6dc52326 | 160 | object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); |
0e5803df CLG |
161 | object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); |
162 | qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); | |
26d5df95 CLG |
163 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", |
164 | &error_abort); | |
7c1c69bc | 165 | |
dbcabeeb | 166 | for (i = 0; i < sc->info->spis_num; i++) { |
6dc52326 CLG |
167 | object_initialize(&s->spi[i], sizeof(s->spi[i]), |
168 | sc->info->spi_typename[i]); | |
bd673bd8 | 169 | object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL); |
dbcabeeb CLG |
170 | qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); |
171 | } | |
c2da8a8b CLG |
172 | |
173 | object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC); | |
174 | object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL); | |
175 | qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default()); | |
176 | qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", | |
b033271f | 177 | sc->info->silicon_rev); |
c6c7cfb0 CLG |
178 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
179 | "ram-size", &error_abort); | |
013befe1 | 180 | |
f986ee1d JS |
181 | for (i = 0; i < sc->info->wdts_num; i++) { |
182 | object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); | |
183 | object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL); | |
184 | qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); | |
429789cc AJ |
185 | qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", |
186 | sc->info->silicon_rev); | |
f986ee1d | 187 | } |
ea337c65 CLG |
188 | |
189 | object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100); | |
190 | object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL); | |
191 | qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default()); | |
43e3346e AJ |
192 | } |
193 | ||
ff90606f | 194 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
195 | { |
196 | int i; | |
ff90606f | 197 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 198 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
7c1c69bc | 199 | Error *err = NULL, *local_err = NULL; |
43e3346e AJ |
200 | |
201 | /* IO space */ | |
ff90606f CLG |
202 | memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL, |
203 | "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE); | |
204 | memory_region_add_subregion_overlap(get_system_memory(), | |
205 | ASPEED_SOC_IOMEM_BASE, &s->iomem, -1); | |
43e3346e | 206 | |
2d105bd6 CLG |
207 | /* CPU */ |
208 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | |
209 | if (err) { | |
210 | error_propagate(errp, err); | |
211 | return; | |
212 | } | |
213 | ||
74af4eec | 214 | /* SRAM */ |
1cfe48c1 | 215 | memory_region_init_ram_nomigrate(&s->sram, OBJECT(dev), "aspeed.sram", |
74af4eec CLG |
216 | sc->info->sram_size, &err); |
217 | if (err) { | |
218 | error_propagate(errp, err); | |
219 | return; | |
220 | } | |
221 | vmstate_register_ram_global(&s->sram); | |
222 | memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE, | |
223 | &s->sram); | |
224 | ||
43e3346e AJ |
225 | /* VIC */ |
226 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | |
227 | if (err) { | |
228 | error_propagate(errp, err); | |
229 | return; | |
230 | } | |
ff90606f | 231 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE); |
43e3346e | 232 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 233 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 234 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 235 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e AJ |
236 | |
237 | /* Timer */ | |
238 | object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | |
239 | if (err) { | |
240 | error_propagate(errp, err); | |
241 | return; | |
242 | } | |
ff90606f | 243 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE); |
43e3346e AJ |
244 | for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) { |
245 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]); | |
246 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
247 | } | |
248 | ||
334973bb AJ |
249 | /* SCU */ |
250 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
251 | if (err) { | |
252 | error_propagate(errp, err); | |
253 | return; | |
254 | } | |
ff90606f | 255 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); |
334973bb | 256 | |
43e3346e AJ |
257 | /* UART - attach an 8250 to the IO space as our UART5 */ |
258 | if (serial_hds[0]) { | |
259 | qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); | |
022d72d0 PMD |
260 | serial_mm_init(get_system_memory(), |
261 | ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, | |
43e3346e AJ |
262 | uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN); |
263 | } | |
16020011 CLG |
264 | |
265 | /* I2C */ | |
266 | object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); | |
267 | if (err) { | |
268 | error_propagate(errp, err); | |
269 | return; | |
270 | } | |
ff90606f | 271 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE); |
16020011 CLG |
272 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
273 | qdev_get_gpio_in(DEVICE(&s->vic), 12)); | |
7c1c69bc | 274 | |
26d5df95 CLG |
275 | /* FMC, The number of CS is set at the board level */ |
276 | object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); | |
7c1c69bc CLG |
277 | if (err) { |
278 | error_propagate(errp, err); | |
279 | return; | |
280 | } | |
0e5803df | 281 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE); |
dcb83444 CLG |
282 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
283 | s->fmc.ctrl->flash_window_base); | |
0e5803df | 284 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
7c1c69bc CLG |
285 | qdev_get_gpio_in(DEVICE(&s->vic), 19)); |
286 | ||
287 | /* SPI */ | |
dbcabeeb CLG |
288 | for (i = 0; i < sc->info->spis_num; i++) { |
289 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | |
290 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | |
291 | &local_err); | |
292 | error_propagate(&err, local_err); | |
293 | if (err) { | |
294 | error_propagate(errp, err); | |
295 | return; | |
296 | } | |
297 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]); | |
298 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | |
299 | s->spi[i].ctrl->flash_window_base); | |
7c1c69bc | 300 | } |
c2da8a8b CLG |
301 | |
302 | /* SDMC - SDRAM Memory Controller */ | |
303 | object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); | |
304 | if (err) { | |
305 | error_propagate(errp, err); | |
306 | return; | |
307 | } | |
ff90606f | 308 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); |
013befe1 CLG |
309 | |
310 | /* Watch dog */ | |
f986ee1d JS |
311 | for (i = 0; i < sc->info->wdts_num; i++) { |
312 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | |
313 | if (err) { | |
314 | error_propagate(errp, err); | |
315 | return; | |
316 | } | |
317 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
318 | ASPEED_SOC_WDT_BASE + i * 0x20); | |
013befe1 | 319 | } |
ea337c65 CLG |
320 | |
321 | /* Net */ | |
322 | qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]); | |
323 | object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err); | |
324 | object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized", | |
325 | &local_err); | |
326 | error_propagate(&err, local_err); | |
327 | if (err) { | |
328 | error_propagate(errp, err); | |
329 | return; | |
330 | } | |
331 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE); | |
332 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, | |
333 | qdev_get_gpio_in(DEVICE(&s->vic), 2)); | |
43e3346e AJ |
334 | } |
335 | ||
ff90606f | 336 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
337 | { |
338 | DeviceClass *dc = DEVICE_CLASS(oc); | |
b033271f | 339 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
43e3346e | 340 | |
b033271f | 341 | sc->info = (AspeedSoCInfo *) data; |
ff90606f | 342 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
343 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
344 | dc->user_creatable = false; | |
43e3346e AJ |
345 | } |
346 | ||
ff90606f | 347 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
348 | .name = TYPE_ASPEED_SOC, |
349 | .parent = TYPE_DEVICE, | |
350 | .instance_init = aspeed_soc_init, | |
351 | .instance_size = sizeof(AspeedSoCState), | |
352 | .class_size = sizeof(AspeedSoCClass), | |
353 | .abstract = true, | |
43e3346e AJ |
354 | }; |
355 | ||
ff90606f | 356 | static void aspeed_soc_register_types(void) |
43e3346e | 357 | { |
b033271f CLG |
358 | int i; |
359 | ||
ff90606f | 360 | type_register_static(&aspeed_soc_type_info); |
b033271f CLG |
361 | for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) { |
362 | TypeInfo ti = { | |
363 | .name = aspeed_socs[i].name, | |
364 | .parent = TYPE_ASPEED_SOC, | |
365 | .class_init = aspeed_soc_class_init, | |
366 | .class_data = (void *) &aspeed_socs[i], | |
367 | }; | |
368 | type_register(&ti); | |
369 | } | |
43e3346e AJ |
370 | } |
371 | ||
ff90606f | 372 | type_init(aspeed_soc_register_types) |