[mirror_qemu.git] / hw / arm / aspeed_soc.c

/*
 * ASPEED SoC family
 *
 * Andrew Jeffery <andrew@aj.id.au>
 * Jeremy Kerr <jk@ozlabs.org>
 *
 * Copyright 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "hw/i2c/aspeed_i2c.h"

#define ASPEED_SOC_UART_5_BASE      0x00184000
#define ASPEED_SOC_IOMEM_SIZE       0x00200000
#define ASPEED_SOC_IOMEM_BASE       0x1E600000
#define ASPEED_SOC_FMC_BASE         0x1E620000
#define ASPEED_SOC_SPI_BASE         0x1E630000
#define ASPEED_SOC_SPI2_BASE        0x1E631000
#define ASPEED_SOC_VIC_BASE         0x1E6C0000
#define ASPEED_SOC_SDMC_BASE        0x1E6E0000
#define ASPEED_SOC_SCU_BASE         0x1E6E2000
#define ASPEED_SOC_SRAM_BASE        0x1E720000
#define ASPEED_SOC_TIMER_BASE       0x1E782000
#define ASPEED_SOC_I2C_BASE         0x1E78A000

static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };

#define AST2400_SDRAM_BASE       0x40000000
#define AST2500_SDRAM_BASE       0x80000000

static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };

static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
                                                       ASPEED_SOC_SPI2_BASE};
static const char *aspeed_soc_ast2500_typenames[] = {
    "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };

static const AspeedSoCInfo aspeed_socs[] = {
    {
        .name         = "ast2400-a0",
        .cpu_model    = "arm926",
        .silicon_rev  = AST2400_A0_SILICON_REV,
        .sdram_base   = AST2400_SDRAM_BASE,
        .sram_size    = 0x8000,
        .spis_num     = 1,
        .spi_bases    = aspeed_soc_ast2400_spi_bases,
        .fmc_typename = "aspeed.smc.fmc",
        .spi_typename = aspeed_soc_ast2400_typenames,
    }, {
        .name         = "ast2400-a1",
        .cpu_model    = "arm926",
        .silicon_rev  = AST2400_A1_SILICON_REV,
        .sdram_base   = AST2400_SDRAM_BASE,
        .sram_size    = 0x8000,
        .spis_num     = 1,
        .spi_bases    = aspeed_soc_ast2400_spi_bases,
        .fmc_typename = "aspeed.smc.fmc",
        .spi_typename = aspeed_soc_ast2400_typenames,
    }, {
        .name         = "ast2400",
        .cpu_model    = "arm926",
        .silicon_rev  = AST2400_A0_SILICON_REV,
        .sdram_base   = AST2400_SDRAM_BASE,
        .sram_size    = 0x8000,
        .spis_num     = 1,
        .spi_bases    = aspeed_soc_ast2400_spi_bases,
        .fmc_typename = "aspeed.smc.fmc",
        .spi_typename = aspeed_soc_ast2400_typenames,
    }, {
        .name         = "ast2500-a1",
        .cpu_model    = "arm1176",
        .silicon_rev  = AST2500_A1_SILICON_REV,
        .sdram_base   = AST2500_SDRAM_BASE,
        .sram_size    = 0x9000,
        .spis_num     = 2,
        .spi_bases    = aspeed_soc_ast2500_spi_bases,
        .fmc_typename = "aspeed.smc.ast2500-fmc",
        .spi_typename = aspeed_soc_ast2500_typenames,
    },
};

/*
 * IO handlers: simply catch any reads/writes to IO addresses that aren't
 * handled by a device mapping.
 */

static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
                  __func__, offset, size);
    return 0;
}

static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
                unsigned size)
{
    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
                  __func__, offset, value, size);
}

static const MemoryRegionOps aspeed_soc_io_ops = {
    .read = aspeed_soc_io_read,
    .write = aspeed_soc_io_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void aspeed_soc_init(Object *obj)
{
    AspeedSoCState *s = ASPEED_SOC(obj);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    char *cpu_typename;
    int i;

    cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
    object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
    object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
    g_free(cpu_typename);

    object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
    object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
    qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());

    object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
    object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
    qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());

    object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
    object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
    qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());

    object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
    object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
    qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
                         sc->info->silicon_rev);
    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                              "hw-strap1", &error_abort);
    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
                              "hw-strap2", &error_abort);

    object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
    object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
    qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());

    for (i = 0; i < sc->info->spis_num; i++) {
        object_initialize(&s->spi[i], sizeof(s->spi[i]),
                          sc->info->spi_typename[i]);
        object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
    }

    object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
    object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
    qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
    qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
                         sc->info->silicon_rev);
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                              "ram-size", &error_abort);
}

static void aspeed_soc_realize(DeviceState *dev, Error **errp)
{
    int i;
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    Error *err = NULL, *local_err = NULL;

    /* IO space */
    memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
            "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
    memory_region_add_subregion_overlap(get_system_memory(),
                                        ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);

    /* CPU */
    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    /* SRAM */
    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
                           sc->info->sram_size, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    vmstate_register_ram_global(&s->sram);
    memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
                                &s->sram);

    /* VIC */
    object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    /* Timer */
    object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
    for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
    }

    /* SCU */
    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);

    /* UART - attach an 8250 to the IO space as our UART5 */
    if (serial_hds[0]) {
        qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
        serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
                       uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
    }

    /* I2C */
    object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
                       qdev_get_gpio_in(DEVICE(&s->vic), 12));

    /* FMC */
    object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err);
    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);
    error_propagate(&err, local_err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
                    s->fmc.ctrl->flash_window_base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
                       qdev_get_gpio_in(DEVICE(&s->vic), 19));

    /* SPI */
    for (i = 0; i < sc->info->spis_num; i++) {
        object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
                        s->spi[i].ctrl->flash_window_base);
    }

    /* SDMC - SDRAM Memory Controller */
    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
}

static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    sc->info = (AspeedSoCInfo *) data;
    dc->realize = aspeed_soc_realize;
}

static const TypeInfo aspeed_soc_type_info = {
    .name           = TYPE_ASPEED_SOC,
    .parent         = TYPE_DEVICE,
    .instance_init  = aspeed_soc_init,
    .instance_size  = sizeof(AspeedSoCState),
    .class_size     = sizeof(AspeedSoCClass),
    .abstract       = true,
};

static void aspeed_soc_register_types(void)
{
    int i;

    type_register_static(&aspeed_soc_type_info);
    for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
        TypeInfo ti = {
            .name       = aspeed_socs[i].name,
            .parent     = TYPE_ASPEED_SOC,
            .class_init = aspeed_soc_class_init,
            .class_data = (void *) &aspeed_socs[i],
        };
        type_register(&ti);
    }
}

type_init(aspeed_soc_register_types)
Commit	Line	Data
43e3346e	1	/*
ff90606f	2	* ASPEED SoC family
43e3346e AJ	3	*
	4	* Andrew Jeffery <andrew@aj.id.au>
	5	* Jeremy Kerr <jk@ozlabs.org>
	6	*
	7	* Copyright 2016 IBM Corp.
	8	*
	9	* This code is licensed under the GPL version 2 or later. See
	10	* the COPYING file in the top-level directory.
	11	*/
	12
	13	#include "qemu/osdep.h"
da34e65c	14	#include "qapi/error.h"
4771d756 PB	15	#include "qemu-common.h"
4771d756 PB	16	#include "cpu.h"
43e3346e	17	#include "exec/address-spaces.h"
00442402	18	#include "hw/arm/aspeed_soc.h"
43e3346e	19	#include "hw/char/serial.h"
03dd024f	20	#include "qemu/log.h"
16020011	21	#include "hw/i2c/aspeed_i2c.h"
43e3346e	22
ff90606f CLG	23	#define ASPEED_SOC_UART_5_BASE 0x00184000
	24	#define ASPEED_SOC_IOMEM_SIZE 0x00200000
	25	#define ASPEED_SOC_IOMEM_BASE 0x1E600000
	26	#define ASPEED_SOC_FMC_BASE 0x1E620000
	27	#define ASPEED_SOC_SPI_BASE 0x1E630000
6dc52326	28	#define ASPEED_SOC_SPI2_BASE 0x1E631000
ff90606f CLG	29	#define ASPEED_SOC_VIC_BASE 0x1E6C0000
	30	#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
	31	#define ASPEED_SOC_SCU_BASE 0x1E6E2000
74af4eec	32	#define ASPEED_SOC_SRAM_BASE 0x1E720000
ff90606f CLG	33	#define ASPEED_SOC_TIMER_BASE 0x1E782000
	34	#define ASPEED_SOC_I2C_BASE 0x1E78A000
	35
43e3346e AJ	36	static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
	37	static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
	38
b033271f	39	#define AST2400_SDRAM_BASE 0x40000000
365aff1e	40	#define AST2500_SDRAM_BASE 0x80000000
b033271f	41
dbcabeeb	42	static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
6dc52326	43	static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
dbcabeeb	44
6dc52326 CLG	45	static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
	46	ASPEED_SOC_SPI2_BASE};
	47	static const char *aspeed_soc_ast2500_typenames[] = {
	48	"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
dbcabeeb	49
b033271f	50	static const AspeedSoCInfo aspeed_socs[] = {
74af4eec CLG	51	{
	52	.name = "ast2400-a0",
	53	.cpu_model = "arm926",
	54	.silicon_rev = AST2400_A0_SILICON_REV,
	55	.sdram_base = AST2400_SDRAM_BASE,
	56	.sram_size = 0x8000,
	57	.spis_num = 1,
	58	.spi_bases = aspeed_soc_ast2400_spi_bases,
	59	.fmc_typename = "aspeed.smc.fmc",
	60	.spi_typename = aspeed_soc_ast2400_typenames,
6efbac90 CLG	61	}, {
	62	.name = "ast2400-a1",
	63	.cpu_model = "arm926",
	64	.silicon_rev = AST2400_A1_SILICON_REV,
	65	.sdram_base = AST2400_SDRAM_BASE,
	66	.sram_size = 0x8000,
	67	.spis_num = 1,
	68	.spi_bases = aspeed_soc_ast2400_spi_bases,
	69	.fmc_typename = "aspeed.smc.fmc",
	70	.spi_typename = aspeed_soc_ast2400_typenames,
74af4eec CLG	71	}, {
	72	.name = "ast2400",
	73	.cpu_model = "arm926",
	74	.silicon_rev = AST2400_A0_SILICON_REV,
	75	.sdram_base = AST2400_SDRAM_BASE,
	76	.sram_size = 0x8000,
	77	.spis_num = 1,
	78	.spi_bases = aspeed_soc_ast2400_spi_bases,
	79	.fmc_typename = "aspeed.smc.fmc",
	80	.spi_typename = aspeed_soc_ast2400_typenames,
	81	}, {
	82	.name = "ast2500-a1",
	83	.cpu_model = "arm1176",
	84	.silicon_rev = AST2500_A1_SILICON_REV,
	85	.sdram_base = AST2500_SDRAM_BASE,
	86	.sram_size = 0x9000,
	87	.spis_num = 2,
	88	.spi_bases = aspeed_soc_ast2500_spi_bases,
	89	.fmc_typename = "aspeed.smc.ast2500-fmc",
	90	.spi_typename = aspeed_soc_ast2500_typenames,
	91	},
b033271f CLG	92	};
b033271f CLG	93
43e3346e AJ	94	/*
	95	* IO handlers: simply catch any reads/writes to IO addresses that aren't
	96	* handled by a device mapping.
	97	*/
	98
ff90606f	99	static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
43e3346e AJ	100	{
	101	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
	102	__func__, offset, size);
	103	return 0;
	104	}
	105
ff90606f	106	static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
43e3346e AJ	107	unsigned size)
	108	{
	109	qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
	110	__func__, offset, value, size);
	111	}
	112
ff90606f CLG	113	static const MemoryRegionOps aspeed_soc_io_ops = {
	114	.read = aspeed_soc_io_read,
	115	.write = aspeed_soc_io_write,
43e3346e AJ	116	.endianness = DEVICE_LITTLE_ENDIAN,
	117	};
	118
ff90606f	119	static void aspeed_soc_init(Object *obj)
43e3346e	120	{
ff90606f	121	AspeedSoCState *s = ASPEED_SOC(obj);
b033271f	122	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
2d105bd6	123	char *cpu_typename;
dbcabeeb	124	int i;
43e3346e	125
2d105bd6 CLG	126	cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
	127	object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
	128	object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
	129	g_free(cpu_typename);
43e3346e AJ	130
	131	object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
	132	object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
	133	qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
	134
	135	object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
	136	object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
	137	qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
16020011 CLG	138
	139	object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
	140	object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
	141	qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
334973bb AJ	142
	143	object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
	144	object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
	145	qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
	146	qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
b033271f	147	sc->info->silicon_rev);
334973bb AJ	148	object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
	149	"hw-strap1", &error_abort);
	150	object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
	151	"hw-strap2", &error_abort);
7c1c69bc	152
6dc52326	153	object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
0e5803df CLG	154	object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
0e5803df CLG	155	qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
7c1c69bc	156
dbcabeeb	157	for (i = 0; i < sc->info->spis_num; i++) {
6dc52326 CLG	158	object_initialize(&s->spi[i], sizeof(s->spi[i]),
6dc52326 CLG	159	sc->info->spi_typename[i]);
bd673bd8	160	object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
dbcabeeb CLG	161	qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
dbcabeeb CLG	162	}
c2da8a8b CLG	163
	164	object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
	165	object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
	166	qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
	167	qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
b033271f	168	sc->info->silicon_rev);
c6c7cfb0 CLG	169	object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
c6c7cfb0 CLG	170	"ram-size", &error_abort);
43e3346e AJ	171	}
43e3346e AJ	172
ff90606f	173	static void aspeed_soc_realize(DeviceState dev, Error *errp)
43e3346e AJ	174	{
43e3346e AJ	175	int i;
ff90606f	176	AspeedSoCState *s = ASPEED_SOC(dev);
dbcabeeb	177	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
7c1c69bc	178	Error err = NULL, local_err = NULL;
43e3346e AJ	179
43e3346e AJ	180	/* IO space */
ff90606f CLG	181	memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
	182	"aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
	183	memory_region_add_subregion_overlap(get_system_memory(),
	184	ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
43e3346e	185
2d105bd6 CLG	186	/* CPU */
	187	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	188	if (err) {
	189	error_propagate(errp, err);
	190	return;
	191	}
	192
74af4eec CLG	193	/* SRAM */
	194	memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
	195	sc->info->sram_size, &err);
	196	if (err) {
	197	error_propagate(errp, err);
	198	return;
	199	}
	200	vmstate_register_ram_global(&s->sram);
	201	memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
	202	&s->sram);
	203
43e3346e AJ	204	/* VIC */
	205	object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
	206	if (err) {
	207	error_propagate(errp, err);
	208	return;
	209	}
ff90606f	210	sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
43e3346e	211	sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
2d105bd6	212	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
43e3346e	213	sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
2d105bd6	214	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
43e3346e AJ	215
	216	/* Timer */
	217	object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
	218	if (err) {
	219	error_propagate(errp, err);
	220	return;
	221	}
ff90606f	222	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
43e3346e AJ	223	for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
	224	qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
	225	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
	226	}
	227
334973bb AJ	228	/* SCU */
	229	object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
	230	if (err) {
	231	error_propagate(errp, err);
	232	return;
	233	}
ff90606f	234	sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
334973bb	235
43e3346e AJ	236	/* UART - attach an 8250 to the IO space as our UART5 */
	237	if (serial_hds[0]) {
	238	qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
ff90606f	239	serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
43e3346e AJ	240	uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
43e3346e AJ	241	}
16020011 CLG	242
	243	/* I2C */
	244	object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
	245	if (err) {
	246	error_propagate(errp, err);
	247	return;
	248	}
ff90606f	249	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
16020011 CLG	250	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
16020011 CLG	251	qdev_get_gpio_in(DEVICE(&s->vic), 12));
7c1c69bc	252
0e5803df CLG	253	/* FMC */
	254	object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err);
	255	object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);
7c1c69bc CLG	256	error_propagate(&err, local_err);
	257	if (err) {
	258	error_propagate(errp, err);
	259	return;
	260	}
0e5803df	261	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
dcb83444 CLG	262	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
dcb83444 CLG	263	s->fmc.ctrl->flash_window_base);
0e5803df	264	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
7c1c69bc CLG	265	qdev_get_gpio_in(DEVICE(&s->vic), 19));
	266
	267	/* SPI */
dbcabeeb CLG	268	for (i = 0; i < sc->info->spis_num; i++) {
	269	object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
	270	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
	271	&local_err);
	272	error_propagate(&err, local_err);
	273	if (err) {
	274	error_propagate(errp, err);
	275	return;
	276	}
	277	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
	278	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
	279	s->spi[i].ctrl->flash_window_base);
7c1c69bc	280	}
c2da8a8b CLG	281
	282	/* SDMC - SDRAM Memory Controller */
	283	object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
	284	if (err) {
	285	error_propagate(errp, err);
	286	return;
	287	}
ff90606f	288	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
43e3346e AJ	289	}
43e3346e AJ	290
ff90606f	291	static void aspeed_soc_class_init(ObjectClass oc, void data)
43e3346e AJ	292	{
43e3346e AJ	293	DeviceClass *dc = DEVICE_CLASS(oc);
b033271f	294	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
43e3346e	295
b033271f	296	sc->info = (AspeedSoCInfo *) data;
ff90606f	297	dc->realize = aspeed_soc_realize;
43e3346e AJ	298	}
43e3346e AJ	299
ff90606f	300	static const TypeInfo aspeed_soc_type_info = {
b033271f CLG	301	.name = TYPE_ASPEED_SOC,
	302	.parent = TYPE_DEVICE,
	303	.instance_init = aspeed_soc_init,
	304	.instance_size = sizeof(AspeedSoCState),
	305	.class_size = sizeof(AspeedSoCClass),
	306	.abstract = true,
43e3346e AJ	307	};
43e3346e AJ	308
ff90606f	309	static void aspeed_soc_register_types(void)
43e3346e	310	{
b033271f CLG	311	int i;
b033271f CLG	312
ff90606f	313	type_register_static(&aspeed_soc_type_info);
b033271f CLG	314	for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
	315	TypeInfo ti = {
	316	.name = aspeed_socs[i].name,
	317	.parent = TYPE_ASPEED_SOC,
	318	.class_init = aspeed_soc_class_init,
	319	.class_data = (void *) &aspeed_socs[i],
	320	};
	321	type_register(&ti);
	322	}
43e3346e AJ	323	}
43e3346e AJ	324
ff90606f	325	type_init(aspeed_soc_register_types)