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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "cpu.h" |
43e3346e | 16 | #include "exec/address-spaces.h" |
c7c3c9f8 | 17 | #include "hw/misc/unimp.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 19 | #include "hw/char/serial.h" |
03dd024f | 20 | #include "qemu/log.h" |
0b8fa32f | 21 | #include "qemu/module.h" |
ece09bee | 22 | #include "qemu/error-report.h" |
16020011 | 23 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 24 | #include "net/net.h" |
46517dd4 | 25 | #include "sysemu/sysemu.h" |
43e3346e | 26 | |
ff90606f | 27 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
28 | |
29 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
30 | [ASPEED_IOMEM] = 0x1E600000, | |
31 | [ASPEED_FMC] = 0x1E620000, | |
32 | [ASPEED_SPI1] = 0x1E630000, | |
33 | [ASPEED_VIC] = 0x1E6C0000, | |
34 | [ASPEED_SDMC] = 0x1E6E0000, | |
35 | [ASPEED_SCU] = 0x1E6E2000, | |
118c82e7 | 36 | [ASPEED_XDMA] = 0x1E6E7000, |
d783d1fe CLG |
37 | [ASPEED_ADC] = 0x1E6E9000, |
38 | [ASPEED_SRAM] = 0x1E720000, | |
2bea128c | 39 | [ASPEED_SDHCI] = 0x1E740000, |
d783d1fe CLG |
40 | [ASPEED_GPIO] = 0x1E780000, |
41 | [ASPEED_RTC] = 0x1E781000, | |
42 | [ASPEED_TIMER1] = 0x1E782000, | |
43 | [ASPEED_WDT] = 0x1E785000, | |
44 | [ASPEED_PWM] = 0x1E786000, | |
45 | [ASPEED_LPC] = 0x1E789000, | |
46 | [ASPEED_IBT] = 0x1E789140, | |
47 | [ASPEED_I2C] = 0x1E78A000, | |
48 | [ASPEED_ETH1] = 0x1E660000, | |
49 | [ASPEED_ETH2] = 0x1E680000, | |
50 | [ASPEED_UART1] = 0x1E783000, | |
51 | [ASPEED_UART5] = 0x1E784000, | |
52 | [ASPEED_VUART] = 0x1E787000, | |
53 | [ASPEED_SDRAM] = 0x40000000, | |
54 | }; | |
55 | ||
56 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
57 | [ASPEED_IOMEM] = 0x1E600000, | |
58 | [ASPEED_FMC] = 0x1E620000, | |
59 | [ASPEED_SPI1] = 0x1E630000, | |
60 | [ASPEED_SPI2] = 0x1E631000, | |
61 | [ASPEED_VIC] = 0x1E6C0000, | |
62 | [ASPEED_SDMC] = 0x1E6E0000, | |
63 | [ASPEED_SCU] = 0x1E6E2000, | |
118c82e7 | 64 | [ASPEED_XDMA] = 0x1E6E7000, |
d783d1fe CLG |
65 | [ASPEED_ADC] = 0x1E6E9000, |
66 | [ASPEED_SRAM] = 0x1E720000, | |
2bea128c | 67 | [ASPEED_SDHCI] = 0x1E740000, |
d783d1fe CLG |
68 | [ASPEED_GPIO] = 0x1E780000, |
69 | [ASPEED_RTC] = 0x1E781000, | |
70 | [ASPEED_TIMER1] = 0x1E782000, | |
71 | [ASPEED_WDT] = 0x1E785000, | |
72 | [ASPEED_PWM] = 0x1E786000, | |
73 | [ASPEED_LPC] = 0x1E789000, | |
74 | [ASPEED_IBT] = 0x1E789140, | |
75 | [ASPEED_I2C] = 0x1E78A000, | |
76 | [ASPEED_ETH1] = 0x1E660000, | |
77 | [ASPEED_ETH2] = 0x1E680000, | |
78 | [ASPEED_UART1] = 0x1E783000, | |
79 | [ASPEED_UART5] = 0x1E784000, | |
80 | [ASPEED_VUART] = 0x1E787000, | |
81 | [ASPEED_SDRAM] = 0x80000000, | |
82 | }; | |
ff90606f | 83 | |
b456b113 CLG |
84 | static const int aspeed_soc_ast2400_irqmap[] = { |
85 | [ASPEED_UART1] = 9, | |
86 | [ASPEED_UART2] = 32, | |
87 | [ASPEED_UART3] = 33, | |
88 | [ASPEED_UART4] = 34, | |
89 | [ASPEED_UART5] = 10, | |
90 | [ASPEED_VUART] = 8, | |
91 | [ASPEED_FMC] = 19, | |
92 | [ASPEED_SDMC] = 0, | |
93 | [ASPEED_SCU] = 21, | |
94 | [ASPEED_ADC] = 31, | |
95 | [ASPEED_GPIO] = 20, | |
96 | [ASPEED_RTC] = 22, | |
97 | [ASPEED_TIMER1] = 16, | |
98 | [ASPEED_TIMER2] = 17, | |
99 | [ASPEED_TIMER3] = 18, | |
100 | [ASPEED_TIMER4] = 35, | |
101 | [ASPEED_TIMER5] = 36, | |
102 | [ASPEED_TIMER6] = 37, | |
103 | [ASPEED_TIMER7] = 38, | |
104 | [ASPEED_TIMER8] = 39, | |
105 | [ASPEED_WDT] = 27, | |
106 | [ASPEED_PWM] = 28, | |
107 | [ASPEED_LPC] = 8, | |
108 | [ASPEED_IBT] = 8, /* LPC */ | |
109 | [ASPEED_I2C] = 12, | |
110 | [ASPEED_ETH1] = 2, | |
111 | [ASPEED_ETH2] = 3, | |
118c82e7 | 112 | [ASPEED_XDMA] = 6, |
2bea128c | 113 | [ASPEED_SDHCI] = 26, |
b456b113 | 114 | }; |
43e3346e | 115 | |
b456b113 CLG |
116 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
117 | ||
b033271f | 118 | static const AspeedSoCInfo aspeed_socs[] = { |
74af4eec | 119 | { |
6efbac90 | 120 | .name = "ast2400-a1", |
ba1ba5cc | 121 | .cpu_type = ARM_CPU_TYPE_NAME("arm926"), |
6efbac90 | 122 | .silicon_rev = AST2400_A1_SILICON_REV, |
6efbac90 CLG |
123 | .sram_size = 0x8000, |
124 | .spis_num = 1, | |
f986ee1d | 125 | .wdts_num = 2, |
b456b113 | 126 | .irqmap = aspeed_soc_ast2400_irqmap, |
d783d1fe | 127 | .memmap = aspeed_soc_ast2400_memmap, |
ece09bee | 128 | .num_cpus = 1, |
74af4eec CLG |
129 | }, { |
130 | .name = "ast2500-a1", | |
ba1ba5cc | 131 | .cpu_type = ARM_CPU_TYPE_NAME("arm1176"), |
74af4eec | 132 | .silicon_rev = AST2500_A1_SILICON_REV, |
74af4eec CLG |
133 | .sram_size = 0x9000, |
134 | .spis_num = 2, | |
f986ee1d | 135 | .wdts_num = 3, |
b456b113 | 136 | .irqmap = aspeed_soc_ast2500_irqmap, |
d783d1fe | 137 | .memmap = aspeed_soc_ast2500_memmap, |
ece09bee | 138 | .num_cpus = 1, |
74af4eec | 139 | }, |
b033271f CLG |
140 | }; |
141 | ||
b456b113 CLG |
142 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) |
143 | { | |
144 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
145 | ||
146 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]); | |
147 | } | |
148 | ||
ff90606f | 149 | static void aspeed_soc_init(Object *obj) |
43e3346e | 150 | { |
ff90606f | 151 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 152 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 153 | int i; |
811a5b1d CLG |
154 | char socname[8]; |
155 | char typename[64]; | |
156 | ||
157 | if (sscanf(sc->info->name, "%7s", socname) != 1) { | |
158 | g_assert_not_reached(); | |
159 | } | |
43e3346e | 160 | |
ece09bee CLG |
161 | for (i = 0; i < sc->info->num_cpus; i++) { |
162 | object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), | |
163 | sizeof(s->cpu[i]), sc->info->cpu_type, | |
164 | &error_abort, NULL); | |
165 | } | |
43e3346e | 166 | |
9a937f6c | 167 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
1b0ad567 | 168 | sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), |
9a937f6c | 169 | typename); |
334973bb | 170 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
b033271f | 171 | sc->info->silicon_rev); |
334973bb AJ |
172 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
173 | "hw-strap1", &error_abort); | |
174 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), | |
175 | "hw-strap2", &error_abort); | |
b6e70d1d JS |
176 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
177 | "hw-prot-key", &error_abort); | |
7c1c69bc | 178 | |
1b0ad567 PMD |
179 | sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic), |
180 | TYPE_ASPEED_VIC); | |
e2a11ca8 | 181 | |
75fb4577 JS |
182 | sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), |
183 | TYPE_ASPEED_RTC); | |
184 | ||
72d96f8e | 185 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
1b0ad567 | 186 | sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), |
72d96f8e | 187 | sizeof(s->timerctrl), typename); |
9b945a9e CLG |
188 | object_property_add_const_link(OBJECT(&s->timerctrl), "scu", |
189 | OBJECT(&s->scu), &error_abort); | |
e2a11ca8 | 190 | |
1b0ad567 PMD |
191 | sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), |
192 | TYPE_ASPEED_I2C); | |
e2a11ca8 | 193 | |
811a5b1d | 194 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
1b0ad567 | 195 | sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), |
811a5b1d | 196 | typename); |
26d5df95 CLG |
197 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", |
198 | &error_abort); | |
c4e1f0b4 CLG |
199 | object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", |
200 | &error_abort); | |
7c1c69bc | 201 | |
dbcabeeb | 202 | for (i = 0; i < sc->info->spis_num; i++) { |
811a5b1d | 203 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
1b0ad567 | 204 | sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), |
811a5b1d | 205 | sizeof(s->spi[i]), typename); |
dbcabeeb | 206 | } |
c2da8a8b | 207 | |
8e00d1a9 | 208 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
1b0ad567 | 209 | sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), |
8e00d1a9 | 210 | typename); |
c6c7cfb0 CLG |
211 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
212 | "ram-size", &error_abort); | |
ebe31c0a CLG |
213 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
214 | "max-ram-size", &error_abort); | |
013befe1 | 215 | |
f986ee1d | 216 | for (i = 0; i < sc->info->wdts_num; i++) { |
1b0ad567 PMD |
217 | sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), |
218 | sizeof(s->wdt[i]), TYPE_ASPEED_WDT); | |
429789cc AJ |
219 | qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", |
220 | sc->info->silicon_rev); | |
3059c2f5 JS |
221 | object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", |
222 | OBJECT(&s->scu), &error_abort); | |
f986ee1d | 223 | } |
ea337c65 | 224 | |
67340990 CLG |
225 | for (i = 0; i < ASPEED_MACS_NUM; i++) { |
226 | sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), | |
227 | sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); | |
228 | } | |
118c82e7 EJ |
229 | |
230 | sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), | |
231 | TYPE_ASPEED_XDMA); | |
fdcc7c06 | 232 | |
811a5b1d | 233 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
fdcc7c06 | 234 | sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), |
811a5b1d | 235 | typename); |
2bea128c EJ |
236 | |
237 | sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), | |
238 | TYPE_ASPEED_SDHCI); | |
239 | ||
240 | /* Init sd card slot class here so that they're under the correct parent */ | |
241 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
242 | sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), | |
243 | sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); | |
244 | } | |
43e3346e AJ |
245 | } |
246 | ||
ff90606f | 247 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
248 | { |
249 | int i; | |
ff90606f | 250 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 251 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
7c1c69bc | 252 | Error *err = NULL, *local_err = NULL; |
43e3346e AJ |
253 | |
254 | /* IO space */ | |
d783d1fe CLG |
255 | create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM], |
256 | ASPEED_SOC_IOMEM_SIZE); | |
43e3346e | 257 | |
ece09bee CLG |
258 | if (s->num_cpus > sc->info->num_cpus) { |
259 | warn_report("%s: invalid number of CPUs %d, using default %d", | |
260 | sc->info->name, s->num_cpus, sc->info->num_cpus); | |
261 | s->num_cpus = sc->info->num_cpus; | |
262 | } | |
263 | ||
2d105bd6 | 264 | /* CPU */ |
ece09bee CLG |
265 | for (i = 0; i < s->num_cpus; i++) { |
266 | object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); | |
267 | if (err) { | |
268 | error_propagate(errp, err); | |
269 | return; | |
270 | } | |
2d105bd6 CLG |
271 | } |
272 | ||
74af4eec | 273 | /* SRAM */ |
a2e9989c | 274 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", |
74af4eec CLG |
275 | sc->info->sram_size, &err); |
276 | if (err) { | |
277 | error_propagate(errp, err); | |
278 | return; | |
279 | } | |
d783d1fe CLG |
280 | memory_region_add_subregion(get_system_memory(), |
281 | sc->info->memmap[ASPEED_SRAM], &s->sram); | |
74af4eec | 282 | |
e2a11ca8 CLG |
283 | /* SCU */ |
284 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
285 | if (err) { | |
286 | error_propagate(errp, err); | |
287 | return; | |
288 | } | |
d783d1fe | 289 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]); |
e2a11ca8 | 290 | |
43e3346e AJ |
291 | /* VIC */ |
292 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | |
293 | if (err) { | |
294 | error_propagate(errp, err); | |
295 | return; | |
296 | } | |
d783d1fe | 297 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]); |
43e3346e | 298 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 299 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 300 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 301 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e | 302 | |
75fb4577 JS |
303 | /* RTC */ |
304 | object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); | |
305 | if (err) { | |
306 | error_propagate(errp, err); | |
307 | return; | |
308 | } | |
309 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]); | |
310 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, | |
311 | aspeed_soc_get_irq(s, ASPEED_RTC)); | |
312 | ||
43e3346e AJ |
313 | /* Timer */ |
314 | object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | |
315 | if (err) { | |
316 | error_propagate(errp, err); | |
317 | return; | |
318 | } | |
d783d1fe CLG |
319 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, |
320 | sc->info->memmap[ASPEED_TIMER1]); | |
b456b113 CLG |
321 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
322 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | |
43e3346e AJ |
323 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
324 | } | |
325 | ||
326 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
9bca0edb | 327 | if (serial_hd(0)) { |
b456b113 | 328 | qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); |
d783d1fe | 329 | serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2, |
9bca0edb | 330 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); |
43e3346e | 331 | } |
16020011 CLG |
332 | |
333 | /* I2C */ | |
334 | object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); | |
335 | if (err) { | |
336 | error_propagate(errp, err); | |
337 | return; | |
338 | } | |
d783d1fe | 339 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]); |
16020011 | 340 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
b456b113 | 341 | aspeed_soc_get_irq(s, ASPEED_I2C)); |
7c1c69bc | 342 | |
26d5df95 | 343 | /* FMC, The number of CS is set at the board level */ |
6da4433f CLG |
344 | object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM], |
345 | "sdram-base", &err); | |
346 | if (err) { | |
347 | error_propagate(errp, err); | |
348 | return; | |
349 | } | |
26d5df95 | 350 | object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); |
7c1c69bc CLG |
351 | if (err) { |
352 | error_propagate(errp, err); | |
353 | return; | |
354 | } | |
d783d1fe | 355 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]); |
dcb83444 CLG |
356 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
357 | s->fmc.ctrl->flash_window_base); | |
0e5803df | 358 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
b456b113 | 359 | aspeed_soc_get_irq(s, ASPEED_FMC)); |
7c1c69bc CLG |
360 | |
361 | /* SPI */ | |
dbcabeeb CLG |
362 | for (i = 0; i < sc->info->spis_num; i++) { |
363 | object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); | |
364 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | |
365 | &local_err); | |
366 | error_propagate(&err, local_err); | |
367 | if (err) { | |
368 | error_propagate(errp, err); | |
369 | return; | |
370 | } | |
d783d1fe CLG |
371 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
372 | sc->info->memmap[ASPEED_SPI1 + i]); | |
dbcabeeb CLG |
373 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
374 | s->spi[i].ctrl->flash_window_base); | |
7c1c69bc | 375 | } |
c2da8a8b CLG |
376 | |
377 | /* SDMC - SDRAM Memory Controller */ | |
378 | object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); | |
379 | if (err) { | |
380 | error_propagate(errp, err); | |
381 | return; | |
382 | } | |
d783d1fe | 383 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]); |
013befe1 CLG |
384 | |
385 | /* Watch dog */ | |
f986ee1d JS |
386 | for (i = 0; i < sc->info->wdts_num; i++) { |
387 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); | |
388 | if (err) { | |
389 | error_propagate(errp, err); | |
390 | return; | |
391 | } | |
392 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
d783d1fe | 393 | sc->info->memmap[ASPEED_WDT] + i * 0x20); |
013befe1 | 394 | } |
ea337c65 CLG |
395 | |
396 | /* Net */ | |
67340990 CLG |
397 | for (i = 0; i < nb_nics; i++) { |
398 | qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); | |
399 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", | |
400 | &err); | |
401 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", | |
402 | &local_err); | |
403 | error_propagate(&err, local_err); | |
404 | if (err) { | |
405 | error_propagate(errp, err); | |
406 | return; | |
407 | } | |
408 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
409 | sc->info->memmap[ASPEED_ETH1 + i]); | |
410 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
411 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | |
ea337c65 | 412 | } |
118c82e7 EJ |
413 | |
414 | /* XDMA */ | |
415 | object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); | |
416 | if (err) { | |
417 | error_propagate(errp, err); | |
418 | return; | |
419 | } | |
420 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
421 | sc->info->memmap[ASPEED_XDMA]); | |
422 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, | |
423 | aspeed_soc_get_irq(s, ASPEED_XDMA)); | |
fdcc7c06 RG |
424 | |
425 | /* GPIO */ | |
426 | object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); | |
427 | if (err) { | |
428 | error_propagate(errp, err); | |
429 | return; | |
430 | } | |
431 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); | |
432 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | |
433 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | |
2bea128c EJ |
434 | |
435 | /* SDHCI */ | |
436 | object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); | |
437 | if (err) { | |
438 | error_propagate(errp, err); | |
439 | return; | |
440 | } | |
441 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
442 | sc->info->memmap[ASPEED_SDHCI]); | |
443 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | |
444 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | |
43e3346e | 445 | } |
ece09bee CLG |
446 | static Property aspeed_soc_properties[] = { |
447 | DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), | |
448 | DEFINE_PROP_END_OF_LIST(), | |
449 | }; | |
43e3346e | 450 | |
ff90606f | 451 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
452 | { |
453 | DeviceClass *dc = DEVICE_CLASS(oc); | |
b033271f | 454 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
43e3346e | 455 | |
b033271f | 456 | sc->info = (AspeedSoCInfo *) data; |
ff90606f | 457 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
458 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
459 | dc->user_creatable = false; | |
ece09bee | 460 | dc->props = aspeed_soc_properties; |
43e3346e AJ |
461 | } |
462 | ||
ff90606f | 463 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
464 | .name = TYPE_ASPEED_SOC, |
465 | .parent = TYPE_DEVICE, | |
466 | .instance_init = aspeed_soc_init, | |
467 | .instance_size = sizeof(AspeedSoCState), | |
468 | .class_size = sizeof(AspeedSoCClass), | |
469 | .abstract = true, | |
43e3346e AJ |
470 | }; |
471 | ||
ff90606f | 472 | static void aspeed_soc_register_types(void) |
43e3346e | 473 | { |
b033271f CLG |
474 | int i; |
475 | ||
ff90606f | 476 | type_register_static(&aspeed_soc_type_info); |
b033271f CLG |
477 | for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) { |
478 | TypeInfo ti = { | |
479 | .name = aspeed_socs[i].name, | |
480 | .parent = TYPE_ASPEED_SOC, | |
481 | .class_init = aspeed_soc_class_init, | |
482 | .class_data = (void *) &aspeed_socs[i], | |
483 | }; | |
484 | type_register(&ti); | |
485 | } | |
43e3346e AJ |
486 | } |
487 | ||
ff90606f | 488 | type_init(aspeed_soc_register_types) |