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Commit | Line | Data |
---|---|---|
43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
346160cb | 14 | #include "qemu/units.h" |
da34e65c | 15 | #include "qapi/error.h" |
c7c3c9f8 | 16 | #include "hw/misc/unimp.h" |
00442402 | 17 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 18 | #include "hw/char/serial.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
ece09bee | 20 | #include "qemu/error-report.h" |
16020011 | 21 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 22 | #include "net/net.h" |
46517dd4 | 23 | #include "sysemu/sysemu.h" |
43e3346e | 24 | |
ff90606f | 25 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
26 | |
27 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
347df6f8 EH |
28 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
29 | [ASPEED_DEV_FMC] = 0x1E620000, | |
30 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
31 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
32 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
33 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
34 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 35 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
36 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
37 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
38 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
39 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
40 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
41 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
42 | [ASPEED_DEV_RTC] = 0x1E781000, | |
43 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
44 | [ASPEED_DEV_WDT] = 0x1E785000, | |
45 | [ASPEED_DEV_PWM] = 0x1E786000, | |
46 | [ASPEED_DEV_LPC] = 0x1E789000, | |
47 | [ASPEED_DEV_IBT] = 0x1E789140, | |
48 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
49 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
50 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
51 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
52 | [ASPEED_DEV_UART2] = 0x1E78D000, |
53 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
54 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 EH |
55 | [ASPEED_DEV_UART5] = 0x1E784000, |
56 | [ASPEED_DEV_VUART] = 0x1E787000, | |
57 | [ASPEED_DEV_SDRAM] = 0x40000000, | |
d783d1fe CLG |
58 | }; |
59 | ||
60 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
347df6f8 EH |
61 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
62 | [ASPEED_DEV_FMC] = 0x1E620000, | |
63 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
64 | [ASPEED_DEV_SPI2] = 0x1E631000, | |
65 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
66 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
67 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
68 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
69 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 70 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
71 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
72 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
73 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
74 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
75 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
76 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
77 | [ASPEED_DEV_RTC] = 0x1E781000, | |
78 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
79 | [ASPEED_DEV_WDT] = 0x1E785000, | |
80 | [ASPEED_DEV_PWM] = 0x1E786000, | |
81 | [ASPEED_DEV_LPC] = 0x1E789000, | |
82 | [ASPEED_DEV_IBT] = 0x1E789140, | |
83 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
84 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
85 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
86 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
87 | [ASPEED_DEV_UART2] = 0x1E78D000, |
88 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
89 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 EH |
90 | [ASPEED_DEV_UART5] = 0x1E784000, |
91 | [ASPEED_DEV_VUART] = 0x1E787000, | |
92 | [ASPEED_DEV_SDRAM] = 0x80000000, | |
d783d1fe | 93 | }; |
ff90606f | 94 | |
b456b113 | 95 | static const int aspeed_soc_ast2400_irqmap[] = { |
347df6f8 EH |
96 | [ASPEED_DEV_UART1] = 9, |
97 | [ASPEED_DEV_UART2] = 32, | |
98 | [ASPEED_DEV_UART3] = 33, | |
99 | [ASPEED_DEV_UART4] = 34, | |
100 | [ASPEED_DEV_UART5] = 10, | |
101 | [ASPEED_DEV_VUART] = 8, | |
102 | [ASPEED_DEV_FMC] = 19, | |
103 | [ASPEED_DEV_EHCI1] = 5, | |
104 | [ASPEED_DEV_EHCI2] = 13, | |
105 | [ASPEED_DEV_SDMC] = 0, | |
106 | [ASPEED_DEV_SCU] = 21, | |
107 | [ASPEED_DEV_ADC] = 31, | |
108 | [ASPEED_DEV_GPIO] = 20, | |
109 | [ASPEED_DEV_RTC] = 22, | |
110 | [ASPEED_DEV_TIMER1] = 16, | |
111 | [ASPEED_DEV_TIMER2] = 17, | |
112 | [ASPEED_DEV_TIMER3] = 18, | |
113 | [ASPEED_DEV_TIMER4] = 35, | |
114 | [ASPEED_DEV_TIMER5] = 36, | |
115 | [ASPEED_DEV_TIMER6] = 37, | |
116 | [ASPEED_DEV_TIMER7] = 38, | |
117 | [ASPEED_DEV_TIMER8] = 39, | |
118 | [ASPEED_DEV_WDT] = 27, | |
119 | [ASPEED_DEV_PWM] = 28, | |
120 | [ASPEED_DEV_LPC] = 8, | |
347df6f8 EH |
121 | [ASPEED_DEV_I2C] = 12, |
122 | [ASPEED_DEV_ETH1] = 2, | |
123 | [ASPEED_DEV_ETH2] = 3, | |
124 | [ASPEED_DEV_XDMA] = 6, | |
125 | [ASPEED_DEV_SDHCI] = 26, | |
a3888d75 | 126 | [ASPEED_DEV_HACE] = 4, |
b456b113 | 127 | }; |
43e3346e | 128 | |
b456b113 CLG |
129 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
130 | ||
699db715 | 131 | static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) |
b456b113 CLG |
132 | { |
133 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
134 | ||
699db715 | 135 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]); |
b456b113 CLG |
136 | } |
137 | ||
ff90606f | 138 | static void aspeed_soc_init(Object *obj) |
43e3346e | 139 | { |
ff90606f | 140 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 141 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 142 | int i; |
811a5b1d CLG |
143 | char socname[8]; |
144 | char typename[64]; | |
145 | ||
54ecafb7 | 146 | if (sscanf(sc->name, "%7s", socname) != 1) { |
811a5b1d CLG |
147 | g_assert_not_reached(); |
148 | } | |
43e3346e | 149 | |
54ecafb7 | 150 | for (i = 0; i < sc->num_cpus; i++) { |
9fc7fc4d | 151 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
ece09bee | 152 | } |
43e3346e | 153 | |
9a937f6c | 154 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
db873cc5 | 155 | object_initialize_child(obj, "scu", &s->scu, typename); |
334973bb | 156 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
54ecafb7 | 157 | sc->silicon_rev); |
334973bb | 158 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
d2623129 | 159 | "hw-strap1"); |
334973bb | 160 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 161 | "hw-strap2"); |
b6e70d1d | 162 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 163 | "hw-prot-key"); |
7c1c69bc | 164 | |
db873cc5 | 165 | object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC); |
e2a11ca8 | 166 | |
db873cc5 | 167 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
75fb4577 | 168 | |
72d96f8e | 169 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
db873cc5 | 170 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
e2a11ca8 | 171 | |
199fd623 AJ |
172 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
173 | object_initialize_child(obj, "adc", &s->adc, typename); | |
174 | ||
f7da1aa8 | 175 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 176 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
e2a11ca8 | 177 | |
811a5b1d | 178 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 179 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
7c1c69bc | 180 | |
54ecafb7 | 181 | for (i = 0; i < sc->spis_num; i++) { |
811a5b1d | 182 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
db873cc5 | 183 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
dbcabeeb | 184 | } |
c2da8a8b | 185 | |
bfdd34f1 | 186 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
187 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
188 | TYPE_PLATFORM_EHCI); | |
bfdd34f1 GR |
189 | } |
190 | ||
8e00d1a9 | 191 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 192 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
c6c7cfb0 | 193 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 194 | "ram-size"); |
013befe1 | 195 | |
54ecafb7 | 196 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 197 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
db873cc5 | 198 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f986ee1d | 199 | } |
ea337c65 | 200 | |
d300db02 | 201 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
202 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
203 | TYPE_FTGMAC100); | |
67340990 | 204 | } |
118c82e7 | 205 | |
8efbee28 CLG |
206 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
207 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
fdcc7c06 | 208 | |
811a5b1d | 209 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
db873cc5 | 210 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
2bea128c | 211 | |
db873cc5 | 212 | object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); |
2bea128c | 213 | |
5325cc34 | 214 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 215 | |
2bea128c EJ |
216 | /* Init sd card slot class here so that they're under the correct parent */ |
217 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
218 | object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], |
219 | TYPE_SYSBUS_SDHCI); | |
2bea128c | 220 | } |
2ecf1726 CLG |
221 | |
222 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
223 | |
224 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
225 | object_initialize_child(obj, "hace", &s->hace, typename); | |
43e3346e AJ |
226 | } |
227 | ||
ff90606f | 228 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
229 | { |
230 | int i; | |
ff90606f | 231 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 232 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
123327d1 | 233 | Error *err = NULL; |
43e3346e AJ |
234 | |
235 | /* IO space */ | |
347df6f8 | 236 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], |
d783d1fe | 237 | ASPEED_SOC_IOMEM_SIZE); |
43e3346e | 238 | |
514bcf6f | 239 | /* Video engine stub */ |
347df6f8 | 240 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], |
514bcf6f JS |
241 | 0x1000); |
242 | ||
2d105bd6 | 243 | /* CPU */ |
b7f1a0cb | 244 | for (i = 0; i < sc->num_cpus; i++) { |
e37976d7 | 245 | object_property_set_link(OBJECT(&s->cpu[i]), "memory", |
4dd9d554 | 246 | OBJECT(s->memory), &error_abort); |
668f62ec | 247 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
ece09bee CLG |
248 | return; |
249 | } | |
2d105bd6 CLG |
250 | } |
251 | ||
74af4eec | 252 | /* SRAM */ |
a2e9989c | 253 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", |
54ecafb7 | 254 | sc->sram_size, &err); |
74af4eec CLG |
255 | if (err) { |
256 | error_propagate(errp, err); | |
257 | return; | |
258 | } | |
4dd9d554 | 259 | memory_region_add_subregion(s->memory, |
347df6f8 | 260 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
74af4eec | 261 | |
e2a11ca8 | 262 | /* SCU */ |
668f62ec | 263 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
e2a11ca8 CLG |
264 | return; |
265 | } | |
347df6f8 | 266 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
e2a11ca8 | 267 | |
43e3346e | 268 | /* VIC */ |
668f62ec | 269 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) { |
43e3346e AJ |
270 | return; |
271 | } | |
347df6f8 | 272 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]); |
43e3346e | 273 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 274 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 275 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 276 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e | 277 | |
75fb4577 | 278 | /* RTC */ |
668f62ec | 279 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
75fb4577 JS |
280 | return; |
281 | } | |
347df6f8 | 282 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
75fb4577 | 283 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 284 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
75fb4577 | 285 | |
43e3346e | 286 | /* Timer */ |
5325cc34 MA |
287 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
288 | &error_abort); | |
668f62ec | 289 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
43e3346e AJ |
290 | return; |
291 | } | |
d783d1fe | 292 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, |
347df6f8 | 293 | sc->memmap[ASPEED_DEV_TIMER1]); |
b456b113 | 294 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 295 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
43e3346e AJ |
296 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
297 | } | |
298 | ||
199fd623 AJ |
299 | /* ADC */ |
300 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
301 | return; | |
302 | } | |
303 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); | |
304 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | |
305 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
306 | ||
470253b6 PD |
307 | /* UART */ |
308 | aspeed_soc_uart_init(s); | |
16020011 CLG |
309 | |
310 | /* I2C */ | |
5325cc34 | 311 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 312 | &error_abort); |
668f62ec | 313 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
16020011 CLG |
314 | return; |
315 | } | |
347df6f8 | 316 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
16020011 | 317 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
347df6f8 | 318 | aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); |
7c1c69bc | 319 | |
26d5df95 | 320 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 321 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 322 | &error_abort); |
668f62ec | 323 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
7c1c69bc CLG |
324 | return; |
325 | } | |
347df6f8 | 326 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
dcb83444 | 327 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
30b6852c | 328 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
0e5803df | 329 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 330 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
7c1c69bc CLG |
331 | |
332 | /* SPI */ | |
54ecafb7 | 333 | for (i = 0; i < sc->spis_num; i++) { |
668f62ec | 334 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
dbcabeeb CLG |
335 | return; |
336 | } | |
d783d1fe | 337 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
347df6f8 | 338 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
dbcabeeb | 339 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 340 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
7c1c69bc | 341 | } |
c2da8a8b | 342 | |
bfdd34f1 GR |
343 | /* EHCI */ |
344 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 345 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
bfdd34f1 GR |
346 | return; |
347 | } | |
348 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
347df6f8 | 349 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
bfdd34f1 | 350 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 351 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
bfdd34f1 GR |
352 | } |
353 | ||
c2da8a8b | 354 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 355 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
c2da8a8b CLG |
356 | return; |
357 | } | |
347df6f8 | 358 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); |
013befe1 CLG |
359 | |
360 | /* Watch dog */ | |
54ecafb7 | 361 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d CLG |
362 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
363 | ||
5325cc34 MA |
364 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
365 | &error_abort); | |
668f62ec | 366 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f986ee1d JS |
367 | return; |
368 | } | |
369 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
347df6f8 | 370 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); |
013befe1 | 371 | } |
ea337c65 | 372 | |
346160cb CLG |
373 | /* RAM */ |
374 | if (!aspeed_soc_dram_init(s, errp)) { | |
375 | return; | |
376 | } | |
377 | ||
ea337c65 | 378 | /* Net */ |
d3bad7e7 | 379 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 380 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 381 | &error_abort); |
668f62ec | 382 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 383 | return; |
67340990 CLG |
384 | } |
385 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
347df6f8 | 386 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
67340990 | 387 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 388 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
ea337c65 | 389 | } |
118c82e7 EJ |
390 | |
391 | /* XDMA */ | |
668f62ec | 392 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
118c82e7 EJ |
393 | return; |
394 | } | |
395 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
347df6f8 | 396 | sc->memmap[ASPEED_DEV_XDMA]); |
118c82e7 | 397 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 398 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
fdcc7c06 RG |
399 | |
400 | /* GPIO */ | |
668f62ec | 401 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
fdcc7c06 RG |
402 | return; |
403 | } | |
347df6f8 | 404 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
fdcc7c06 | 405 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 406 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
2bea128c EJ |
407 | |
408 | /* SDHCI */ | |
668f62ec | 409 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
2bea128c EJ |
410 | return; |
411 | } | |
412 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
347df6f8 | 413 | sc->memmap[ASPEED_DEV_SDHCI]); |
2bea128c | 414 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 415 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
2ecf1726 CLG |
416 | |
417 | /* LPC */ | |
418 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
419 | return; | |
420 | } | |
421 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
c59f781e AJ |
422 | |
423 | /* Connect the LPC IRQ to the VIC */ | |
2ecf1726 CLG |
424 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
425 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
426 | |
427 | /* | |
428 | * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the | |
429 | * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by | |
430 | * contrast, on the AST2600, the subdevice IRQs are connected straight to | |
431 | * the GIC). | |
432 | * | |
433 | * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output | |
434 | * to the VIC is at offset 0. | |
435 | */ | |
436 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
437 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); | |
438 | ||
439 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
440 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); | |
441 | ||
442 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
443 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); | |
444 | ||
445 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
446 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); | |
a3888d75 JS |
447 | |
448 | /* HACE */ | |
449 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
450 | &error_abort); | |
451 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
452 | return; | |
453 | } | |
454 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); | |
455 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
456 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
43e3346e | 457 | } |
ece09bee | 458 | static Property aspeed_soc_properties[] = { |
4dd9d554 PD |
459 | DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, |
460 | MemoryRegion *), | |
95b56e17 CLG |
461 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |
462 | MemoryRegion *), | |
5d63d0c7 PD |
463 | DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, |
464 | ASPEED_DEV_UART5), | |
ece09bee CLG |
465 | DEFINE_PROP_END_OF_LIST(), |
466 | }; | |
43e3346e | 467 | |
ff90606f | 468 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
469 | { |
470 | DeviceClass *dc = DEVICE_CLASS(oc); | |
471 | ||
ff90606f | 472 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
473 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
474 | dc->user_creatable = false; | |
4f67d30b | 475 | device_class_set_props(dc, aspeed_soc_properties); |
43e3346e AJ |
476 | } |
477 | ||
ff90606f | 478 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
479 | .name = TYPE_ASPEED_SOC, |
480 | .parent = TYPE_DEVICE, | |
b033271f CLG |
481 | .instance_size = sizeof(AspeedSoCState), |
482 | .class_size = sizeof(AspeedSoCClass), | |
54ecafb7 | 483 | .class_init = aspeed_soc_class_init, |
b033271f | 484 | .abstract = true, |
43e3346e AJ |
485 | }; |
486 | ||
54ecafb7 | 487 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) |
43e3346e | 488 | { |
54ecafb7 | 489 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
b033271f | 490 | |
54ecafb7 CLG |
491 | sc->name = "ast2400-a1"; |
492 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | |
493 | sc->silicon_rev = AST2400_A1_SILICON_REV; | |
494 | sc->sram_size = 0x8000; | |
495 | sc->spis_num = 1; | |
bfdd34f1 | 496 | sc->ehcis_num = 1; |
54ecafb7 | 497 | sc->wdts_num = 2; |
d300db02 | 498 | sc->macs_num = 2; |
c5e1bdb9 | 499 | sc->uarts_num = 5; |
54ecafb7 CLG |
500 | sc->irqmap = aspeed_soc_ast2400_irqmap; |
501 | sc->memmap = aspeed_soc_ast2400_memmap; | |
502 | sc->num_cpus = 1; | |
699db715 | 503 | sc->get_irq = aspeed_soc_ast2400_get_irq; |
54ecafb7 CLG |
504 | } |
505 | ||
506 | static const TypeInfo aspeed_soc_ast2400_type_info = { | |
507 | .name = "ast2400-a1", | |
508 | .parent = TYPE_ASPEED_SOC, | |
509 | .instance_init = aspeed_soc_init, | |
510 | .instance_size = sizeof(AspeedSoCState), | |
511 | .class_init = aspeed_soc_ast2400_class_init, | |
512 | }; | |
513 | ||
514 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | |
515 | { | |
516 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
517 | ||
518 | sc->name = "ast2500-a1"; | |
519 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
520 | sc->silicon_rev = AST2500_A1_SILICON_REV; | |
521 | sc->sram_size = 0x9000; | |
522 | sc->spis_num = 2; | |
bfdd34f1 | 523 | sc->ehcis_num = 2; |
54ecafb7 | 524 | sc->wdts_num = 3; |
d300db02 | 525 | sc->macs_num = 2; |
c5e1bdb9 | 526 | sc->uarts_num = 5; |
54ecafb7 CLG |
527 | sc->irqmap = aspeed_soc_ast2500_irqmap; |
528 | sc->memmap = aspeed_soc_ast2500_memmap; | |
529 | sc->num_cpus = 1; | |
699db715 | 530 | sc->get_irq = aspeed_soc_ast2400_get_irq; |
43e3346e AJ |
531 | } |
532 | ||
54ecafb7 CLG |
533 | static const TypeInfo aspeed_soc_ast2500_type_info = { |
534 | .name = "ast2500-a1", | |
535 | .parent = TYPE_ASPEED_SOC, | |
536 | .instance_init = aspeed_soc_init, | |
537 | .instance_size = sizeof(AspeedSoCState), | |
538 | .class_init = aspeed_soc_ast2500_class_init, | |
539 | }; | |
540 | static void aspeed_soc_register_types(void) | |
541 | { | |
542 | type_register_static(&aspeed_soc_type_info); | |
543 | type_register_static(&aspeed_soc_ast2400_type_info); | |
544 | type_register_static(&aspeed_soc_ast2500_type_info); | |
545 | }; | |
546 | ||
699db715 CLG |
547 | type_init(aspeed_soc_register_types); |
548 | ||
549 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | |
550 | { | |
551 | return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | |
552 | } | |
470253b6 PD |
553 | |
554 | void aspeed_soc_uart_init(AspeedSoCState *s) | |
555 | { | |
556 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
6827ff20 | 557 | int i, uart; |
470253b6 PD |
558 | |
559 | /* Attach an 8250 to the IO space as our UART */ | |
4dd9d554 | 560 | serial_mm_init(s->memory, sc->memmap[s->uart_default], 2, |
470253b6 PD |
561 | aspeed_soc_get_irq(s, s->uart_default), 38400, |
562 | serial_hd(0), DEVICE_LITTLE_ENDIAN); | |
6827ff20 PD |
563 | for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { |
564 | if (uart == s->uart_default) { | |
565 | uart++; | |
566 | } | |
4dd9d554 | 567 | serial_mm_init(s->memory, sc->memmap[uart], 2, |
6827ff20 PD |
568 | aspeed_soc_get_irq(s, uart), 38400, |
569 | serial_hd(i), DEVICE_LITTLE_ENDIAN); | |
570 | } | |
470253b6 | 571 | } |
346160cb CLG |
572 | |
573 | /* | |
574 | * SDMC should be realized first to get correct RAM size and max size | |
575 | * values | |
576 | */ | |
577 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) | |
578 | { | |
579 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
580 | ram_addr_t ram_size, max_ram_size; | |
581 | ||
582 | ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", | |
583 | &error_abort); | |
584 | max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", | |
585 | &error_abort); | |
586 | ||
587 | memory_region_init(&s->dram_container, OBJECT(s), "ram-container", | |
588 | max_ram_size); | |
589 | memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); | |
590 | ||
591 | /* | |
592 | * Add a memory region beyond the RAM region to let firmwares scan | |
593 | * the address space with load/store and guess how much RAM the | |
594 | * SoC has. | |
595 | */ | |
596 | if (ram_size < max_ram_size) { | |
597 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); | |
598 | ||
599 | qdev_prop_set_string(dev, "name", "ram-empty"); | |
600 | qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); | |
601 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { | |
602 | return false; | |
603 | } | |
604 | ||
605 | memory_region_add_subregion_overlap(&s->dram_container, ram_size, | |
606 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); | |
607 | } | |
608 | ||
4dd9d554 | 609 | memory_region_add_subregion(s->memory, |
346160cb CLG |
610 | sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); |
611 | return true; | |
612 | } |