[mirror_qemu.git] / hw / arm / aspeed_soc.c

/*
 * ASPEED SoC family
 *
 * Andrew Jeffery <andrew@aj.id.au>
 * Jeremy Kerr <jk@ozlabs.org>
 *
 * Copyright 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"

#define ASPEED_SOC_IOMEM_SIZE       0x00200000

static const hwaddr aspeed_soc_ast2400_memmap[] = {
    [ASPEED_IOMEM]  = 0x1E600000,
    [ASPEED_FMC]    = 0x1E620000,
    [ASPEED_SPI1]   = 0x1E630000,
    [ASPEED_EHCI1]  = 0x1E6A1000,
    [ASPEED_VIC]    = 0x1E6C0000,
    [ASPEED_SDMC]   = 0x1E6E0000,
    [ASPEED_SCU]    = 0x1E6E2000,
    [ASPEED_XDMA]   = 0x1E6E7000,
    [ASPEED_VIDEO]  = 0x1E700000,
    [ASPEED_ADC]    = 0x1E6E9000,
    [ASPEED_SRAM]   = 0x1E720000,
    [ASPEED_SDHCI]  = 0x1E740000,
    [ASPEED_GPIO]   = 0x1E780000,
    [ASPEED_RTC]    = 0x1E781000,
    [ASPEED_TIMER1] = 0x1E782000,
    [ASPEED_WDT]    = 0x1E785000,
    [ASPEED_PWM]    = 0x1E786000,
    [ASPEED_LPC]    = 0x1E789000,
    [ASPEED_IBT]    = 0x1E789140,
    [ASPEED_I2C]    = 0x1E78A000,
    [ASPEED_ETH1]   = 0x1E660000,
    [ASPEED_ETH2]   = 0x1E680000,
    [ASPEED_UART1]  = 0x1E783000,
    [ASPEED_UART5]  = 0x1E784000,
    [ASPEED_VUART]  = 0x1E787000,
    [ASPEED_SDRAM]  = 0x40000000,
};

static const hwaddr aspeed_soc_ast2500_memmap[] = {
    [ASPEED_IOMEM]  = 0x1E600000,
    [ASPEED_FMC]    = 0x1E620000,
    [ASPEED_SPI1]   = 0x1E630000,
    [ASPEED_SPI2]   = 0x1E631000,
    [ASPEED_EHCI1]  = 0x1E6A1000,
    [ASPEED_EHCI2]  = 0x1E6A3000,
    [ASPEED_VIC]    = 0x1E6C0000,
    [ASPEED_SDMC]   = 0x1E6E0000,
    [ASPEED_SCU]    = 0x1E6E2000,
    [ASPEED_XDMA]   = 0x1E6E7000,
    [ASPEED_ADC]    = 0x1E6E9000,
    [ASPEED_VIDEO]  = 0x1E700000,
    [ASPEED_SRAM]   = 0x1E720000,
    [ASPEED_SDHCI]  = 0x1E740000,
    [ASPEED_GPIO]   = 0x1E780000,
    [ASPEED_RTC]    = 0x1E781000,
    [ASPEED_TIMER1] = 0x1E782000,
    [ASPEED_WDT]    = 0x1E785000,
    [ASPEED_PWM]    = 0x1E786000,
    [ASPEED_LPC]    = 0x1E789000,
    [ASPEED_IBT]    = 0x1E789140,
    [ASPEED_I2C]    = 0x1E78A000,
    [ASPEED_ETH1]   = 0x1E660000,
    [ASPEED_ETH2]   = 0x1E680000,
    [ASPEED_UART1]  = 0x1E783000,
    [ASPEED_UART5]  = 0x1E784000,
    [ASPEED_VUART]  = 0x1E787000,
    [ASPEED_SDRAM]  = 0x80000000,
};

static const int aspeed_soc_ast2400_irqmap[] = {
    [ASPEED_UART1]  = 9,
    [ASPEED_UART2]  = 32,
    [ASPEED_UART3]  = 33,
    [ASPEED_UART4]  = 34,
    [ASPEED_UART5]  = 10,
    [ASPEED_VUART]  = 8,
    [ASPEED_FMC]    = 19,
    [ASPEED_EHCI1]  = 5,
    [ASPEED_EHCI2]  = 13,
    [ASPEED_SDMC]   = 0,
    [ASPEED_SCU]    = 21,
    [ASPEED_ADC]    = 31,
    [ASPEED_GPIO]   = 20,
    [ASPEED_RTC]    = 22,
    [ASPEED_TIMER1] = 16,
    [ASPEED_TIMER2] = 17,
    [ASPEED_TIMER3] = 18,
    [ASPEED_TIMER4] = 35,
    [ASPEED_TIMER5] = 36,
    [ASPEED_TIMER6] = 37,
    [ASPEED_TIMER7] = 38,
    [ASPEED_TIMER8] = 39,
    [ASPEED_WDT]    = 27,
    [ASPEED_PWM]    = 28,
    [ASPEED_LPC]    = 8,
    [ASPEED_IBT]    = 8, /* LPC */
    [ASPEED_I2C]    = 12,
    [ASPEED_ETH1]   = 2,
    [ASPEED_ETH2]   = 3,
    [ASPEED_XDMA]   = 6,
    [ASPEED_SDHCI]  = 26,
};

#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap

static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
{
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

    return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
}

static void aspeed_soc_init(Object *obj)
{
    AspeedSoCState *s = ASPEED_SOC(obj);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int i;
    char socname[8];
    char typename[64];

    if (sscanf(sc->name, "%7s", socname) != 1) {
        g_assert_not_reached();
    }

    for (i = 0; i < sc->num_cpus; i++) {
        object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
                                sizeof(s->cpu[i]), sc->cpu_type,
                                &error_abort, NULL);
    }

    snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
    sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
                          typename);
    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
                         sc->silicon_rev);
    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                              "hw-strap1");
    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
                              "hw-strap2");
    object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                              "hw-prot-key");

    sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
                          TYPE_ASPEED_VIC);

    sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
                          TYPE_ASPEED_RTC);

    snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
    sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
                          sizeof(s->timerctrl), typename);

    snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
    sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
                          typename);

    snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
    sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
                          typename);
    object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");

    for (i = 0; i < sc->spis_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
        sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
                              sizeof(s->spi[i]), typename);
    }

    for (i = 0; i < sc->ehcis_num; i++) {
        sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
                              sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
    }

    snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
    sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
                          typename);
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                              "ram-size");
    object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
                              "max-ram-size");

    for (i = 0; i < sc->wdts_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
        sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
                              sizeof(s->wdt[i]), typename);
    }

    for (i = 0; i < sc->macs_num; i++) {
        sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
                              sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
    }

    sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
                          TYPE_ASPEED_XDMA);

    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
    sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
                          typename);

    sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
                          TYPE_ASPEED_SDHCI);

    object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);

    /* Init sd card slot class here so that they're under the correct parent */
    for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
        sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
                              sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
    }
}

static void aspeed_soc_realize(DeviceState *dev, Error **errp)
{
    int i;
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    Error *err = NULL, *local_err = NULL;

    /* IO space */
    create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
                                ASPEED_SOC_IOMEM_SIZE);

    /* Video engine stub */
    create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
                                0x1000);

    if (s->num_cpus > sc->num_cpus) {
        warn_report("%s: invalid number of CPUs %d, using default %d",
                    sc->name, s->num_cpus, sc->num_cpus);
        s->num_cpus = sc->num_cpus;
    }

    /* CPU */
    for (i = 0; i < s->num_cpus; i++) {
        object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    /* SRAM */
    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
                           sc->sram_size, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(),
                                sc->memmap[ASPEED_SRAM], &s->sram);

    /* SCU */
    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);

    /* VIC */
    object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    /* RTC */
    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
                       aspeed_soc_get_irq(s, ASPEED_RTC));

    /* Timer */
    object_property_set_link(OBJECT(&s->timerctrl),
                             OBJECT(&s->scu), "scu", &error_abort);
    object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
                    sc->memmap[ASPEED_TIMER1]);
    for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
        qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
    }

    /* UART - attach an 8250 to the IO space as our UART5 */
    if (serial_hd(0)) {
        qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
        serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
                       uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
    }

    /* I2C */
    object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
                       aspeed_soc_get_irq(s, ASPEED_I2C));

    /* FMC, The number of CS is set at the board level */
    object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
                            "sdram-base", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
                    s->fmc.ctrl->flash_window_base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
                       aspeed_soc_get_irq(s, ASPEED_FMC));

    /* SPI */
    for (i = 0; i < sc->spis_num; i++) {
        object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
                        sc->memmap[ASPEED_SPI1 + i]);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
                        s->spi[i].ctrl->flash_window_base);
    }

    /* EHCI */
    for (i = 0; i < sc->ehcis_num; i++) {
        object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                        sc->memmap[ASPEED_EHCI1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
    }

    /* SDMC - SDRAM Memory Controller */
    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);

    /* Watch dog */
    for (i = 0; i < sc->wdts_num; i++) {
        AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);

        object_property_set_link(OBJECT(&s->wdt[i]),
                                 OBJECT(&s->scu), "scu", &error_abort);
        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
                        sc->memmap[ASPEED_WDT] + i * awc->offset);
    }

    /* Net */
    for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
        qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
                                 &err);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
           return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                        sc->memmap[ASPEED_ETH1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
    }

    /* XDMA */
    object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
                    sc->memmap[ASPEED_XDMA]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
                       aspeed_soc_get_irq(s, ASPEED_XDMA));

    /* GPIO */
    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                       aspeed_soc_get_irq(s, ASPEED_GPIO));

    /* SDHCI */
    object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
                    sc->memmap[ASPEED_SDHCI]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                       aspeed_soc_get_irq(s, ASPEED_SDHCI));
}
static Property aspeed_soc_properties[] = {
    DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_END_OF_LIST(),
};

static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = aspeed_soc_realize;
    /* Reason: Uses serial_hds and nd_table in realize() directly */
    dc->user_creatable = false;
    device_class_set_props(dc, aspeed_soc_properties);
}

static const TypeInfo aspeed_soc_type_info = {
    .name           = TYPE_ASPEED_SOC,
    .parent         = TYPE_DEVICE,
    .instance_size  = sizeof(AspeedSoCState),
    .class_size     = sizeof(AspeedSoCClass),
    .class_init     = aspeed_soc_class_init,
    .abstract       = true,
};

static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
{
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    sc->name         = "ast2400-a1";
    sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
    sc->silicon_rev  = AST2400_A1_SILICON_REV;
    sc->sram_size    = 0x8000;
    sc->spis_num     = 1;
    sc->ehcis_num    = 1;
    sc->wdts_num     = 2;
    sc->macs_num     = 2;
    sc->irqmap       = aspeed_soc_ast2400_irqmap;
    sc->memmap       = aspeed_soc_ast2400_memmap;
    sc->num_cpus     = 1;
}

static const TypeInfo aspeed_soc_ast2400_type_info = {
    .name           = "ast2400-a1",
    .parent         = TYPE_ASPEED_SOC,
    .instance_init  = aspeed_soc_init,
    .instance_size  = sizeof(AspeedSoCState),
    .class_init     = aspeed_soc_ast2400_class_init,
};

static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
{
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    sc->name         = "ast2500-a1";
    sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
    sc->silicon_rev  = AST2500_A1_SILICON_REV;
    sc->sram_size    = 0x9000;
    sc->spis_num     = 2;
    sc->ehcis_num    = 2;
    sc->wdts_num     = 3;
    sc->macs_num     = 2;
    sc->irqmap       = aspeed_soc_ast2500_irqmap;
    sc->memmap       = aspeed_soc_ast2500_memmap;
    sc->num_cpus     = 1;
}

static const TypeInfo aspeed_soc_ast2500_type_info = {
    .name           = "ast2500-a1",
    .parent         = TYPE_ASPEED_SOC,
    .instance_init  = aspeed_soc_init,
    .instance_size  = sizeof(AspeedSoCState),
    .class_init     = aspeed_soc_ast2500_class_init,
};
static void aspeed_soc_register_types(void)
{
    type_register_static(&aspeed_soc_type_info);
    type_register_static(&aspeed_soc_ast2400_type_info);
    type_register_static(&aspeed_soc_ast2500_type_info);
};

type_init(aspeed_soc_register_types)
Commit	Line	Data
43e3346e	1	/*
ff90606f	2	* ASPEED SoC family
43e3346e AJ	3	*
	4	* Andrew Jeffery <andrew@aj.id.au>
	5	* Jeremy Kerr <jk@ozlabs.org>
	6	*
	7	* Copyright 2016 IBM Corp.
	8	*
	9	* This code is licensed under the GPL version 2 or later. See
	10	* the COPYING file in the top-level directory.
	11	*/
	12
	13	#include "qemu/osdep.h"
da34e65c	14	#include "qapi/error.h"
4771d756	15	#include "cpu.h"
43e3346e	16	#include "exec/address-spaces.h"
c7c3c9f8	17	#include "hw/misc/unimp.h"
00442402	18	#include "hw/arm/aspeed_soc.h"
43e3346e	19	#include "hw/char/serial.h"
03dd024f	20	#include "qemu/log.h"
0b8fa32f	21	#include "qemu/module.h"
ece09bee	22	#include "qemu/error-report.h"
16020011	23	#include "hw/i2c/aspeed_i2c.h"
ea337c65	24	#include "net/net.h"
46517dd4	25	#include "sysemu/sysemu.h"
43e3346e	26
ff90606f	27	#define ASPEED_SOC_IOMEM_SIZE 0x00200000
d783d1fe CLG	28
	29	static const hwaddr aspeed_soc_ast2400_memmap[] = {
	30	[ASPEED_IOMEM] = 0x1E600000,
	31	[ASPEED_FMC] = 0x1E620000,
	32	[ASPEED_SPI1] = 0x1E630000,
bfdd34f1	33	[ASPEED_EHCI1] = 0x1E6A1000,
d783d1fe CLG	34	[ASPEED_VIC] = 0x1E6C0000,
	35	[ASPEED_SDMC] = 0x1E6E0000,
	36	[ASPEED_SCU] = 0x1E6E2000,
118c82e7	37	[ASPEED_XDMA] = 0x1E6E7000,
514bcf6f	38	[ASPEED_VIDEO] = 0x1E700000,
d783d1fe CLG	39	[ASPEED_ADC] = 0x1E6E9000,
d783d1fe CLG	40	[ASPEED_SRAM] = 0x1E720000,
2bea128c	41	[ASPEED_SDHCI] = 0x1E740000,
d783d1fe CLG	42	[ASPEED_GPIO] = 0x1E780000,
	43	[ASPEED_RTC] = 0x1E781000,
	44	[ASPEED_TIMER1] = 0x1E782000,
	45	[ASPEED_WDT] = 0x1E785000,
	46	[ASPEED_PWM] = 0x1E786000,
	47	[ASPEED_LPC] = 0x1E789000,
	48	[ASPEED_IBT] = 0x1E789140,
	49	[ASPEED_I2C] = 0x1E78A000,
	50	[ASPEED_ETH1] = 0x1E660000,
	51	[ASPEED_ETH2] = 0x1E680000,
	52	[ASPEED_UART1] = 0x1E783000,
	53	[ASPEED_UART5] = 0x1E784000,
	54	[ASPEED_VUART] = 0x1E787000,
	55	[ASPEED_SDRAM] = 0x40000000,
	56	};
	57
	58	static const hwaddr aspeed_soc_ast2500_memmap[] = {
	59	[ASPEED_IOMEM] = 0x1E600000,
	60	[ASPEED_FMC] = 0x1E620000,
	61	[ASPEED_SPI1] = 0x1E630000,
	62	[ASPEED_SPI2] = 0x1E631000,
bfdd34f1 GR	63	[ASPEED_EHCI1] = 0x1E6A1000,
bfdd34f1 GR	64	[ASPEED_EHCI2] = 0x1E6A3000,
d783d1fe CLG	65	[ASPEED_VIC] = 0x1E6C0000,
	66	[ASPEED_SDMC] = 0x1E6E0000,
	67	[ASPEED_SCU] = 0x1E6E2000,
118c82e7	68	[ASPEED_XDMA] = 0x1E6E7000,
d783d1fe	69	[ASPEED_ADC] = 0x1E6E9000,
514bcf6f	70	[ASPEED_VIDEO] = 0x1E700000,
d783d1fe	71	[ASPEED_SRAM] = 0x1E720000,
2bea128c	72	[ASPEED_SDHCI] = 0x1E740000,
d783d1fe CLG	73	[ASPEED_GPIO] = 0x1E780000,
	74	[ASPEED_RTC] = 0x1E781000,
	75	[ASPEED_TIMER1] = 0x1E782000,
	76	[ASPEED_WDT] = 0x1E785000,
	77	[ASPEED_PWM] = 0x1E786000,
	78	[ASPEED_LPC] = 0x1E789000,
	79	[ASPEED_IBT] = 0x1E789140,
	80	[ASPEED_I2C] = 0x1E78A000,
	81	[ASPEED_ETH1] = 0x1E660000,
	82	[ASPEED_ETH2] = 0x1E680000,
	83	[ASPEED_UART1] = 0x1E783000,
	84	[ASPEED_UART5] = 0x1E784000,
	85	[ASPEED_VUART] = 0x1E787000,
	86	[ASPEED_SDRAM] = 0x80000000,
	87	};
ff90606f	88
b456b113 CLG	89	static const int aspeed_soc_ast2400_irqmap[] = {
	90	[ASPEED_UART1] = 9,
	91	[ASPEED_UART2] = 32,
	92	[ASPEED_UART3] = 33,
	93	[ASPEED_UART4] = 34,
	94	[ASPEED_UART5] = 10,
	95	[ASPEED_VUART] = 8,
	96	[ASPEED_FMC] = 19,
bfdd34f1 GR	97	[ASPEED_EHCI1] = 5,
bfdd34f1 GR	98	[ASPEED_EHCI2] = 13,
b456b113 CLG	99	[ASPEED_SDMC] = 0,
	100	[ASPEED_SCU] = 21,
	101	[ASPEED_ADC] = 31,
	102	[ASPEED_GPIO] = 20,
	103	[ASPEED_RTC] = 22,
	104	[ASPEED_TIMER1] = 16,
	105	[ASPEED_TIMER2] = 17,
	106	[ASPEED_TIMER3] = 18,
	107	[ASPEED_TIMER4] = 35,
	108	[ASPEED_TIMER5] = 36,
	109	[ASPEED_TIMER6] = 37,
	110	[ASPEED_TIMER7] = 38,
	111	[ASPEED_TIMER8] = 39,
	112	[ASPEED_WDT] = 27,
	113	[ASPEED_PWM] = 28,
	114	[ASPEED_LPC] = 8,
	115	[ASPEED_IBT] = 8, /* LPC */
	116	[ASPEED_I2C] = 12,
	117	[ASPEED_ETH1] = 2,
	118	[ASPEED_ETH2] = 3,
118c82e7	119	[ASPEED_XDMA] = 6,
2bea128c	120	[ASPEED_SDHCI] = 26,
b456b113	121	};
43e3346e	122
b456b113 CLG	123	#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
b456b113 CLG	124
b456b113 CLG	125	static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
	126	{
	127	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	128
54ecafb7	129	return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
b456b113 CLG	130	}
b456b113 CLG	131
ff90606f	132	static void aspeed_soc_init(Object *obj)
43e3346e	133	{
ff90606f	134	AspeedSoCState *s = ASPEED_SOC(obj);
b033271f	135	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
dbcabeeb	136	int i;
811a5b1d CLG	137	char socname[8];
	138	char typename[64];
	139
54ecafb7	140	if (sscanf(sc->name, "%7s", socname) != 1) {
811a5b1d CLG	141	g_assert_not_reached();
811a5b1d CLG	142	}
43e3346e	143
54ecafb7	144	for (i = 0; i < sc->num_cpus; i++) {
ece09bee	145	object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
54ecafb7	146	sizeof(s->cpu[i]), sc->cpu_type,
ece09bee CLG	147	&error_abort, NULL);
ece09bee CLG	148	}
43e3346e	149
9a937f6c	150	snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
1b0ad567	151	sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
9a937f6c	152	typename);
334973bb	153	qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
54ecafb7	154	sc->silicon_rev);
334973bb	155	object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
d2623129	156	"hw-strap1");
334973bb	157	object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
d2623129	158	"hw-strap2");
b6e70d1d	159	object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
d2623129	160	"hw-prot-key");
7c1c69bc	161
1b0ad567 PMD	162	sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
1b0ad567 PMD	163	TYPE_ASPEED_VIC);
e2a11ca8	164
75fb4577 JS	165	sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
	166	TYPE_ASPEED_RTC);
	167
72d96f8e	168	snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
1b0ad567	169	sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
72d96f8e	170	sizeof(s->timerctrl), typename);
e2a11ca8	171
f7da1aa8	172	snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
1b0ad567	173	sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
f7da1aa8	174	typename);
e2a11ca8	175
811a5b1d	176	snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
1b0ad567	177	sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
811a5b1d	178	typename);
d2623129	179	object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
7c1c69bc	180
54ecafb7	181	for (i = 0; i < sc->spis_num; i++) {
811a5b1d	182	snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
1b0ad567	183	sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
811a5b1d	184	sizeof(s->spi[i]), typename);
dbcabeeb	185	}
c2da8a8b	186
bfdd34f1 GR	187	for (i = 0; i < sc->ehcis_num; i++) {
	188	sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
	189	sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
	190	}
	191
8e00d1a9	192	snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
1b0ad567	193	sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
8e00d1a9	194	typename);
c6c7cfb0	195	object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
d2623129	196	"ram-size");
ebe31c0a	197	object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
d2623129	198	"max-ram-size");
013befe1	199
54ecafb7	200	for (i = 0; i < sc->wdts_num; i++) {
6112bd6d	201	snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
1b0ad567	202	sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
6112bd6d	203	sizeof(s->wdt[i]), typename);
f986ee1d	204	}
ea337c65	205
d300db02	206	for (i = 0; i < sc->macs_num; i++) {
67340990 CLG	207	sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
	208	sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
	209	}
118c82e7 EJ	210
	211	sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
	212	TYPE_ASPEED_XDMA);
fdcc7c06	213
811a5b1d	214	snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
fdcc7c06	215	sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
811a5b1d	216	typename);
2bea128c EJ	217
	218	sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
	219	TYPE_ASPEED_SDHCI);
	220
0e2c24c6 AJ	221	object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
0e2c24c6 AJ	222
2bea128c EJ	223	/* Init sd card slot class here so that they're under the correct parent */
	224	for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
	225	sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
	226	sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
	227	}
43e3346e AJ	228	}
43e3346e AJ	229
ff90606f	230	static void aspeed_soc_realize(DeviceState dev, Error *errp)
43e3346e AJ	231	{
43e3346e AJ	232	int i;
ff90606f	233	AspeedSoCState *s = ASPEED_SOC(dev);
dbcabeeb	234	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
7c1c69bc	235	Error err = NULL, local_err = NULL;
43e3346e AJ	236
43e3346e AJ	237	/* IO space */
54ecafb7	238	create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
d783d1fe	239	ASPEED_SOC_IOMEM_SIZE);
43e3346e	240
514bcf6f JS	241	/* Video engine stub */
	242	create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
	243	0x1000);
	244
54ecafb7	245	if (s->num_cpus > sc->num_cpus) {
ece09bee	246	warn_report("%s: invalid number of CPUs %d, using default %d",
54ecafb7 CLG	247	sc->name, s->num_cpus, sc->num_cpus);
54ecafb7 CLG	248	s->num_cpus = sc->num_cpus;
ece09bee CLG	249	}
ece09bee CLG	250
2d105bd6	251	/* CPU */
ece09bee CLG	252	for (i = 0; i < s->num_cpus; i++) {
	253	object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
	254	if (err) {
	255	error_propagate(errp, err);
	256	return;
	257	}
2d105bd6 CLG	258	}
2d105bd6 CLG	259
74af4eec	260	/* SRAM */
a2e9989c	261	memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
54ecafb7	262	sc->sram_size, &err);
74af4eec CLG	263	if (err) {
	264	error_propagate(errp, err);
	265	return;
	266	}
d783d1fe	267	memory_region_add_subregion(get_system_memory(),
54ecafb7	268	sc->memmap[ASPEED_SRAM], &s->sram);
74af4eec	269
e2a11ca8 CLG	270	/* SCU */
	271	object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
	272	if (err) {
	273	error_propagate(errp, err);
	274	return;
	275	}
54ecafb7	276	sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
e2a11ca8	277
43e3346e AJ	278	/* VIC */
	279	object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
	280	if (err) {
	281	error_propagate(errp, err);
	282	return;
	283	}
54ecafb7	284	sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
43e3346e	285	sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
2d105bd6	286	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
43e3346e	287	sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
2d105bd6	288	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
43e3346e	289
75fb4577 JS	290	/* RTC */
	291	object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
	292	if (err) {
	293	error_propagate(errp, err);
	294	return;
	295	}
54ecafb7	296	sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
75fb4577 JS	297	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
	298	aspeed_soc_get_irq(s, ASPEED_RTC));
	299
43e3346e	300	/* Timer */
2ec11f23 CLG	301	object_property_set_link(OBJECT(&s->timerctrl),
2ec11f23 CLG	302	OBJECT(&s->scu), "scu", &error_abort);
43e3346e AJ	303	object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
	304	if (err) {
	305	error_propagate(errp, err);
	306	return;
	307	}
d783d1fe	308	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
54ecafb7	309	sc->memmap[ASPEED_TIMER1]);
b456b113 CLG	310	for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
b456b113 CLG	311	qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
43e3346e AJ	312	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
	313	}
	314
	315	/* UART - attach an 8250 to the IO space as our UART5 */
9bca0edb	316	if (serial_hd(0)) {
b456b113	317	qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
54ecafb7	318	serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
9bca0edb	319	uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
43e3346e	320	}
16020011 CLG	321
16020011 CLG	322	/* I2C */
545d6bef CLG	323	object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
	324	if (err) {
	325	error_propagate(errp, err);
	326	return;
	327	}
16020011 CLG	328	object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
	329	if (err) {
	330	error_propagate(errp, err);
	331	return;
	332	}
54ecafb7	333	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
16020011	334	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
b456b113	335	aspeed_soc_get_irq(s, ASPEED_I2C));
7c1c69bc	336
26d5df95	337	/* FMC, The number of CS is set at the board level */
95b56e17 CLG	338	object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
	339	if (err) {
	340	error_propagate(errp, err);
	341	return;
	342	}
54ecafb7	343	object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
6da4433f CLG	344	"sdram-base", &err);
	345	if (err) {
	346	error_propagate(errp, err);
	347	return;
	348	}
26d5df95	349	object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
7c1c69bc CLG	350	if (err) {
	351	error_propagate(errp, err);
	352	return;
	353	}
54ecafb7	354	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
dcb83444 CLG	355	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
dcb83444 CLG	356	s->fmc.ctrl->flash_window_base);
0e5803df	357	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
b456b113	358	aspeed_soc_get_irq(s, ASPEED_FMC));
7c1c69bc CLG	359
7c1c69bc CLG	360	/* SPI */
54ecafb7	361	for (i = 0; i < sc->spis_num; i++) {
dbcabeeb CLG	362	object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
	363	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
	364	&local_err);
	365	error_propagate(&err, local_err);
	366	if (err) {
	367	error_propagate(errp, err);
	368	return;
	369	}
d783d1fe	370	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
54ecafb7	371	sc->memmap[ASPEED_SPI1 + i]);
dbcabeeb CLG	372	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
dbcabeeb CLG	373	s->spi[i].ctrl->flash_window_base);
7c1c69bc	374	}
c2da8a8b	375
bfdd34f1 GR	376	/* EHCI */
	377	for (i = 0; i < sc->ehcis_num; i++) {
	378	object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
	379	if (err) {
	380	error_propagate(errp, err);
	381	return;
	382	}
	383	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	384	sc->memmap[ASPEED_EHCI1 + i]);
	385	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
	386	aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
	387	}
	388
c2da8a8b CLG	389	/* SDMC - SDRAM Memory Controller */
	390	object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
	391	if (err) {
	392	error_propagate(errp, err);
	393	return;
	394	}
54ecafb7	395	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
013befe1 CLG	396
013befe1 CLG	397	/* Watch dog */
54ecafb7	398	for (i = 0; i < sc->wdts_num; i++) {
6112bd6d CLG	399	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
6112bd6d CLG	400
2ec11f23 CLG	401	object_property_set_link(OBJECT(&s->wdt[i]),
2ec11f23 CLG	402	OBJECT(&s->scu), "scu", &error_abort);
f986ee1d JS	403	object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
	404	if (err) {
	405	error_propagate(errp, err);
	406	return;
	407	}
	408	sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
54ecafb7	409	sc->memmap[ASPEED_WDT] + i * awc->offset);
013befe1	410	}
ea337c65 CLG	411
ea337c65 CLG	412	/* Net */
d300db02	413	for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
67340990 CLG	414	qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
	415	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
	416	&err);
	417	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
	418	&local_err);
	419	error_propagate(&err, local_err);
	420	if (err) {
	421	error_propagate(errp, err);
	422	return;
	423	}
	424	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
54ecafb7	425	sc->memmap[ASPEED_ETH1 + i]);
67340990 CLG	426	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
67340990 CLG	427	aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
ea337c65	428	}
118c82e7 EJ	429
	430	/* XDMA */
	431	object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
	432	if (err) {
	433	error_propagate(errp, err);
	434	return;
	435	}
	436	sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
54ecafb7	437	sc->memmap[ASPEED_XDMA]);
118c82e7 EJ	438	sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
118c82e7 EJ	439	aspeed_soc_get_irq(s, ASPEED_XDMA));
fdcc7c06 RG	440
	441	/* GPIO */
	442	object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
	443	if (err) {
	444	error_propagate(errp, err);
	445	return;
	446	}
54ecafb7	447	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
fdcc7c06 RG	448	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
fdcc7c06 RG	449	aspeed_soc_get_irq(s, ASPEED_GPIO));
2bea128c EJ	450
	451	/* SDHCI */
	452	object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
	453	if (err) {
	454	error_propagate(errp, err);
	455	return;
	456	}
	457	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
54ecafb7	458	sc->memmap[ASPEED_SDHCI]);
2bea128c EJ	459	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
2bea128c EJ	460	aspeed_soc_get_irq(s, ASPEED_SDHCI));
43e3346e	461	}
ece09bee CLG	462	static Property aspeed_soc_properties[] = {
ece09bee CLG	463	DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
95b56e17 CLG	464	DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
95b56e17 CLG	465	MemoryRegion *),
ece09bee CLG	466	DEFINE_PROP_END_OF_LIST(),
ece09bee CLG	467	};
43e3346e	468
ff90606f	469	static void aspeed_soc_class_init(ObjectClass oc, void data)
43e3346e AJ	470	{
	471	DeviceClass *dc = DEVICE_CLASS(oc);
	472
ff90606f	473	dc->realize = aspeed_soc_realize;
469f3da4 TH	474	/* Reason: Uses serial_hds and nd_table in realize() directly */
469f3da4 TH	475	dc->user_creatable = false;
4f67d30b	476	device_class_set_props(dc, aspeed_soc_properties);
43e3346e AJ	477	}
43e3346e AJ	478
ff90606f	479	static const TypeInfo aspeed_soc_type_info = {
b033271f CLG	480	.name = TYPE_ASPEED_SOC,
b033271f CLG	481	.parent = TYPE_DEVICE,
b033271f CLG	482	.instance_size = sizeof(AspeedSoCState),
b033271f CLG	483	.class_size = sizeof(AspeedSoCClass),
54ecafb7	484	.class_init = aspeed_soc_class_init,
b033271f	485	.abstract = true,
43e3346e AJ	486	};
43e3346e AJ	487
54ecafb7	488	static void aspeed_soc_ast2400_class_init(ObjectClass oc, void data)
43e3346e	489	{
54ecafb7	490	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
b033271f	491
54ecafb7 CLG	492	sc->name = "ast2400-a1";
	493	sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
	494	sc->silicon_rev = AST2400_A1_SILICON_REV;
	495	sc->sram_size = 0x8000;
	496	sc->spis_num = 1;
bfdd34f1	497	sc->ehcis_num = 1;
54ecafb7	498	sc->wdts_num = 2;
d300db02	499	sc->macs_num = 2;
54ecafb7 CLG	500	sc->irqmap = aspeed_soc_ast2400_irqmap;
	501	sc->memmap = aspeed_soc_ast2400_memmap;
	502	sc->num_cpus = 1;
	503	}
	504
	505	static const TypeInfo aspeed_soc_ast2400_type_info = {
	506	.name = "ast2400-a1",
	507	.parent = TYPE_ASPEED_SOC,
	508	.instance_init = aspeed_soc_init,
	509	.instance_size = sizeof(AspeedSoCState),
	510	.class_init = aspeed_soc_ast2400_class_init,
	511	};
	512
	513	static void aspeed_soc_ast2500_class_init(ObjectClass oc, void data)
	514	{
	515	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
	516
	517	sc->name = "ast2500-a1";
	518	sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
	519	sc->silicon_rev = AST2500_A1_SILICON_REV;
	520	sc->sram_size = 0x9000;
	521	sc->spis_num = 2;
bfdd34f1	522	sc->ehcis_num = 2;
54ecafb7	523	sc->wdts_num = 3;
d300db02	524	sc->macs_num = 2;
54ecafb7 CLG	525	sc->irqmap = aspeed_soc_ast2500_irqmap;
	526	sc->memmap = aspeed_soc_ast2500_memmap;
	527	sc->num_cpus = 1;
43e3346e AJ	528	}
43e3346e AJ	529
54ecafb7 CLG	530	static const TypeInfo aspeed_soc_ast2500_type_info = {
	531	.name = "ast2500-a1",
	532	.parent = TYPE_ASPEED_SOC,
	533	.instance_init = aspeed_soc_init,
	534	.instance_size = sizeof(AspeedSoCState),
	535	.class_init = aspeed_soc_ast2500_class_init,
	536	};
	537	static void aspeed_soc_register_types(void)
	538	{
	539	type_register_static(&aspeed_soc_type_info);
	540	type_register_static(&aspeed_soc_ast2400_type_info);
	541	type_register_static(&aspeed_soc_ast2500_type_info);
	542	};
	543
ff90606f	544	type_init(aspeed_soc_register_types)