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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
346160cb | 14 | #include "qemu/units.h" |
da34e65c | 15 | #include "qapi/error.h" |
c7c3c9f8 | 16 | #include "hw/misc/unimp.h" |
00442402 | 17 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 18 | #include "hw/char/serial.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
ece09bee | 20 | #include "qemu/error-report.h" |
16020011 | 21 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 22 | #include "net/net.h" |
46517dd4 | 23 | #include "sysemu/sysemu.h" |
43e3346e | 24 | |
ff90606f | 25 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
26 | |
27 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
5aa281d7 | 28 | [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, |
347df6f8 EH |
29 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
30 | [ASPEED_DEV_FMC] = 0x1E620000, | |
31 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
32 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
33 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
34 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
35 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 36 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
37 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
38 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
39 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
40 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
41 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
42 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
43 | [ASPEED_DEV_RTC] = 0x1E781000, | |
44 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
45 | [ASPEED_DEV_WDT] = 0x1E785000, | |
46 | [ASPEED_DEV_PWM] = 0x1E786000, | |
47 | [ASPEED_DEV_LPC] = 0x1E789000, | |
48 | [ASPEED_DEV_IBT] = 0x1E789140, | |
49 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
55c57023 | 50 | [ASPEED_DEV_PECI] = 0x1E78B000, |
347df6f8 EH |
51 | [ASPEED_DEV_ETH1] = 0x1E660000, |
52 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
53 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
54 | [ASPEED_DEV_UART2] = 0x1E78D000, |
55 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
56 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 EH |
57 | [ASPEED_DEV_UART5] = 0x1E784000, |
58 | [ASPEED_DEV_VUART] = 0x1E787000, | |
59 | [ASPEED_DEV_SDRAM] = 0x40000000, | |
d783d1fe CLG |
60 | }; |
61 | ||
62 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
5aa281d7 | 63 | [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, |
347df6f8 EH |
64 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
65 | [ASPEED_DEV_FMC] = 0x1E620000, | |
66 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
67 | [ASPEED_DEV_SPI2] = 0x1E631000, | |
68 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
69 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
70 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
71 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
72 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 73 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
74 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
75 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
76 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
77 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
78 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
79 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
80 | [ASPEED_DEV_RTC] = 0x1E781000, | |
81 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
82 | [ASPEED_DEV_WDT] = 0x1E785000, | |
83 | [ASPEED_DEV_PWM] = 0x1E786000, | |
84 | [ASPEED_DEV_LPC] = 0x1E789000, | |
85 | [ASPEED_DEV_IBT] = 0x1E789140, | |
86 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
55c57023 | 87 | [ASPEED_DEV_PECI] = 0x1E78B000, |
347df6f8 EH |
88 | [ASPEED_DEV_ETH1] = 0x1E660000, |
89 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
90 | [ASPEED_DEV_UART1] = 0x1E783000, | |
ab5e8605 PD |
91 | [ASPEED_DEV_UART2] = 0x1E78D000, |
92 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
93 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 EH |
94 | [ASPEED_DEV_UART5] = 0x1E784000, |
95 | [ASPEED_DEV_VUART] = 0x1E787000, | |
96 | [ASPEED_DEV_SDRAM] = 0x80000000, | |
d783d1fe | 97 | }; |
ff90606f | 98 | |
b456b113 | 99 | static const int aspeed_soc_ast2400_irqmap[] = { |
347df6f8 EH |
100 | [ASPEED_DEV_UART1] = 9, |
101 | [ASPEED_DEV_UART2] = 32, | |
102 | [ASPEED_DEV_UART3] = 33, | |
103 | [ASPEED_DEV_UART4] = 34, | |
104 | [ASPEED_DEV_UART5] = 10, | |
105 | [ASPEED_DEV_VUART] = 8, | |
106 | [ASPEED_DEV_FMC] = 19, | |
107 | [ASPEED_DEV_EHCI1] = 5, | |
108 | [ASPEED_DEV_EHCI2] = 13, | |
109 | [ASPEED_DEV_SDMC] = 0, | |
110 | [ASPEED_DEV_SCU] = 21, | |
111 | [ASPEED_DEV_ADC] = 31, | |
112 | [ASPEED_DEV_GPIO] = 20, | |
113 | [ASPEED_DEV_RTC] = 22, | |
114 | [ASPEED_DEV_TIMER1] = 16, | |
115 | [ASPEED_DEV_TIMER2] = 17, | |
116 | [ASPEED_DEV_TIMER3] = 18, | |
117 | [ASPEED_DEV_TIMER4] = 35, | |
118 | [ASPEED_DEV_TIMER5] = 36, | |
119 | [ASPEED_DEV_TIMER6] = 37, | |
120 | [ASPEED_DEV_TIMER7] = 38, | |
121 | [ASPEED_DEV_TIMER8] = 39, | |
122 | [ASPEED_DEV_WDT] = 27, | |
123 | [ASPEED_DEV_PWM] = 28, | |
124 | [ASPEED_DEV_LPC] = 8, | |
347df6f8 | 125 | [ASPEED_DEV_I2C] = 12, |
55c57023 | 126 | [ASPEED_DEV_PECI] = 15, |
347df6f8 EH |
127 | [ASPEED_DEV_ETH1] = 2, |
128 | [ASPEED_DEV_ETH2] = 3, | |
129 | [ASPEED_DEV_XDMA] = 6, | |
130 | [ASPEED_DEV_SDHCI] = 26, | |
a3888d75 | 131 | [ASPEED_DEV_HACE] = 4, |
b456b113 | 132 | }; |
43e3346e | 133 | |
b456b113 CLG |
134 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
135 | ||
699db715 | 136 | static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) |
b456b113 CLG |
137 | { |
138 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
139 | ||
699db715 | 140 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]); |
b456b113 CLG |
141 | } |
142 | ||
ff90606f | 143 | static void aspeed_soc_init(Object *obj) |
43e3346e | 144 | { |
ff90606f | 145 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 146 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 147 | int i; |
811a5b1d CLG |
148 | char socname[8]; |
149 | char typename[64]; | |
150 | ||
54ecafb7 | 151 | if (sscanf(sc->name, "%7s", socname) != 1) { |
811a5b1d CLG |
152 | g_assert_not_reached(); |
153 | } | |
43e3346e | 154 | |
54ecafb7 | 155 | for (i = 0; i < sc->num_cpus; i++) { |
9fc7fc4d | 156 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
ece09bee | 157 | } |
43e3346e | 158 | |
9a937f6c | 159 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
db873cc5 | 160 | object_initialize_child(obj, "scu", &s->scu, typename); |
334973bb | 161 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
54ecafb7 | 162 | sc->silicon_rev); |
334973bb | 163 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
d2623129 | 164 | "hw-strap1"); |
334973bb | 165 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 166 | "hw-strap2"); |
b6e70d1d | 167 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 168 | "hw-prot-key"); |
7c1c69bc | 169 | |
db873cc5 | 170 | object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC); |
e2a11ca8 | 171 | |
db873cc5 | 172 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
75fb4577 | 173 | |
72d96f8e | 174 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
db873cc5 | 175 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
e2a11ca8 | 176 | |
199fd623 AJ |
177 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
178 | object_initialize_child(obj, "adc", &s->adc, typename); | |
179 | ||
f7da1aa8 | 180 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 181 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
e2a11ca8 | 182 | |
55c57023 PD |
183 | object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); |
184 | ||
811a5b1d | 185 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 186 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
7c1c69bc | 187 | |
54ecafb7 | 188 | for (i = 0; i < sc->spis_num; i++) { |
811a5b1d | 189 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
db873cc5 | 190 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
dbcabeeb | 191 | } |
c2da8a8b | 192 | |
bfdd34f1 | 193 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
194 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
195 | TYPE_PLATFORM_EHCI); | |
bfdd34f1 GR |
196 | } |
197 | ||
8e00d1a9 | 198 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 199 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
c6c7cfb0 | 200 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 201 | "ram-size"); |
013befe1 | 202 | |
54ecafb7 | 203 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 204 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
db873cc5 | 205 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f986ee1d | 206 | } |
ea337c65 | 207 | |
d300db02 | 208 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
209 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
210 | TYPE_FTGMAC100); | |
67340990 | 211 | } |
118c82e7 | 212 | |
d2b3eaef PD |
213 | for (i = 0; i < sc->uarts_num; i++) { |
214 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); | |
215 | } | |
216 | ||
8efbee28 CLG |
217 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
218 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
fdcc7c06 | 219 | |
811a5b1d | 220 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
db873cc5 | 221 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
2bea128c | 222 | |
db873cc5 | 223 | object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); |
2bea128c | 224 | |
5325cc34 | 225 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 226 | |
2bea128c EJ |
227 | /* Init sd card slot class here so that they're under the correct parent */ |
228 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
229 | object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], |
230 | TYPE_SYSBUS_SDHCI); | |
2bea128c | 231 | } |
2ecf1726 CLG |
232 | |
233 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
234 | |
235 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
236 | object_initialize_child(obj, "hace", &s->hace, typename); | |
80beb085 PD |
237 | |
238 | object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); | |
239 | object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); | |
43e3346e AJ |
240 | } |
241 | ||
ff90606f | 242 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
243 | { |
244 | int i; | |
ff90606f | 245 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 246 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
123327d1 | 247 | Error *err = NULL; |
72a7c473 | 248 | g_autofree char *sram_name = NULL; |
43e3346e | 249 | |
5aa281d7 CLG |
250 | /* Default boot region (SPI memory or ROMs) */ |
251 | memory_region_init(&s->spi_boot_container, OBJECT(s), | |
252 | "aspeed.spi_boot_container", 0x10000000); | |
253 | memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], | |
254 | &s->spi_boot_container); | |
255 | ||
43e3346e | 256 | /* IO space */ |
80beb085 PD |
257 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", |
258 | sc->memmap[ASPEED_DEV_IOMEM], | |
259 | ASPEED_SOC_IOMEM_SIZE); | |
43e3346e | 260 | |
514bcf6f | 261 | /* Video engine stub */ |
80beb085 PD |
262 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", |
263 | sc->memmap[ASPEED_DEV_VIDEO], 0x1000); | |
514bcf6f | 264 | |
2d105bd6 | 265 | /* CPU */ |
b7f1a0cb | 266 | for (i = 0; i < sc->num_cpus; i++) { |
e37976d7 | 267 | object_property_set_link(OBJECT(&s->cpu[i]), "memory", |
4dd9d554 | 268 | OBJECT(s->memory), &error_abort); |
668f62ec | 269 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
ece09bee CLG |
270 | return; |
271 | } | |
2d105bd6 CLG |
272 | } |
273 | ||
74af4eec | 274 | /* SRAM */ |
72a7c473 PD |
275 | sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index); |
276 | memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); | |
74af4eec CLG |
277 | if (err) { |
278 | error_propagate(errp, err); | |
279 | return; | |
280 | } | |
4dd9d554 | 281 | memory_region_add_subregion(s->memory, |
347df6f8 | 282 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
74af4eec | 283 | |
e2a11ca8 | 284 | /* SCU */ |
668f62ec | 285 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
e2a11ca8 CLG |
286 | return; |
287 | } | |
5bfcbda7 | 288 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
e2a11ca8 | 289 | |
43e3346e | 290 | /* VIC */ |
668f62ec | 291 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) { |
43e3346e AJ |
292 | return; |
293 | } | |
5bfcbda7 | 294 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]); |
43e3346e | 295 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 296 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 297 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 298 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e | 299 | |
75fb4577 | 300 | /* RTC */ |
668f62ec | 301 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
75fb4577 JS |
302 | return; |
303 | } | |
5bfcbda7 | 304 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
75fb4577 | 305 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 306 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
75fb4577 | 307 | |
43e3346e | 308 | /* Timer */ |
5325cc34 MA |
309 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
310 | &error_abort); | |
668f62ec | 311 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
43e3346e AJ |
312 | return; |
313 | } | |
5bfcbda7 | 314 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, |
347df6f8 | 315 | sc->memmap[ASPEED_DEV_TIMER1]); |
b456b113 | 316 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 317 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
43e3346e AJ |
318 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
319 | } | |
320 | ||
199fd623 AJ |
321 | /* ADC */ |
322 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
323 | return; | |
324 | } | |
5bfcbda7 | 325 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); |
199fd623 AJ |
326 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
327 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
328 | ||
470253b6 | 329 | /* UART */ |
d2b3eaef PD |
330 | if (!aspeed_soc_uart_realize(s, errp)) { |
331 | return; | |
332 | } | |
16020011 CLG |
333 | |
334 | /* I2C */ | |
5325cc34 | 335 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 336 | &error_abort); |
668f62ec | 337 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
16020011 CLG |
338 | return; |
339 | } | |
5bfcbda7 | 340 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
16020011 | 341 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
347df6f8 | 342 | aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); |
7c1c69bc | 343 | |
55c57023 PD |
344 | /* PECI */ |
345 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { | |
346 | return; | |
347 | } | |
348 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, | |
349 | sc->memmap[ASPEED_DEV_PECI]); | |
350 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, | |
351 | aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); | |
352 | ||
26d5df95 | 353 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 354 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 355 | &error_abort); |
668f62ec | 356 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
7c1c69bc CLG |
357 | return; |
358 | } | |
5bfcbda7 PD |
359 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
360 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, | |
30b6852c | 361 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
0e5803df | 362 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 363 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
7c1c69bc | 364 | |
5aa281d7 CLG |
365 | /* Set up an alias on the FMC CE0 region (boot default) */ |
366 | MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; | |
367 | memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", | |
368 | fmc0_mmio, 0, memory_region_size(fmc0_mmio)); | |
369 | memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); | |
370 | ||
7c1c69bc | 371 | /* SPI */ |
54ecafb7 | 372 | for (i = 0; i < sc->spis_num; i++) { |
668f62ec | 373 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
dbcabeeb CLG |
374 | return; |
375 | } | |
5bfcbda7 | 376 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, |
347df6f8 | 377 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
5bfcbda7 | 378 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 379 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
7c1c69bc | 380 | } |
c2da8a8b | 381 | |
bfdd34f1 GR |
382 | /* EHCI */ |
383 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 384 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
bfdd34f1 GR |
385 | return; |
386 | } | |
5bfcbda7 | 387 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 388 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
bfdd34f1 | 389 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 390 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
bfdd34f1 GR |
391 | } |
392 | ||
c2da8a8b | 393 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 394 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
c2da8a8b CLG |
395 | return; |
396 | } | |
5bfcbda7 PD |
397 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, |
398 | sc->memmap[ASPEED_DEV_SDMC]); | |
013befe1 CLG |
399 | |
400 | /* Watch dog */ | |
54ecafb7 | 401 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 402 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
6fdb4381 | 403 | hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; |
6112bd6d | 404 | |
5325cc34 MA |
405 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
406 | &error_abort); | |
668f62ec | 407 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f986ee1d JS |
408 | return; |
409 | } | |
6fdb4381 | 410 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); |
013befe1 | 411 | } |
ea337c65 | 412 | |
346160cb CLG |
413 | /* RAM */ |
414 | if (!aspeed_soc_dram_init(s, errp)) { | |
415 | return; | |
416 | } | |
417 | ||
ea337c65 | 418 | /* Net */ |
d3bad7e7 | 419 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 420 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 421 | &error_abort); |
668f62ec | 422 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 423 | return; |
67340990 | 424 | } |
5bfcbda7 | 425 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 426 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
67340990 | 427 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 428 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
ea337c65 | 429 | } |
118c82e7 EJ |
430 | |
431 | /* XDMA */ | |
668f62ec | 432 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
118c82e7 EJ |
433 | return; |
434 | } | |
5bfcbda7 | 435 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 436 | sc->memmap[ASPEED_DEV_XDMA]); |
118c82e7 | 437 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 438 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
fdcc7c06 RG |
439 | |
440 | /* GPIO */ | |
668f62ec | 441 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
fdcc7c06 RG |
442 | return; |
443 | } | |
5bfcbda7 PD |
444 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, |
445 | sc->memmap[ASPEED_DEV_GPIO]); | |
fdcc7c06 | 446 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 447 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
2bea128c EJ |
448 | |
449 | /* SDHCI */ | |
668f62ec | 450 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
2bea128c EJ |
451 | return; |
452 | } | |
5bfcbda7 | 453 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 454 | sc->memmap[ASPEED_DEV_SDHCI]); |
2bea128c | 455 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 456 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
2ecf1726 CLG |
457 | |
458 | /* LPC */ | |
459 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
460 | return; | |
461 | } | |
5bfcbda7 | 462 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); |
c59f781e AJ |
463 | |
464 | /* Connect the LPC IRQ to the VIC */ | |
2ecf1726 CLG |
465 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
466 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
467 | |
468 | /* | |
469 | * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the | |
470 | * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by | |
471 | * contrast, on the AST2600, the subdevice IRQs are connected straight to | |
472 | * the GIC). | |
473 | * | |
474 | * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output | |
475 | * to the VIC is at offset 0. | |
476 | */ | |
477 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
478 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); | |
479 | ||
480 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
481 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); | |
482 | ||
483 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
484 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); | |
485 | ||
486 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
487 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); | |
a3888d75 JS |
488 | |
489 | /* HACE */ | |
490 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
491 | &error_abort); | |
492 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
493 | return; | |
494 | } | |
5bfcbda7 PD |
495 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, |
496 | sc->memmap[ASPEED_DEV_HACE]); | |
a3888d75 JS |
497 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, |
498 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
43e3346e | 499 | } |
ece09bee | 500 | static Property aspeed_soc_properties[] = { |
4dd9d554 PD |
501 | DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, |
502 | MemoryRegion *), | |
95b56e17 CLG |
503 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |
504 | MemoryRegion *), | |
ece09bee CLG |
505 | DEFINE_PROP_END_OF_LIST(), |
506 | }; | |
43e3346e | 507 | |
ff90606f | 508 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
509 | { |
510 | DeviceClass *dc = DEVICE_CLASS(oc); | |
511 | ||
ff90606f | 512 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
513 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
514 | dc->user_creatable = false; | |
4f67d30b | 515 | device_class_set_props(dc, aspeed_soc_properties); |
43e3346e AJ |
516 | } |
517 | ||
ff90606f | 518 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
519 | .name = TYPE_ASPEED_SOC, |
520 | .parent = TYPE_DEVICE, | |
b033271f CLG |
521 | .instance_size = sizeof(AspeedSoCState), |
522 | .class_size = sizeof(AspeedSoCClass), | |
54ecafb7 | 523 | .class_init = aspeed_soc_class_init, |
b033271f | 524 | .abstract = true, |
43e3346e AJ |
525 | }; |
526 | ||
54ecafb7 | 527 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) |
43e3346e | 528 | { |
54ecafb7 | 529 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
b033271f | 530 | |
54ecafb7 CLG |
531 | sc->name = "ast2400-a1"; |
532 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | |
533 | sc->silicon_rev = AST2400_A1_SILICON_REV; | |
534 | sc->sram_size = 0x8000; | |
535 | sc->spis_num = 1; | |
bfdd34f1 | 536 | sc->ehcis_num = 1; |
54ecafb7 | 537 | sc->wdts_num = 2; |
d300db02 | 538 | sc->macs_num = 2; |
c5e1bdb9 | 539 | sc->uarts_num = 5; |
54ecafb7 CLG |
540 | sc->irqmap = aspeed_soc_ast2400_irqmap; |
541 | sc->memmap = aspeed_soc_ast2400_memmap; | |
542 | sc->num_cpus = 1; | |
699db715 | 543 | sc->get_irq = aspeed_soc_ast2400_get_irq; |
54ecafb7 CLG |
544 | } |
545 | ||
546 | static const TypeInfo aspeed_soc_ast2400_type_info = { | |
547 | .name = "ast2400-a1", | |
548 | .parent = TYPE_ASPEED_SOC, | |
549 | .instance_init = aspeed_soc_init, | |
550 | .instance_size = sizeof(AspeedSoCState), | |
551 | .class_init = aspeed_soc_ast2400_class_init, | |
552 | }; | |
553 | ||
554 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | |
555 | { | |
556 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
557 | ||
558 | sc->name = "ast2500-a1"; | |
559 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
560 | sc->silicon_rev = AST2500_A1_SILICON_REV; | |
561 | sc->sram_size = 0x9000; | |
562 | sc->spis_num = 2; | |
bfdd34f1 | 563 | sc->ehcis_num = 2; |
54ecafb7 | 564 | sc->wdts_num = 3; |
d300db02 | 565 | sc->macs_num = 2; |
c5e1bdb9 | 566 | sc->uarts_num = 5; |
54ecafb7 CLG |
567 | sc->irqmap = aspeed_soc_ast2500_irqmap; |
568 | sc->memmap = aspeed_soc_ast2500_memmap; | |
569 | sc->num_cpus = 1; | |
699db715 | 570 | sc->get_irq = aspeed_soc_ast2400_get_irq; |
43e3346e AJ |
571 | } |
572 | ||
54ecafb7 CLG |
573 | static const TypeInfo aspeed_soc_ast2500_type_info = { |
574 | .name = "ast2500-a1", | |
575 | .parent = TYPE_ASPEED_SOC, | |
576 | .instance_init = aspeed_soc_init, | |
577 | .instance_size = sizeof(AspeedSoCState), | |
578 | .class_init = aspeed_soc_ast2500_class_init, | |
579 | }; | |
580 | static void aspeed_soc_register_types(void) | |
581 | { | |
582 | type_register_static(&aspeed_soc_type_info); | |
583 | type_register_static(&aspeed_soc_ast2400_type_info); | |
584 | type_register_static(&aspeed_soc_ast2500_type_info); | |
585 | }; | |
586 | ||
699db715 CLG |
587 | type_init(aspeed_soc_register_types); |
588 | ||
589 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) | |
590 | { | |
591 | return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); | |
592 | } | |
470253b6 | 593 | |
d2b3eaef | 594 | bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) |
470253b6 PD |
595 | { |
596 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
d2b3eaef PD |
597 | SerialMM *smm; |
598 | ||
599 | for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { | |
600 | smm = &s->uart[i]; | |
601 | ||
602 | /* Chardev property is set by the machine. */ | |
603 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); | |
604 | qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); | |
605 | qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); | |
606 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); | |
607 | if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { | |
608 | return false; | |
6827ff20 | 609 | } |
d2b3eaef PD |
610 | |
611 | sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); | |
612 | aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); | |
6827ff20 | 613 | } |
d2b3eaef PD |
614 | |
615 | return true; | |
616 | } | |
617 | ||
618 | void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) | |
619 | { | |
620 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
621 | int i = dev - ASPEED_DEV_UART1; | |
622 | ||
623 | g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); | |
624 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); | |
470253b6 | 625 | } |
346160cb CLG |
626 | |
627 | /* | |
628 | * SDMC should be realized first to get correct RAM size and max size | |
629 | * values | |
630 | */ | |
631 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) | |
632 | { | |
633 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
634 | ram_addr_t ram_size, max_ram_size; | |
635 | ||
636 | ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", | |
637 | &error_abort); | |
638 | max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", | |
639 | &error_abort); | |
640 | ||
641 | memory_region_init(&s->dram_container, OBJECT(s), "ram-container", | |
642 | max_ram_size); | |
643 | memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); | |
644 | ||
645 | /* | |
646 | * Add a memory region beyond the RAM region to let firmwares scan | |
647 | * the address space with load/store and guess how much RAM the | |
648 | * SoC has. | |
649 | */ | |
650 | if (ram_size < max_ram_size) { | |
651 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); | |
652 | ||
653 | qdev_prop_set_string(dev, "name", "ram-empty"); | |
654 | qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); | |
655 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { | |
656 | return false; | |
657 | } | |
658 | ||
659 | memory_region_add_subregion_overlap(&s->dram_container, ram_size, | |
660 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); | |
661 | } | |
662 | ||
4dd9d554 | 663 | memory_region_add_subregion(s->memory, |
346160cb CLG |
664 | sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); |
665 | return true; | |
666 | } | |
5bfcbda7 PD |
667 | |
668 | void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr) | |
669 | { | |
670 | memory_region_add_subregion(s->memory, addr, | |
671 | sysbus_mmio_get_region(dev, n)); | |
672 | } | |
80beb085 PD |
673 | |
674 | void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, | |
675 | const char *name, hwaddr addr, uint64_t size) | |
676 | { | |
677 | qdev_prop_set_string(DEVICE(dev), "name", name); | |
678 | qdev_prop_set_uint64(DEVICE(dev), "size", size); | |
679 | sysbus_realize(dev, &error_abort); | |
680 | ||
681 | memory_region_add_subregion_overlap(s->memory, addr, | |
682 | sysbus_mmio_get_region(dev, 0), -1000); | |
683 | } |