[mirror_qemu.git] / hw / arm / aspeed_soc.c

/*
 * ASPEED SoC family
 *
 * Andrew Jeffery <andrew@aj.id.au>
 * Jeremy Kerr <jk@ozlabs.org>
 *
 * Copyright 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"

#define ASPEED_SOC_IOMEM_SIZE       0x00200000

static const hwaddr aspeed_soc_ast2400_memmap[] = {
    [ASPEED_IOMEM]  = 0x1E600000,
    [ASPEED_FMC]    = 0x1E620000,
    [ASPEED_SPI1]   = 0x1E630000,
    [ASPEED_VIC]    = 0x1E6C0000,
    [ASPEED_SDMC]   = 0x1E6E0000,
    [ASPEED_SCU]    = 0x1E6E2000,
    [ASPEED_ADC]    = 0x1E6E9000,
    [ASPEED_SRAM]   = 0x1E720000,
    [ASPEED_GPIO]   = 0x1E780000,
    [ASPEED_RTC]    = 0x1E781000,
    [ASPEED_TIMER1] = 0x1E782000,
    [ASPEED_WDT]    = 0x1E785000,
    [ASPEED_PWM]    = 0x1E786000,
    [ASPEED_LPC]    = 0x1E789000,
    [ASPEED_IBT]    = 0x1E789140,
    [ASPEED_I2C]    = 0x1E78A000,
    [ASPEED_ETH1]   = 0x1E660000,
    [ASPEED_ETH2]   = 0x1E680000,
    [ASPEED_UART1]  = 0x1E783000,
    [ASPEED_UART5]  = 0x1E784000,
    [ASPEED_VUART]  = 0x1E787000,
    [ASPEED_SDRAM]  = 0x40000000,
};

static const hwaddr aspeed_soc_ast2500_memmap[] = {
    [ASPEED_IOMEM]  = 0x1E600000,
    [ASPEED_FMC]    = 0x1E620000,
    [ASPEED_SPI1]   = 0x1E630000,
    [ASPEED_SPI2]   = 0x1E631000,
    [ASPEED_VIC]    = 0x1E6C0000,
    [ASPEED_SDMC]   = 0x1E6E0000,
    [ASPEED_SCU]    = 0x1E6E2000,
    [ASPEED_ADC]    = 0x1E6E9000,
    [ASPEED_SRAM]   = 0x1E720000,
    [ASPEED_GPIO]   = 0x1E780000,
    [ASPEED_RTC]    = 0x1E781000,
    [ASPEED_TIMER1] = 0x1E782000,
    [ASPEED_WDT]    = 0x1E785000,
    [ASPEED_PWM]    = 0x1E786000,
    [ASPEED_LPC]    = 0x1E789000,
    [ASPEED_IBT]    = 0x1E789140,
    [ASPEED_I2C]    = 0x1E78A000,
    [ASPEED_ETH1]   = 0x1E660000,
    [ASPEED_ETH2]   = 0x1E680000,
    [ASPEED_UART1]  = 0x1E783000,
    [ASPEED_UART5]  = 0x1E784000,
    [ASPEED_VUART]  = 0x1E787000,
    [ASPEED_SDRAM]  = 0x80000000,
};

static const int aspeed_soc_ast2400_irqmap[] = {
    [ASPEED_UART1]  = 9,
    [ASPEED_UART2]  = 32,
    [ASPEED_UART3]  = 33,
    [ASPEED_UART4]  = 34,
    [ASPEED_UART5]  = 10,
    [ASPEED_VUART]  = 8,
    [ASPEED_FMC]    = 19,
    [ASPEED_SDMC]   = 0,
    [ASPEED_SCU]    = 21,
    [ASPEED_ADC]    = 31,
    [ASPEED_GPIO]   = 20,
    [ASPEED_RTC]    = 22,
    [ASPEED_TIMER1] = 16,
    [ASPEED_TIMER2] = 17,
    [ASPEED_TIMER3] = 18,
    [ASPEED_TIMER4] = 35,
    [ASPEED_TIMER5] = 36,
    [ASPEED_TIMER6] = 37,
    [ASPEED_TIMER7] = 38,
    [ASPEED_TIMER8] = 39,
    [ASPEED_WDT]    = 27,
    [ASPEED_PWM]    = 28,
    [ASPEED_LPC]    = 8,
    [ASPEED_IBT]    = 8, /* LPC */
    [ASPEED_I2C]    = 12,
    [ASPEED_ETH1]   = 2,
    [ASPEED_ETH2]   = 3,
};

#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap

static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
static const char *aspeed_soc_ast2500_typenames[] = {
    "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };

static const AspeedSoCInfo aspeed_socs[] = {
    {
        .name         = "ast2400-a0",
        .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
        .silicon_rev  = AST2400_A0_SILICON_REV,
        .sram_size    = 0x8000,
        .spis_num     = 1,
        .fmc_typename = "aspeed.smc.fmc",
        .spi_typename = aspeed_soc_ast2400_typenames,
        .wdts_num     = 2,
        .irqmap       = aspeed_soc_ast2400_irqmap,
        .memmap       = aspeed_soc_ast2400_memmap,
        .num_cpus     = 1,
    }, {
        .name         = "ast2400-a1",
        .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
        .silicon_rev  = AST2400_A1_SILICON_REV,
        .sram_size    = 0x8000,
        .spis_num     = 1,
        .fmc_typename = "aspeed.smc.fmc",
        .spi_typename = aspeed_soc_ast2400_typenames,
        .wdts_num     = 2,
        .irqmap       = aspeed_soc_ast2400_irqmap,
        .memmap       = aspeed_soc_ast2400_memmap,
        .num_cpus     = 1,
    }, {
        .name         = "ast2400",
        .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
        .silicon_rev  = AST2400_A0_SILICON_REV,
        .sram_size    = 0x8000,
        .spis_num     = 1,
        .fmc_typename = "aspeed.smc.fmc",
        .spi_typename = aspeed_soc_ast2400_typenames,
        .wdts_num     = 2,
        .irqmap       = aspeed_soc_ast2400_irqmap,
        .memmap       = aspeed_soc_ast2400_memmap,
        .num_cpus     = 1,
    }, {
        .name         = "ast2500-a1",
        .cpu_type     = ARM_CPU_TYPE_NAME("arm1176"),
        .silicon_rev  = AST2500_A1_SILICON_REV,
        .sram_size    = 0x9000,
        .spis_num     = 2,
        .fmc_typename = "aspeed.smc.ast2500-fmc",
        .spi_typename = aspeed_soc_ast2500_typenames,
        .wdts_num     = 3,
        .irqmap       = aspeed_soc_ast2500_irqmap,
        .memmap       = aspeed_soc_ast2500_memmap,
        .num_cpus     = 1,
    },
};

static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
{
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

    return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
}

static void aspeed_soc_init(Object *obj)
{
    AspeedSoCState *s = ASPEED_SOC(obj);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int i;

    for (i = 0; i < sc->info->num_cpus; i++) {
        object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
                                sizeof(s->cpu[i]), sc->info->cpu_type,
                                &error_abort, NULL);
    }

    sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
                          TYPE_ASPEED_SCU);
    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
                         sc->info->silicon_rev);
    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                              "hw-strap1", &error_abort);
    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
                              "hw-strap2", &error_abort);
    object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                              "hw-prot-key", &error_abort);

    sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
                          TYPE_ASPEED_VIC);

    sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
                          TYPE_ASPEED_RTC);

    sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
                          sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
    object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
                                   OBJECT(&s->scu), &error_abort);

    sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
                          TYPE_ASPEED_I2C);

    sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
                          sc->info->fmc_typename);
    object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
                              &error_abort);

    for (i = 0; i < sc->info->spis_num; i++) {
        sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
                              sizeof(s->spi[i]), sc->info->spi_typename[i]);
    }

    sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
                          TYPE_ASPEED_SDMC);
    qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
                         sc->info->silicon_rev);
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                              "ram-size", &error_abort);
    object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
                              "max-ram-size", &error_abort);

    for (i = 0; i < sc->info->wdts_num; i++) {
        sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
                              sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
        qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
                                    sc->info->silicon_rev);
    }

    for (i = 0; i < ASPEED_MACS_NUM; i++) {
        sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
                              sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
    }
}

static void aspeed_soc_realize(DeviceState *dev, Error **errp)
{
    int i;
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    Error *err = NULL, *local_err = NULL;

    /* IO space */
    create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
                                ASPEED_SOC_IOMEM_SIZE);

    if (s->num_cpus > sc->info->num_cpus) {
        warn_report("%s: invalid number of CPUs %d, using default %d",
                    sc->info->name, s->num_cpus, sc->info->num_cpus);
        s->num_cpus = sc->info->num_cpus;
    }

    /* CPU */
    for (i = 0; i < s->num_cpus; i++) {
        object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    /* SRAM */
    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
                           sc->info->sram_size, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(),
                                sc->info->memmap[ASPEED_SRAM], &s->sram);

    /* SCU */
    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);

    /* VIC */
    object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    /* RTC */
    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
                       aspeed_soc_get_irq(s, ASPEED_RTC));

    /* Timer */
    object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
                    sc->info->memmap[ASPEED_TIMER1]);
    for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
        qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
    }

    /* UART - attach an 8250 to the IO space as our UART5 */
    if (serial_hd(0)) {
        qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
        serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
                       uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
    }

    /* I2C */
    object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
                       aspeed_soc_get_irq(s, ASPEED_I2C));

    /* FMC, The number of CS is set at the board level */
    object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
                            "sdram-base", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
                    s->fmc.ctrl->flash_window_base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
                       aspeed_soc_get_irq(s, ASPEED_FMC));

    /* SPI */
    for (i = 0; i < sc->info->spis_num; i++) {
        object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
                        sc->info->memmap[ASPEED_SPI1 + i]);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
                        s->spi[i].ctrl->flash_window_base);
    }

    /* SDMC - SDRAM Memory Controller */
    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);

    /* Watch dog */
    for (i = 0; i < sc->info->wdts_num; i++) {
        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
                        sc->info->memmap[ASPEED_WDT] + i * 0x20);
    }

    /* Net */
    for (i = 0; i < nb_nics; i++) {
        qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
                                 &err);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
                                 &local_err);
        error_propagate(&err, local_err);
        if (err) {
            error_propagate(errp, err);
           return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                        sc->info->memmap[ASPEED_ETH1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                           aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
    }
}
static Property aspeed_soc_properties[] = {
    DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    sc->info = (AspeedSoCInfo *) data;
    dc->realize = aspeed_soc_realize;
    /* Reason: Uses serial_hds and nd_table in realize() directly */
    dc->user_creatable = false;
    dc->props = aspeed_soc_properties;
}

static const TypeInfo aspeed_soc_type_info = {
    .name           = TYPE_ASPEED_SOC,
    .parent         = TYPE_DEVICE,
    .instance_init  = aspeed_soc_init,
    .instance_size  = sizeof(AspeedSoCState),
    .class_size     = sizeof(AspeedSoCClass),
    .abstract       = true,
};

static void aspeed_soc_register_types(void)
{
    int i;

    type_register_static(&aspeed_soc_type_info);
    for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
        TypeInfo ti = {
            .name       = aspeed_socs[i].name,
            .parent     = TYPE_ASPEED_SOC,
            .class_init = aspeed_soc_class_init,
            .class_data = (void *) &aspeed_socs[i],
        };
        type_register(&ti);
    }
}

type_init(aspeed_soc_register_types)
Commit	Line	Data
43e3346e	1	/*
ff90606f	2	* ASPEED SoC family
43e3346e AJ	3	*
	4	* Andrew Jeffery <andrew@aj.id.au>
	5	* Jeremy Kerr <jk@ozlabs.org>
	6	*
	7	* Copyright 2016 IBM Corp.
	8	*
	9	* This code is licensed under the GPL version 2 or later. See
	10	* the COPYING file in the top-level directory.
	11	*/
	12
	13	#include "qemu/osdep.h"
da34e65c	14	#include "qapi/error.h"
4771d756	15	#include "cpu.h"
43e3346e	16	#include "exec/address-spaces.h"
c7c3c9f8	17	#include "hw/misc/unimp.h"
00442402	18	#include "hw/arm/aspeed_soc.h"
43e3346e	19	#include "hw/char/serial.h"
03dd024f	20	#include "qemu/log.h"
0b8fa32f	21	#include "qemu/module.h"
ece09bee	22	#include "qemu/error-report.h"
16020011	23	#include "hw/i2c/aspeed_i2c.h"
ea337c65	24	#include "net/net.h"
43e3346e	25
ff90606f	26	#define ASPEED_SOC_IOMEM_SIZE 0x00200000
d783d1fe CLG	27
	28	static const hwaddr aspeed_soc_ast2400_memmap[] = {
	29	[ASPEED_IOMEM] = 0x1E600000,
	30	[ASPEED_FMC] = 0x1E620000,
	31	[ASPEED_SPI1] = 0x1E630000,
	32	[ASPEED_VIC] = 0x1E6C0000,
	33	[ASPEED_SDMC] = 0x1E6E0000,
	34	[ASPEED_SCU] = 0x1E6E2000,
	35	[ASPEED_ADC] = 0x1E6E9000,
	36	[ASPEED_SRAM] = 0x1E720000,
	37	[ASPEED_GPIO] = 0x1E780000,
	38	[ASPEED_RTC] = 0x1E781000,
	39	[ASPEED_TIMER1] = 0x1E782000,
	40	[ASPEED_WDT] = 0x1E785000,
	41	[ASPEED_PWM] = 0x1E786000,
	42	[ASPEED_LPC] = 0x1E789000,
	43	[ASPEED_IBT] = 0x1E789140,
	44	[ASPEED_I2C] = 0x1E78A000,
	45	[ASPEED_ETH1] = 0x1E660000,
	46	[ASPEED_ETH2] = 0x1E680000,
	47	[ASPEED_UART1] = 0x1E783000,
	48	[ASPEED_UART5] = 0x1E784000,
	49	[ASPEED_VUART] = 0x1E787000,
	50	[ASPEED_SDRAM] = 0x40000000,
	51	};
	52
	53	static const hwaddr aspeed_soc_ast2500_memmap[] = {
	54	[ASPEED_IOMEM] = 0x1E600000,
	55	[ASPEED_FMC] = 0x1E620000,
	56	[ASPEED_SPI1] = 0x1E630000,
	57	[ASPEED_SPI2] = 0x1E631000,
	58	[ASPEED_VIC] = 0x1E6C0000,
	59	[ASPEED_SDMC] = 0x1E6E0000,
	60	[ASPEED_SCU] = 0x1E6E2000,
	61	[ASPEED_ADC] = 0x1E6E9000,
	62	[ASPEED_SRAM] = 0x1E720000,
	63	[ASPEED_GPIO] = 0x1E780000,
	64	[ASPEED_RTC] = 0x1E781000,
	65	[ASPEED_TIMER1] = 0x1E782000,
	66	[ASPEED_WDT] = 0x1E785000,
	67	[ASPEED_PWM] = 0x1E786000,
	68	[ASPEED_LPC] = 0x1E789000,
	69	[ASPEED_IBT] = 0x1E789140,
	70	[ASPEED_I2C] = 0x1E78A000,
	71	[ASPEED_ETH1] = 0x1E660000,
	72	[ASPEED_ETH2] = 0x1E680000,
	73	[ASPEED_UART1] = 0x1E783000,
	74	[ASPEED_UART5] = 0x1E784000,
	75	[ASPEED_VUART] = 0x1E787000,
	76	[ASPEED_SDRAM] = 0x80000000,
	77	};
ff90606f	78
b456b113 CLG	79	static const int aspeed_soc_ast2400_irqmap[] = {
	80	[ASPEED_UART1] = 9,
	81	[ASPEED_UART2] = 32,
	82	[ASPEED_UART3] = 33,
	83	[ASPEED_UART4] = 34,
	84	[ASPEED_UART5] = 10,
	85	[ASPEED_VUART] = 8,
	86	[ASPEED_FMC] = 19,
	87	[ASPEED_SDMC] = 0,
	88	[ASPEED_SCU] = 21,
	89	[ASPEED_ADC] = 31,
	90	[ASPEED_GPIO] = 20,
	91	[ASPEED_RTC] = 22,
	92	[ASPEED_TIMER1] = 16,
	93	[ASPEED_TIMER2] = 17,
	94	[ASPEED_TIMER3] = 18,
	95	[ASPEED_TIMER4] = 35,
	96	[ASPEED_TIMER5] = 36,
	97	[ASPEED_TIMER6] = 37,
	98	[ASPEED_TIMER7] = 38,
	99	[ASPEED_TIMER8] = 39,
	100	[ASPEED_WDT] = 27,
	101	[ASPEED_PWM] = 28,
	102	[ASPEED_LPC] = 8,
	103	[ASPEED_IBT] = 8, /* LPC */
	104	[ASPEED_I2C] = 12,
	105	[ASPEED_ETH1] = 2,
	106	[ASPEED_ETH2] = 3,
	107	};
43e3346e	108
b456b113 CLG	109	#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
b456b113 CLG	110
6dc52326	111	static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
6dc52326 CLG	112	static const char *aspeed_soc_ast2500_typenames[] = {
6dc52326 CLG	113	"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
dbcabeeb	114
b033271f	115	static const AspeedSoCInfo aspeed_socs[] = {
74af4eec CLG	116	{
74af4eec CLG	117	.name = "ast2400-a0",
ba1ba5cc	118	.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
74af4eec	119	.silicon_rev = AST2400_A0_SILICON_REV,
74af4eec CLG	120	.sram_size = 0x8000,
74af4eec CLG	121	.spis_num = 1,
74af4eec CLG	122	.fmc_typename = "aspeed.smc.fmc",
74af4eec CLG	123	.spi_typename = aspeed_soc_ast2400_typenames,
f986ee1d	124	.wdts_num = 2,
b456b113	125	.irqmap = aspeed_soc_ast2400_irqmap,
d783d1fe	126	.memmap = aspeed_soc_ast2400_memmap,
ece09bee	127	.num_cpus = 1,
6efbac90 CLG	128	}, {
6efbac90 CLG	129	.name = "ast2400-a1",
ba1ba5cc	130	.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
6efbac90	131	.silicon_rev = AST2400_A1_SILICON_REV,
6efbac90 CLG	132	.sram_size = 0x8000,
6efbac90 CLG	133	.spis_num = 1,
6efbac90 CLG	134	.fmc_typename = "aspeed.smc.fmc",
6efbac90 CLG	135	.spi_typename = aspeed_soc_ast2400_typenames,
f986ee1d	136	.wdts_num = 2,
b456b113	137	.irqmap = aspeed_soc_ast2400_irqmap,
d783d1fe	138	.memmap = aspeed_soc_ast2400_memmap,
ece09bee	139	.num_cpus = 1,
74af4eec CLG	140	}, {
74af4eec CLG	141	.name = "ast2400",
ba1ba5cc	142	.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
74af4eec	143	.silicon_rev = AST2400_A0_SILICON_REV,
74af4eec CLG	144	.sram_size = 0x8000,
74af4eec CLG	145	.spis_num = 1,
74af4eec CLG	146	.fmc_typename = "aspeed.smc.fmc",
74af4eec CLG	147	.spi_typename = aspeed_soc_ast2400_typenames,
f986ee1d	148	.wdts_num = 2,
b456b113	149	.irqmap = aspeed_soc_ast2400_irqmap,
d783d1fe	150	.memmap = aspeed_soc_ast2400_memmap,
ece09bee	151	.num_cpus = 1,
74af4eec CLG	152	}, {
74af4eec CLG	153	.name = "ast2500-a1",
ba1ba5cc	154	.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
74af4eec	155	.silicon_rev = AST2500_A1_SILICON_REV,
74af4eec CLG	156	.sram_size = 0x9000,
74af4eec CLG	157	.spis_num = 2,
74af4eec CLG	158	.fmc_typename = "aspeed.smc.ast2500-fmc",
74af4eec CLG	159	.spi_typename = aspeed_soc_ast2500_typenames,
f986ee1d	160	.wdts_num = 3,
b456b113	161	.irqmap = aspeed_soc_ast2500_irqmap,
d783d1fe	162	.memmap = aspeed_soc_ast2500_memmap,
ece09bee	163	.num_cpus = 1,
74af4eec	164	},
b033271f CLG	165	};
b033271f CLG	166
b456b113 CLG	167	static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
	168	{
	169	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
	170
	171	return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
	172	}
	173
ff90606f	174	static void aspeed_soc_init(Object *obj)
43e3346e	175	{
ff90606f	176	AspeedSoCState *s = ASPEED_SOC(obj);
b033271f	177	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
dbcabeeb	178	int i;
43e3346e	179
ece09bee CLG	180	for (i = 0; i < sc->info->num_cpus; i++) {
	181	object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
	182	sizeof(s->cpu[i]), sc->info->cpu_type,
	183	&error_abort, NULL);
	184	}
43e3346e	185
1b0ad567 PMD	186	sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
1b0ad567 PMD	187	TYPE_ASPEED_SCU);
334973bb	188	qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
b033271f	189	sc->info->silicon_rev);
334973bb AJ	190	object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
	191	"hw-strap1", &error_abort);
	192	object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
	193	"hw-strap2", &error_abort);
b6e70d1d JS	194	object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
b6e70d1d JS	195	"hw-prot-key", &error_abort);
7c1c69bc	196
1b0ad567 PMD	197	sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
1b0ad567 PMD	198	TYPE_ASPEED_VIC);
e2a11ca8	199
75fb4577 JS	200	sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
	201	TYPE_ASPEED_RTC);
	202
1b0ad567 PMD	203	sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
1b0ad567 PMD	204	sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
9b945a9e CLG	205	object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
9b945a9e CLG	206	OBJECT(&s->scu), &error_abort);
e2a11ca8	207
1b0ad567 PMD	208	sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
1b0ad567 PMD	209	TYPE_ASPEED_I2C);
e2a11ca8	210
1b0ad567 PMD	211	sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
1b0ad567 PMD	212	sc->info->fmc_typename);
26d5df95 CLG	213	object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
26d5df95 CLG	214	&error_abort);
7c1c69bc	215
dbcabeeb	216	for (i = 0; i < sc->info->spis_num; i++) {
1b0ad567 PMD	217	sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
1b0ad567 PMD	218	sizeof(s->spi[i]), sc->info->spi_typename[i]);
dbcabeeb	219	}
c2da8a8b	220
1b0ad567 PMD	221	sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
1b0ad567 PMD	222	TYPE_ASPEED_SDMC);
c2da8a8b	223	qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
b033271f	224	sc->info->silicon_rev);
c6c7cfb0 CLG	225	object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
c6c7cfb0 CLG	226	"ram-size", &error_abort);
ebe31c0a CLG	227	object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
ebe31c0a CLG	228	"max-ram-size", &error_abort);
013befe1	229
f986ee1d	230	for (i = 0; i < sc->info->wdts_num; i++) {
1b0ad567 PMD	231	sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
1b0ad567 PMD	232	sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
429789cc AJ	233	qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
429789cc AJ	234	sc->info->silicon_rev);
f986ee1d	235	}
ea337c65	236
67340990 CLG	237	for (i = 0; i < ASPEED_MACS_NUM; i++) {
	238	sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
	239	sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
	240	}
43e3346e AJ	241	}
43e3346e AJ	242
ff90606f	243	static void aspeed_soc_realize(DeviceState dev, Error *errp)
43e3346e AJ	244	{
43e3346e AJ	245	int i;
ff90606f	246	AspeedSoCState *s = ASPEED_SOC(dev);
dbcabeeb	247	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
7c1c69bc	248	Error err = NULL, local_err = NULL;
43e3346e AJ	249
43e3346e AJ	250	/* IO space */
d783d1fe CLG	251	create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
d783d1fe CLG	252	ASPEED_SOC_IOMEM_SIZE);
43e3346e	253
ece09bee CLG	254	if (s->num_cpus > sc->info->num_cpus) {
	255	warn_report("%s: invalid number of CPUs %d, using default %d",
	256	sc->info->name, s->num_cpus, sc->info->num_cpus);
	257	s->num_cpus = sc->info->num_cpus;
	258	}
	259
2d105bd6	260	/* CPU */
ece09bee CLG	261	for (i = 0; i < s->num_cpus; i++) {
	262	object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
	263	if (err) {
	264	error_propagate(errp, err);
	265	return;
	266	}
2d105bd6 CLG	267	}
2d105bd6 CLG	268
74af4eec	269	/* SRAM */
a2e9989c	270	memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
74af4eec CLG	271	sc->info->sram_size, &err);
	272	if (err) {
	273	error_propagate(errp, err);
	274	return;
	275	}
d783d1fe CLG	276	memory_region_add_subregion(get_system_memory(),
d783d1fe CLG	277	sc->info->memmap[ASPEED_SRAM], &s->sram);
74af4eec	278
e2a11ca8 CLG	279	/* SCU */
	280	object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
	281	if (err) {
	282	error_propagate(errp, err);
	283	return;
	284	}
d783d1fe	285	sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
e2a11ca8	286
43e3346e AJ	287	/* VIC */
	288	object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
	289	if (err) {
	290	error_propagate(errp, err);
	291	return;
	292	}
d783d1fe	293	sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
43e3346e	294	sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
2d105bd6	295	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
43e3346e	296	sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
2d105bd6	297	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
43e3346e	298
75fb4577 JS	299	/* RTC */
	300	object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
	301	if (err) {
	302	error_propagate(errp, err);
	303	return;
	304	}
	305	sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
	306	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
	307	aspeed_soc_get_irq(s, ASPEED_RTC));
	308
43e3346e AJ	309	/* Timer */
	310	object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
	311	if (err) {
	312	error_propagate(errp, err);
	313	return;
	314	}
d783d1fe CLG	315	sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
d783d1fe CLG	316	sc->info->memmap[ASPEED_TIMER1]);
b456b113 CLG	317	for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
b456b113 CLG	318	qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
43e3346e AJ	319	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
	320	}
	321
	322	/* UART - attach an 8250 to the IO space as our UART5 */
9bca0edb	323	if (serial_hd(0)) {
b456b113	324	qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
d783d1fe	325	serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
9bca0edb	326	uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
43e3346e	327	}
16020011 CLG	328
	329	/* I2C */
	330	object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
	331	if (err) {
	332	error_propagate(errp, err);
	333	return;
	334	}
d783d1fe	335	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
16020011	336	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
b456b113	337	aspeed_soc_get_irq(s, ASPEED_I2C));
7c1c69bc	338
26d5df95	339	/* FMC, The number of CS is set at the board level */
6da4433f CLG	340	object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
	341	"sdram-base", &err);
	342	if (err) {
	343	error_propagate(errp, err);
	344	return;
	345	}
26d5df95	346	object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
7c1c69bc CLG	347	if (err) {
	348	error_propagate(errp, err);
	349	return;
	350	}
d783d1fe	351	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
dcb83444 CLG	352	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
dcb83444 CLG	353	s->fmc.ctrl->flash_window_base);
0e5803df	354	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
b456b113	355	aspeed_soc_get_irq(s, ASPEED_FMC));
7c1c69bc CLG	356
7c1c69bc CLG	357	/* SPI */
dbcabeeb CLG	358	for (i = 0; i < sc->info->spis_num; i++) {
	359	object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
	360	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
	361	&local_err);
	362	error_propagate(&err, local_err);
	363	if (err) {
	364	error_propagate(errp, err);
	365	return;
	366	}
d783d1fe CLG	367	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
d783d1fe CLG	368	sc->info->memmap[ASPEED_SPI1 + i]);
dbcabeeb CLG	369	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
dbcabeeb CLG	370	s->spi[i].ctrl->flash_window_base);
7c1c69bc	371	}
c2da8a8b CLG	372
	373	/* SDMC - SDRAM Memory Controller */
	374	object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
	375	if (err) {
	376	error_propagate(errp, err);
	377	return;
	378	}
d783d1fe	379	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
013befe1 CLG	380
013befe1 CLG	381	/* Watch dog */
f986ee1d JS	382	for (i = 0; i < sc->info->wdts_num; i++) {
	383	object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
	384	if (err) {
	385	error_propagate(errp, err);
	386	return;
	387	}
	388	sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
d783d1fe	389	sc->info->memmap[ASPEED_WDT] + i * 0x20);
013befe1	390	}
ea337c65 CLG	391
ea337c65 CLG	392	/* Net */
67340990 CLG	393	for (i = 0; i < nb_nics; i++) {
	394	qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
	395	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
	396	&err);
	397	object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
	398	&local_err);
	399	error_propagate(&err, local_err);
	400	if (err) {
	401	error_propagate(errp, err);
	402	return;
	403	}
	404	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
	405	sc->info->memmap[ASPEED_ETH1 + i]);
	406	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
	407	aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
ea337c65	408	}
43e3346e	409	}
ece09bee CLG	410	static Property aspeed_soc_properties[] = {
	411	DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
	412	DEFINE_PROP_END_OF_LIST(),
	413	};
43e3346e	414
ff90606f	415	static void aspeed_soc_class_init(ObjectClass oc, void data)
43e3346e AJ	416	{
43e3346e AJ	417	DeviceClass *dc = DEVICE_CLASS(oc);
b033271f	418	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
43e3346e	419
b033271f	420	sc->info = (AspeedSoCInfo *) data;
ff90606f	421	dc->realize = aspeed_soc_realize;
469f3da4 TH	422	/* Reason: Uses serial_hds and nd_table in realize() directly */
469f3da4 TH	423	dc->user_creatable = false;
ece09bee	424	dc->props = aspeed_soc_properties;
43e3346e AJ	425	}
43e3346e AJ	426
ff90606f	427	static const TypeInfo aspeed_soc_type_info = {
b033271f CLG	428	.name = TYPE_ASPEED_SOC,
	429	.parent = TYPE_DEVICE,
	430	.instance_init = aspeed_soc_init,
	431	.instance_size = sizeof(AspeedSoCState),
	432	.class_size = sizeof(AspeedSoCClass),
	433	.abstract = true,
43e3346e AJ	434	};
43e3346e AJ	435
ff90606f	436	static void aspeed_soc_register_types(void)
43e3346e	437	{
b033271f CLG	438	int i;
b033271f CLG	439
ff90606f	440	type_register_static(&aspeed_soc_type_info);
b033271f CLG	441	for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
	442	TypeInfo ti = {
	443	.name = aspeed_socs[i].name,
	444	.parent = TYPE_ASPEED_SOC,
	445	.class_init = aspeed_soc_class_init,
	446	.class_data = (void *) &aspeed_socs[i],
	447	};
	448	type_register(&ti);
	449	}
43e3346e AJ	450	}
43e3346e AJ	451
ff90606f	452	type_init(aspeed_soc_register_types)