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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
c7c3c9f8 | 15 | #include "hw/misc/unimp.h" |
00442402 | 16 | #include "hw/arm/aspeed_soc.h" |
43e3346e | 17 | #include "hw/char/serial.h" |
0b8fa32f | 18 | #include "qemu/module.h" |
ece09bee | 19 | #include "qemu/error-report.h" |
16020011 | 20 | #include "hw/i2c/aspeed_i2c.h" |
ea337c65 | 21 | #include "net/net.h" |
46517dd4 | 22 | #include "sysemu/sysemu.h" |
43e3346e | 23 | |
ff90606f | 24 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
d783d1fe CLG |
25 | |
26 | static const hwaddr aspeed_soc_ast2400_memmap[] = { | |
347df6f8 EH |
27 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
28 | [ASPEED_DEV_FMC] = 0x1E620000, | |
29 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
30 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
31 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
32 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
33 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 34 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
35 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
36 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
37 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
38 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
39 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
40 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
41 | [ASPEED_DEV_RTC] = 0x1E781000, | |
42 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
43 | [ASPEED_DEV_WDT] = 0x1E785000, | |
44 | [ASPEED_DEV_PWM] = 0x1E786000, | |
45 | [ASPEED_DEV_LPC] = 0x1E789000, | |
46 | [ASPEED_DEV_IBT] = 0x1E789140, | |
47 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
48 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
49 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
50 | [ASPEED_DEV_UART1] = 0x1E783000, | |
51 | [ASPEED_DEV_UART5] = 0x1E784000, | |
52 | [ASPEED_DEV_VUART] = 0x1E787000, | |
53 | [ASPEED_DEV_SDRAM] = 0x40000000, | |
d783d1fe CLG |
54 | }; |
55 | ||
56 | static const hwaddr aspeed_soc_ast2500_memmap[] = { | |
347df6f8 EH |
57 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
58 | [ASPEED_DEV_FMC] = 0x1E620000, | |
59 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
60 | [ASPEED_DEV_SPI2] = 0x1E631000, | |
61 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
62 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
63 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
64 | [ASPEED_DEV_SDMC] = 0x1E6E0000, | |
65 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
a3888d75 | 66 | [ASPEED_DEV_HACE] = 0x1E6E3000, |
347df6f8 EH |
67 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
68 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
69 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
70 | [ASPEED_DEV_SRAM] = 0x1E720000, | |
71 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
72 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
73 | [ASPEED_DEV_RTC] = 0x1E781000, | |
74 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
75 | [ASPEED_DEV_WDT] = 0x1E785000, | |
76 | [ASPEED_DEV_PWM] = 0x1E786000, | |
77 | [ASPEED_DEV_LPC] = 0x1E789000, | |
78 | [ASPEED_DEV_IBT] = 0x1E789140, | |
79 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
80 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
81 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
82 | [ASPEED_DEV_UART1] = 0x1E783000, | |
83 | [ASPEED_DEV_UART5] = 0x1E784000, | |
84 | [ASPEED_DEV_VUART] = 0x1E787000, | |
85 | [ASPEED_DEV_SDRAM] = 0x80000000, | |
d783d1fe | 86 | }; |
ff90606f | 87 | |
b456b113 | 88 | static const int aspeed_soc_ast2400_irqmap[] = { |
347df6f8 EH |
89 | [ASPEED_DEV_UART1] = 9, |
90 | [ASPEED_DEV_UART2] = 32, | |
91 | [ASPEED_DEV_UART3] = 33, | |
92 | [ASPEED_DEV_UART4] = 34, | |
93 | [ASPEED_DEV_UART5] = 10, | |
94 | [ASPEED_DEV_VUART] = 8, | |
95 | [ASPEED_DEV_FMC] = 19, | |
96 | [ASPEED_DEV_EHCI1] = 5, | |
97 | [ASPEED_DEV_EHCI2] = 13, | |
98 | [ASPEED_DEV_SDMC] = 0, | |
99 | [ASPEED_DEV_SCU] = 21, | |
100 | [ASPEED_DEV_ADC] = 31, | |
101 | [ASPEED_DEV_GPIO] = 20, | |
102 | [ASPEED_DEV_RTC] = 22, | |
103 | [ASPEED_DEV_TIMER1] = 16, | |
104 | [ASPEED_DEV_TIMER2] = 17, | |
105 | [ASPEED_DEV_TIMER3] = 18, | |
106 | [ASPEED_DEV_TIMER4] = 35, | |
107 | [ASPEED_DEV_TIMER5] = 36, | |
108 | [ASPEED_DEV_TIMER6] = 37, | |
109 | [ASPEED_DEV_TIMER7] = 38, | |
110 | [ASPEED_DEV_TIMER8] = 39, | |
111 | [ASPEED_DEV_WDT] = 27, | |
112 | [ASPEED_DEV_PWM] = 28, | |
113 | [ASPEED_DEV_LPC] = 8, | |
347df6f8 EH |
114 | [ASPEED_DEV_I2C] = 12, |
115 | [ASPEED_DEV_ETH1] = 2, | |
116 | [ASPEED_DEV_ETH2] = 3, | |
117 | [ASPEED_DEV_XDMA] = 6, | |
118 | [ASPEED_DEV_SDHCI] = 26, | |
a3888d75 | 119 | [ASPEED_DEV_HACE] = 4, |
b456b113 | 120 | }; |
43e3346e | 121 | |
b456b113 CLG |
122 | #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap |
123 | ||
b456b113 CLG |
124 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) |
125 | { | |
126 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
127 | ||
54ecafb7 | 128 | return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); |
b456b113 CLG |
129 | } |
130 | ||
ff90606f | 131 | static void aspeed_soc_init(Object *obj) |
43e3346e | 132 | { |
ff90606f | 133 | AspeedSoCState *s = ASPEED_SOC(obj); |
b033271f | 134 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
dbcabeeb | 135 | int i; |
811a5b1d CLG |
136 | char socname[8]; |
137 | char typename[64]; | |
138 | ||
54ecafb7 | 139 | if (sscanf(sc->name, "%7s", socname) != 1) { |
811a5b1d CLG |
140 | g_assert_not_reached(); |
141 | } | |
43e3346e | 142 | |
54ecafb7 | 143 | for (i = 0; i < sc->num_cpus; i++) { |
9fc7fc4d | 144 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
ece09bee | 145 | } |
43e3346e | 146 | |
9a937f6c | 147 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
db873cc5 | 148 | object_initialize_child(obj, "scu", &s->scu, typename); |
334973bb | 149 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
54ecafb7 | 150 | sc->silicon_rev); |
334973bb | 151 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
d2623129 | 152 | "hw-strap1"); |
334973bb | 153 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 154 | "hw-strap2"); |
b6e70d1d | 155 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 156 | "hw-prot-key"); |
7c1c69bc | 157 | |
db873cc5 | 158 | object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC); |
e2a11ca8 | 159 | |
db873cc5 | 160 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
75fb4577 | 161 | |
72d96f8e | 162 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
db873cc5 | 163 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
e2a11ca8 | 164 | |
f7da1aa8 | 165 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 166 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
e2a11ca8 | 167 | |
811a5b1d | 168 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 169 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
d2623129 | 170 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); |
7c1c69bc | 171 | |
54ecafb7 | 172 | for (i = 0; i < sc->spis_num; i++) { |
811a5b1d | 173 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
db873cc5 | 174 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
dbcabeeb | 175 | } |
c2da8a8b | 176 | |
bfdd34f1 | 177 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
178 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
179 | TYPE_PLATFORM_EHCI); | |
bfdd34f1 GR |
180 | } |
181 | ||
8e00d1a9 | 182 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 183 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
c6c7cfb0 | 184 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 185 | "ram-size"); |
ebe31c0a | 186 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
d2623129 | 187 | "max-ram-size"); |
013befe1 | 188 | |
54ecafb7 | 189 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d | 190 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
db873cc5 | 191 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f986ee1d | 192 | } |
ea337c65 | 193 | |
d300db02 | 194 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
195 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
196 | TYPE_FTGMAC100); | |
67340990 | 197 | } |
118c82e7 | 198 | |
8efbee28 CLG |
199 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
200 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
fdcc7c06 | 201 | |
811a5b1d | 202 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
db873cc5 | 203 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
2bea128c | 204 | |
db873cc5 | 205 | object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); |
2bea128c | 206 | |
5325cc34 | 207 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 208 | |
2bea128c EJ |
209 | /* Init sd card slot class here so that they're under the correct parent */ |
210 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
211 | object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], |
212 | TYPE_SYSBUS_SDHCI); | |
2bea128c | 213 | } |
2ecf1726 CLG |
214 | |
215 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
216 | |
217 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
218 | object_initialize_child(obj, "hace", &s->hace, typename); | |
43e3346e AJ |
219 | } |
220 | ||
ff90606f | 221 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
43e3346e AJ |
222 | { |
223 | int i; | |
ff90606f | 224 | AspeedSoCState *s = ASPEED_SOC(dev); |
dbcabeeb | 225 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
123327d1 | 226 | Error *err = NULL; |
43e3346e AJ |
227 | |
228 | /* IO space */ | |
347df6f8 | 229 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], |
d783d1fe | 230 | ASPEED_SOC_IOMEM_SIZE); |
43e3346e | 231 | |
514bcf6f | 232 | /* Video engine stub */ |
347df6f8 | 233 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], |
514bcf6f JS |
234 | 0x1000); |
235 | ||
2d105bd6 | 236 | /* CPU */ |
b7f1a0cb | 237 | for (i = 0; i < sc->num_cpus; i++) { |
668f62ec | 238 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
ece09bee CLG |
239 | return; |
240 | } | |
2d105bd6 CLG |
241 | } |
242 | ||
74af4eec | 243 | /* SRAM */ |
a2e9989c | 244 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", |
54ecafb7 | 245 | sc->sram_size, &err); |
74af4eec CLG |
246 | if (err) { |
247 | error_propagate(errp, err); | |
248 | return; | |
249 | } | |
d783d1fe | 250 | memory_region_add_subregion(get_system_memory(), |
347df6f8 | 251 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
74af4eec | 252 | |
e2a11ca8 | 253 | /* SCU */ |
668f62ec | 254 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
e2a11ca8 CLG |
255 | return; |
256 | } | |
347df6f8 | 257 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
e2a11ca8 | 258 | |
43e3346e | 259 | /* VIC */ |
668f62ec | 260 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) { |
43e3346e AJ |
261 | return; |
262 | } | |
347df6f8 | 263 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]); |
43e3346e | 264 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, |
2d105bd6 | 265 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
43e3346e | 266 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, |
2d105bd6 | 267 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
43e3346e | 268 | |
75fb4577 | 269 | /* RTC */ |
668f62ec | 270 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
75fb4577 JS |
271 | return; |
272 | } | |
347df6f8 | 273 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
75fb4577 | 274 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 275 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
75fb4577 | 276 | |
43e3346e | 277 | /* Timer */ |
5325cc34 MA |
278 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
279 | &error_abort); | |
668f62ec | 280 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
43e3346e AJ |
281 | return; |
282 | } | |
d783d1fe | 283 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, |
347df6f8 | 284 | sc->memmap[ASPEED_DEV_TIMER1]); |
b456b113 | 285 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 286 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
43e3346e AJ |
287 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
288 | } | |
289 | ||
5d63d0c7 PD |
290 | /* UART - attach an 8250 to the IO space as our UART */ |
291 | serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | |
292 | aspeed_soc_get_irq(s, s->uart_default), 38400, | |
a6b2f1fc | 293 | serial_hd(0), DEVICE_LITTLE_ENDIAN); |
16020011 CLG |
294 | |
295 | /* I2C */ | |
5325cc34 | 296 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 297 | &error_abort); |
668f62ec | 298 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
16020011 CLG |
299 | return; |
300 | } | |
347df6f8 | 301 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
16020011 | 302 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, |
347df6f8 | 303 | aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); |
7c1c69bc | 304 | |
26d5df95 | 305 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 306 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 307 | &error_abort); |
668f62ec | 308 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
7c1c69bc CLG |
309 | return; |
310 | } | |
347df6f8 | 311 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
dcb83444 CLG |
312 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
313 | s->fmc.ctrl->flash_window_base); | |
0e5803df | 314 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 315 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
7c1c69bc CLG |
316 | |
317 | /* SPI */ | |
54ecafb7 | 318 | for (i = 0; i < sc->spis_num; i++) { |
5325cc34 | 319 | object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); |
668f62ec | 320 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
dbcabeeb CLG |
321 | return; |
322 | } | |
d783d1fe | 323 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
347df6f8 | 324 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
dbcabeeb CLG |
325 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
326 | s->spi[i].ctrl->flash_window_base); | |
7c1c69bc | 327 | } |
c2da8a8b | 328 | |
bfdd34f1 GR |
329 | /* EHCI */ |
330 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 331 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
bfdd34f1 GR |
332 | return; |
333 | } | |
334 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
347df6f8 | 335 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
bfdd34f1 | 336 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 337 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
bfdd34f1 GR |
338 | } |
339 | ||
c2da8a8b | 340 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 341 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
c2da8a8b CLG |
342 | return; |
343 | } | |
347df6f8 | 344 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); |
013befe1 CLG |
345 | |
346 | /* Watch dog */ | |
54ecafb7 | 347 | for (i = 0; i < sc->wdts_num; i++) { |
6112bd6d CLG |
348 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
349 | ||
5325cc34 MA |
350 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
351 | &error_abort); | |
668f62ec | 352 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f986ee1d JS |
353 | return; |
354 | } | |
355 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
347df6f8 | 356 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); |
013befe1 | 357 | } |
ea337c65 CLG |
358 | |
359 | /* Net */ | |
d3bad7e7 | 360 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 361 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 362 | &error_abort); |
668f62ec | 363 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 364 | return; |
67340990 CLG |
365 | } |
366 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
347df6f8 | 367 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
67340990 | 368 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 369 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
ea337c65 | 370 | } |
118c82e7 EJ |
371 | |
372 | /* XDMA */ | |
668f62ec | 373 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
118c82e7 EJ |
374 | return; |
375 | } | |
376 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
347df6f8 | 377 | sc->memmap[ASPEED_DEV_XDMA]); |
118c82e7 | 378 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 379 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
fdcc7c06 RG |
380 | |
381 | /* GPIO */ | |
668f62ec | 382 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
fdcc7c06 RG |
383 | return; |
384 | } | |
347df6f8 | 385 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
fdcc7c06 | 386 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 387 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
2bea128c EJ |
388 | |
389 | /* SDHCI */ | |
668f62ec | 390 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
2bea128c EJ |
391 | return; |
392 | } | |
393 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
347df6f8 | 394 | sc->memmap[ASPEED_DEV_SDHCI]); |
2bea128c | 395 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 396 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
2ecf1726 CLG |
397 | |
398 | /* LPC */ | |
399 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
400 | return; | |
401 | } | |
402 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
c59f781e AJ |
403 | |
404 | /* Connect the LPC IRQ to the VIC */ | |
2ecf1726 CLG |
405 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
406 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
407 | |
408 | /* | |
409 | * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the | |
410 | * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by | |
411 | * contrast, on the AST2600, the subdevice IRQs are connected straight to | |
412 | * the GIC). | |
413 | * | |
414 | * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output | |
415 | * to the VIC is at offset 0. | |
416 | */ | |
417 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
418 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); | |
419 | ||
420 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
421 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); | |
422 | ||
423 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
424 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); | |
425 | ||
426 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
427 | qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); | |
a3888d75 JS |
428 | |
429 | /* HACE */ | |
430 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
431 | &error_abort); | |
432 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
433 | return; | |
434 | } | |
435 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); | |
436 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
437 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
43e3346e | 438 | } |
ece09bee | 439 | static Property aspeed_soc_properties[] = { |
95b56e17 CLG |
440 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |
441 | MemoryRegion *), | |
5d63d0c7 PD |
442 | DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, |
443 | ASPEED_DEV_UART5), | |
ece09bee CLG |
444 | DEFINE_PROP_END_OF_LIST(), |
445 | }; | |
43e3346e | 446 | |
ff90606f | 447 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) |
43e3346e AJ |
448 | { |
449 | DeviceClass *dc = DEVICE_CLASS(oc); | |
450 | ||
ff90606f | 451 | dc->realize = aspeed_soc_realize; |
469f3da4 TH |
452 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
453 | dc->user_creatable = false; | |
4f67d30b | 454 | device_class_set_props(dc, aspeed_soc_properties); |
43e3346e AJ |
455 | } |
456 | ||
ff90606f | 457 | static const TypeInfo aspeed_soc_type_info = { |
b033271f CLG |
458 | .name = TYPE_ASPEED_SOC, |
459 | .parent = TYPE_DEVICE, | |
b033271f CLG |
460 | .instance_size = sizeof(AspeedSoCState), |
461 | .class_size = sizeof(AspeedSoCClass), | |
54ecafb7 | 462 | .class_init = aspeed_soc_class_init, |
b033271f | 463 | .abstract = true, |
43e3346e AJ |
464 | }; |
465 | ||
54ecafb7 | 466 | static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) |
43e3346e | 467 | { |
54ecafb7 | 468 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
b033271f | 469 | |
54ecafb7 CLG |
470 | sc->name = "ast2400-a1"; |
471 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); | |
472 | sc->silicon_rev = AST2400_A1_SILICON_REV; | |
473 | sc->sram_size = 0x8000; | |
474 | sc->spis_num = 1; | |
bfdd34f1 | 475 | sc->ehcis_num = 1; |
54ecafb7 | 476 | sc->wdts_num = 2; |
d300db02 | 477 | sc->macs_num = 2; |
54ecafb7 CLG |
478 | sc->irqmap = aspeed_soc_ast2400_irqmap; |
479 | sc->memmap = aspeed_soc_ast2400_memmap; | |
480 | sc->num_cpus = 1; | |
481 | } | |
482 | ||
483 | static const TypeInfo aspeed_soc_ast2400_type_info = { | |
484 | .name = "ast2400-a1", | |
485 | .parent = TYPE_ASPEED_SOC, | |
486 | .instance_init = aspeed_soc_init, | |
487 | .instance_size = sizeof(AspeedSoCState), | |
488 | .class_init = aspeed_soc_ast2400_class_init, | |
489 | }; | |
490 | ||
491 | static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) | |
492 | { | |
493 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
494 | ||
495 | sc->name = "ast2500-a1"; | |
496 | sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
497 | sc->silicon_rev = AST2500_A1_SILICON_REV; | |
498 | sc->sram_size = 0x9000; | |
499 | sc->spis_num = 2; | |
bfdd34f1 | 500 | sc->ehcis_num = 2; |
54ecafb7 | 501 | sc->wdts_num = 3; |
d300db02 | 502 | sc->macs_num = 2; |
54ecafb7 CLG |
503 | sc->irqmap = aspeed_soc_ast2500_irqmap; |
504 | sc->memmap = aspeed_soc_ast2500_memmap; | |
505 | sc->num_cpus = 1; | |
43e3346e AJ |
506 | } |
507 | ||
54ecafb7 CLG |
508 | static const TypeInfo aspeed_soc_ast2500_type_info = { |
509 | .name = "ast2500-a1", | |
510 | .parent = TYPE_ASPEED_SOC, | |
511 | .instance_init = aspeed_soc_init, | |
512 | .instance_size = sizeof(AspeedSoCState), | |
513 | .class_init = aspeed_soc_ast2500_class_init, | |
514 | }; | |
515 | static void aspeed_soc_register_types(void) | |
516 | { | |
517 | type_register_static(&aspeed_soc_type_info); | |
518 | type_register_static(&aspeed_soc_ast2400_type_info); | |
519 | type_register_static(&aspeed_soc_ast2500_type_info); | |
520 | }; | |
521 | ||
ff90606f | 522 | type_init(aspeed_soc_register_types) |