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43e3346e AJ |
1 | /* |
2 | * AST2400 SoC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 PB |
15 | #include "qemu-common.h" |
16 | #include "cpu.h" | |
43e3346e AJ |
17 | #include "exec/address-spaces.h" |
18 | #include "hw/arm/ast2400.h" | |
19 | #include "hw/char/serial.h" | |
20 | ||
21 | #define AST2400_UART_5_BASE 0x00184000 | |
22 | #define AST2400_IOMEM_SIZE 0x00200000 | |
23 | #define AST2400_IOMEM_BASE 0x1E600000 | |
24 | #define AST2400_VIC_BASE 0x1E6C0000 | |
25 | #define AST2400_TIMER_BASE 0x1E782000 | |
26 | ||
27 | static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; | |
28 | static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; | |
29 | ||
30 | /* | |
31 | * IO handlers: simply catch any reads/writes to IO addresses that aren't | |
32 | * handled by a device mapping. | |
33 | */ | |
34 | ||
35 | static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size) | |
36 | { | |
37 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | |
38 | __func__, offset, size); | |
39 | return 0; | |
40 | } | |
41 | ||
42 | static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value, | |
43 | unsigned size) | |
44 | { | |
45 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", | |
46 | __func__, offset, value, size); | |
47 | } | |
48 | ||
49 | static const MemoryRegionOps ast2400_io_ops = { | |
50 | .read = ast2400_io_read, | |
51 | .write = ast2400_io_write, | |
52 | .endianness = DEVICE_LITTLE_ENDIAN, | |
53 | }; | |
54 | ||
55 | static void ast2400_init(Object *obj) | |
56 | { | |
57 | AST2400State *s = AST2400(obj); | |
58 | ||
59 | s->cpu = cpu_arm_init("arm926"); | |
60 | ||
61 | object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); | |
62 | object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); | |
63 | qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); | |
64 | ||
65 | object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER); | |
66 | object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL); | |
67 | qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); | |
68 | } | |
69 | ||
70 | static void ast2400_realize(DeviceState *dev, Error **errp) | |
71 | { | |
72 | int i; | |
73 | AST2400State *s = AST2400(dev); | |
74 | Error *err = NULL; | |
75 | ||
76 | /* IO space */ | |
77 | memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL, | |
78 | "ast2400.io", AST2400_IOMEM_SIZE); | |
79 | memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE, | |
80 | &s->iomem, -1); | |
81 | ||
82 | /* VIC */ | |
83 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | |
84 | if (err) { | |
85 | error_propagate(errp, err); | |
86 | return; | |
87 | } | |
88 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE); | |
89 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, | |
90 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); | |
91 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, | |
92 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); | |
93 | ||
94 | /* Timer */ | |
95 | object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | |
96 | if (err) { | |
97 | error_propagate(errp, err); | |
98 | return; | |
99 | } | |
100 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE); | |
101 | for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) { | |
102 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]); | |
103 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
104 | } | |
105 | ||
106 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
107 | if (serial_hds[0]) { | |
108 | qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); | |
109 | serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2, | |
110 | uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN); | |
111 | } | |
112 | } | |
113 | ||
114 | static void ast2400_class_init(ObjectClass *oc, void *data) | |
115 | { | |
116 | DeviceClass *dc = DEVICE_CLASS(oc); | |
117 | ||
118 | dc->realize = ast2400_realize; | |
119 | ||
120 | /* | |
121 | * Reason: creates an ARM CPU, thus use after free(), see | |
122 | * arm_cpu_class_init() | |
123 | */ | |
124 | dc->cannot_destroy_with_object_finalize_yet = true; | |
125 | } | |
126 | ||
127 | static const TypeInfo ast2400_type_info = { | |
128 | .name = TYPE_AST2400, | |
129 | .parent = TYPE_SYS_BUS_DEVICE, | |
130 | .instance_size = sizeof(AST2400State), | |
131 | .instance_init = ast2400_init, | |
132 | .class_init = ast2400_class_init, | |
133 | }; | |
134 | ||
135 | static void ast2400_register_types(void) | |
136 | { | |
137 | type_register_static(&ast2400_type_info); | |
138 | } | |
139 | ||
140 | type_init(ast2400_register_types) |