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43e3346e AJ |
1 | /* |
2 | * AST2400 SoC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * Jeremy Kerr <jk@ozlabs.org> | |
6 | * | |
7 | * Copyright 2016 IBM Corp. | |
8 | * | |
9 | * This code is licensed under the GPL version 2 or later. See | |
10 | * the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #include "qemu/osdep.h" | |
da34e65c | 14 | #include "qapi/error.h" |
43e3346e AJ |
15 | #include "exec/address-spaces.h" |
16 | #include "hw/arm/ast2400.h" | |
17 | #include "hw/char/serial.h" | |
18 | ||
19 | #define AST2400_UART_5_BASE 0x00184000 | |
20 | #define AST2400_IOMEM_SIZE 0x00200000 | |
21 | #define AST2400_IOMEM_BASE 0x1E600000 | |
22 | #define AST2400_VIC_BASE 0x1E6C0000 | |
23 | #define AST2400_TIMER_BASE 0x1E782000 | |
24 | ||
25 | static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; | |
26 | static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, }; | |
27 | ||
28 | /* | |
29 | * IO handlers: simply catch any reads/writes to IO addresses that aren't | |
30 | * handled by a device mapping. | |
31 | */ | |
32 | ||
33 | static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size) | |
34 | { | |
35 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | |
36 | __func__, offset, size); | |
37 | return 0; | |
38 | } | |
39 | ||
40 | static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value, | |
41 | unsigned size) | |
42 | { | |
43 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", | |
44 | __func__, offset, value, size); | |
45 | } | |
46 | ||
47 | static const MemoryRegionOps ast2400_io_ops = { | |
48 | .read = ast2400_io_read, | |
49 | .write = ast2400_io_write, | |
50 | .endianness = DEVICE_LITTLE_ENDIAN, | |
51 | }; | |
52 | ||
53 | static void ast2400_init(Object *obj) | |
54 | { | |
55 | AST2400State *s = AST2400(obj); | |
56 | ||
57 | s->cpu = cpu_arm_init("arm926"); | |
58 | ||
59 | object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); | |
60 | object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); | |
61 | qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); | |
62 | ||
63 | object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER); | |
64 | object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL); | |
65 | qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); | |
66 | } | |
67 | ||
68 | static void ast2400_realize(DeviceState *dev, Error **errp) | |
69 | { | |
70 | int i; | |
71 | AST2400State *s = AST2400(dev); | |
72 | Error *err = NULL; | |
73 | ||
74 | /* IO space */ | |
75 | memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL, | |
76 | "ast2400.io", AST2400_IOMEM_SIZE); | |
77 | memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE, | |
78 | &s->iomem, -1); | |
79 | ||
80 | /* VIC */ | |
81 | object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); | |
82 | if (err) { | |
83 | error_propagate(errp, err); | |
84 | return; | |
85 | } | |
86 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE); | |
87 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0, | |
88 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); | |
89 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1, | |
90 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); | |
91 | ||
92 | /* Timer */ | |
93 | object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); | |
94 | if (err) { | |
95 | error_propagate(errp, err); | |
96 | return; | |
97 | } | |
98 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE); | |
99 | for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) { | |
100 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]); | |
101 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
102 | } | |
103 | ||
104 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
105 | if (serial_hds[0]) { | |
106 | qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); | |
107 | serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2, | |
108 | uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN); | |
109 | } | |
110 | } | |
111 | ||
112 | static void ast2400_class_init(ObjectClass *oc, void *data) | |
113 | { | |
114 | DeviceClass *dc = DEVICE_CLASS(oc); | |
115 | ||
116 | dc->realize = ast2400_realize; | |
117 | ||
118 | /* | |
119 | * Reason: creates an ARM CPU, thus use after free(), see | |
120 | * arm_cpu_class_init() | |
121 | */ | |
122 | dc->cannot_destroy_with_object_finalize_yet = true; | |
123 | } | |
124 | ||
125 | static const TypeInfo ast2400_type_info = { | |
126 | .name = TYPE_AST2400, | |
127 | .parent = TYPE_SYS_BUS_DEVICE, | |
128 | .instance_size = sizeof(AST2400State), | |
129 | .instance_init = ast2400_init, | |
130 | .class_init = ast2400_class_init, | |
131 | }; | |
132 | ||
133 | static void ast2400_register_types(void) | |
134 | { | |
135 | type_register_static(&ast2400_type_info); | |
136 | } | |
137 | ||
138 | type_init(ast2400_register_types) |