[mirror_qemu.git] / hw / arm / bcm2836.c

/*
 * Raspberry Pi emulation (c) 2012 Gregory Estrade
 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
 *
 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
 * Written by Andrew Baumann
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/arm/bcm2836.h"
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"

struct BCM283XClass {
    /*< private >*/
    DeviceClass parent_class;
    /*< public >*/
    const char *name;
    const char *cpu_type;
    unsigned core_count;
    hwaddr peri_base; /* Peripheral base address seen by the CPU */
    hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
    int clusterid;
};

static Property bcm2836_enabled_cores_property =
    DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);

static void bcm2836_init(Object *obj)
{
    BCM283XState *s = BCM283X(obj);
    BCM283XClass *bc = BCM283X_GET_CLASS(obj);
    int n;

    for (n = 0; n < bc->core_count; n++) {
        object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
                                bc->cpu_type);
    }
    if (bc->core_count > 1) {
        qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
        qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
    }

    if (bc->ctrl_base) {
        object_initialize_child(obj, "control", &s->control,
                                TYPE_BCM2836_CONTROL);
    }

    object_initialize_child(obj, "peripherals", &s->peripherals,
                            TYPE_BCM2835_PERIPHERALS);
    object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
                              "board-rev");
    object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals),
                              "command-line");
    object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
                              "vcram-size");
}

static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
{
    BCM283XState *s = BCM283X(dev);
    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
    Object *obj;

    /* common peripherals from bcm2835 */

    obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);

    object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
        return false;
    }

    object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
                              "sd-bus");

    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
                            bc->peri_base, 1);
    return true;
}

static void bcm2835_realize(DeviceState *dev, Error **errp)
{
    BCM283XState *s = BCM283X(dev);

    if (!bcm283x_common_realize(dev, errp)) {
        return;
    }

    if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
        return;
    }

    /* Connect irq/fiq outputs from the interrupt controller. */
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
            qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
            qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
}

static void bcm2836_realize(DeviceState *dev, Error **errp)
{
    BCM283XState *s = BCM283X(dev);
    BCM283XClass *bc = BCM283X_GET_CLASS(dev);
    int n;

    if (!bcm283x_common_realize(dev, errp)) {
        return;
    }

    /* bcm2836 interrupt controller (and mailboxes, etc.) */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
        qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
        qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));

    for (n = 0; n < BCM283X_NCPUS; n++) {
        /* TODO: this should be converted to a property of ARM_CPU */
        s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;

        /* set periphbase/CBAR value for CPU-local registers */
        if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
                                     bc->peri_base, errp)) {
            return;
        }

        /* start powered off if not enabled */
        if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
                                      "start-powered-off",
                                      n >= s->enabled_cpus,
                                      errp)) {
            return;
        }

        if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
            return;
        }

        /* Connect irq/fiq outputs from the interrupt controller. */
        qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
                qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
        qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
                qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));

        /* Connect timers from the CPU to the interrupt controller */
        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
                qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
                qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
    }
}

static void bcm283x_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    /* Reason: Must be wired up in code (see raspi_init() function) */
    dc->user_creatable = false;
}

static void bcm2835_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    BCM283XClass *bc = BCM283X_CLASS(oc);

    bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
    bc->core_count = 1;
    bc->peri_base = 0x20000000;
    dc->realize = bcm2835_realize;
};

static void bcm2836_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    BCM283XClass *bc = BCM283X_CLASS(oc);

    bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
    bc->core_count = BCM283X_NCPUS;
    bc->peri_base = 0x3f000000;
    bc->ctrl_base = 0x40000000;
    bc->clusterid = 0xf;
    dc->realize = bcm2836_realize;
};

#ifdef TARGET_AARCH64
static void bcm2837_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    BCM283XClass *bc = BCM283X_CLASS(oc);

    bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
    bc->core_count = BCM283X_NCPUS;
    bc->peri_base = 0x3f000000;
    bc->ctrl_base = 0x40000000;
    bc->clusterid = 0x0;
    dc->realize = bcm2836_realize;
};
#endif

static const TypeInfo bcm283x_types[] = {
    {
        .name           = TYPE_BCM2835,
        .parent         = TYPE_BCM283X,
        .class_init     = bcm2835_class_init,
    }, {
        .name           = TYPE_BCM2836,
        .parent         = TYPE_BCM283X,
        .class_init     = bcm2836_class_init,
#ifdef TARGET_AARCH64
    }, {
        .name           = TYPE_BCM2837,
        .parent         = TYPE_BCM283X,
        .class_init     = bcm2837_class_init,
#endif
    }, {
        .name           = TYPE_BCM283X,
        .parent         = TYPE_DEVICE,
        .instance_size  = sizeof(BCM283XState),
        .instance_init  = bcm2836_init,
        .class_size     = sizeof(BCM283XClass),
        .class_init     = bcm283x_class_init,
        .abstract       = true,
    }
};

DEFINE_TYPES(bcm283x_types)
Commit	Line	Data
bad56236 AB	1	/*
	2	* Raspberry Pi emulation (c) 2012 Gregory Estrade
	3	* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
	4	*
	5	* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
	6	* Written by Andrew Baumann
	7	*
6111a0c0 PMD	8	* This work is licensed under the terms of the GNU GPL, version 2 or later.
6111a0c0 PMD	9	* See the COPYING file in the top-level directory.
bad56236 AB	10	*/
bad56236 AB	11
c964b660	12	#include "qemu/osdep.h"
da34e65c	13	#include "qapi/error.h"
0b8fa32f	14	#include "qemu/module.h"
bad56236 AB	15	#include "hw/arm/bcm2836.h"
	16	#include "hw/arm/raspi_platform.h"
	17	#include "hw/sysbus.h"
bad56236	18
a91179e7	19	struct BCM283XClass {
58b35028 PMD	20	/< private >/
	21	DeviceClass parent_class;
	22	/< public >/
0fd74f03	23	const char *name;
210f4784	24	const char *cpu_type;
25ea2884	25	unsigned core_count;
d0567e94 PMD	26	hwaddr peri_base; /* Peripheral base address seen by the CPU */
d0567e94 PMD	27	hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
1bcb4d16	28	int clusterid;
a91179e7	29	};
58b35028	30
96c741d7 PMD	31	static Property bcm2836_enabled_cores_property =
	32	DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
	33
bad56236 AB	34	static void bcm2836_init(Object *obj)
bad56236 AB	35	{
926dcdf0	36	BCM283XState *s = BCM283X(obj);
210f4784	37	BCM283XClass *bc = BCM283X_GET_CLASS(obj);
210f4784 PM	38	int n;
210f4784 PM	39
25ea2884	40	for (n = 0; n < bc->core_count; n++) {
5e5e9ed6	41	object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
34d1a4f5	42	bc->cpu_type);
210f4784	43	}
96c741d7 PMD	44	if (bc->core_count > 1) {
	45	qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
	46	qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
	47	}
bad56236	48
f5600924 PMD	49	if (bc->ctrl_base) {
	50	object_initialize_child(obj, "control", &s->control,
	51	TYPE_BCM2836_CONTROL);
	52	}
bad56236	53
db873cc5 MA	54	object_initialize_child(obj, "peripherals", &s->peripherals,
db873cc5 MA	55	TYPE_BCM2835_PERIPHERALS);
f0afa731	56	object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
d2623129	57	"board-rev");
f802ff1e DB	58	object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals),
f802ff1e DB	59	"command-line");
5e9c2a8d	60	object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
d2623129	61	"vcram-size");
bad56236 AB	62	}
bad56236 AB	63
f5600924	64	static bool bcm283x_common_realize(DeviceState dev, Error *errp)
bad56236	65	{
926dcdf0	66	BCM283XState *s = BCM283X(dev);
1bcb4d16	67	BCM283XClass *bc = BCM283X_GET_CLASS(dev);
bad56236	68	Object *obj;
bad56236 AB	69
	70	/* common peripherals from bcm2835 */
	71
4d21fcd5	72	obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
bad56236	73
d2623129	74	object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
bad56236	75
668f62ec	76	if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
f5600924	77	return false;
bad56236 AB	78	}
bad56236 AB	79
a55b53a2	80	object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
d2623129	81	"sd-bus");
a55b53a2	82
bad56236	83	sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
34d1a4f5	84	bc->peri_base, 1);
f5600924 PMD	85	return true;
	86	}
	87
df6cf08d PMD	88	static void bcm2835_realize(DeviceState dev, Error *errp)
	89	{
	90	BCM283XState *s = BCM283X(dev);
	91
	92	if (!bcm283x_common_realize(dev, errp)) {
	93	return;
	94	}
	95
	96	if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
	97	return;
	98	}
	99
	100	/* Connect irq/fiq outputs from the interrupt controller. */
	101	sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
	102	qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
	103	sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
	104	qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
	105	}
	106
f5600924 PMD	107	static void bcm2836_realize(DeviceState dev, Error *errp)
	108	{
	109	BCM283XState *s = BCM283X(dev);
	110	BCM283XClass *bc = BCM283X_GET_CLASS(dev);
	111	int n;
	112
	113	if (!bcm283x_common_realize(dev, errp)) {
	114	return;
	115	}
bad56236 AB	116
bad56236 AB	117	/* bcm2836 interrupt controller (and mailboxes, etc.) */
668f62ec	118	if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
bad56236 AB	119	return;
	120	}
	121
34d1a4f5	122	sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
bad56236 AB	123
	124	sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
	125	qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
	126	sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
	127	qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
	128
926dcdf0	129	for (n = 0; n < BCM283X_NCPUS; n++) {
1bcb4d16	130	/* TODO: this should be converted to a property of ARM_CPU */
34d1a4f5	131	s->cpu[n].core.mp_affinity = (bc->clusterid << 8) \| n;
bad56236 AB	132
bad56236 AB	133	/* set periphbase/CBAR value for CPU-local registers */
778a2dc5	134	if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
34d1a4f5	135	bc->peri_base, errp)) {
bad56236 AB	136	return;
	137	}
	138
	139	/* start powered off if not enabled */
778a2dc5 MA	140	if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
	141	"start-powered-off",
	142	n >= s->enabled_cpus,
668f62ec	143	errp)) {
bad56236 AB	144	return;
	145	}
	146
668f62ec	147	if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
bad56236 AB	148	return;
	149	}
	150
	151	/* Connect irq/fiq outputs from the interrupt controller. */
	152	qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
5e5e9ed6	153	qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
bad56236	154	qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
5e5e9ed6	155	qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));
bad56236 AB	156
bad56236 AB	157	/* Connect timers from the CPU to the interrupt controller */
5e5e9ed6	158	qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
0dc19823	159	qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
5e5e9ed6	160	qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
bad56236	161	qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
5e5e9ed6	162	qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
0dc19823	163	qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
5e5e9ed6	164	qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
0dc19823	165	qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
bad56236 AB	166	}
	167	}
	168
0fd74f03	169	static void bcm283x_class_init(ObjectClass oc, void data)
bad56236 AB	170	{
	171	DeviceClass *dc = DEVICE_CLASS(oc);
	172
cccf96c3 TH	173	/* Reason: Must be wired up in code (see raspi_init() function) */
cccf96c3 TH	174	dc->user_creatable = false;
bad56236 AB	175	}
bad56236 AB	176
df6cf08d PMD	177	static void bcm2835_class_init(ObjectClass oc, void data)
	178	{
	179	DeviceClass *dc = DEVICE_CLASS(oc);
	180	BCM283XClass *bc = BCM283X_CLASS(oc);
	181
	182	bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
	183	bc->core_count = 1;
	184	bc->peri_base = 0x20000000;
	185	dc->realize = bcm2835_realize;
	186	};
	187
34d1a4f5 PMD	188	static void bcm2836_class_init(ObjectClass oc, void data)
	189	{
	190	DeviceClass *dc = DEVICE_CLASS(oc);
	191	BCM283XClass *bc = BCM283X_CLASS(oc);
	192
	193	bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
25ea2884	194	bc->core_count = BCM283X_NCPUS;
34d1a4f5 PMD	195	bc->peri_base = 0x3f000000;
	196	bc->ctrl_base = 0x40000000;
	197	bc->clusterid = 0xf;
	198	dc->realize = bcm2836_realize;
bad56236 AB	199	};
bad56236 AB	200
34d1a4f5 PMD	201	#ifdef TARGET_AARCH64
34d1a4f5 PMD	202	static void bcm2837_class_init(ObjectClass oc, void data)
bad56236	203	{
34d1a4f5 PMD	204	DeviceClass *dc = DEVICE_CLASS(oc);
	205	BCM283XClass *bc = BCM283X_CLASS(oc);
	206
	207	bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
25ea2884	208	bc->core_count = BCM283X_NCPUS;
34d1a4f5 PMD	209	bc->peri_base = 0x3f000000;
	210	bc->ctrl_base = 0x40000000;
	211	bc->clusterid = 0x0;
	212	dc->realize = bcm2836_realize;
34d1a4f5 PMD	213	};
	214	#endif
	215
	216	static const TypeInfo bcm283x_types[] = {
	217	{
df6cf08d PMD	218	.name = TYPE_BCM2835,
	219	.parent = TYPE_BCM283X,
	220	.class_init = bcm2835_class_init,
	221	}, {
34d1a4f5 PMD	222	.name = TYPE_BCM2836,
	223	.parent = TYPE_BCM283X,
	224	.class_init = bcm2836_class_init,
	225	#ifdef TARGET_AARCH64
	226	}, {
	227	.name = TYPE_BCM2837,
	228	.parent = TYPE_BCM283X,
	229	.class_init = bcm2837_class_init,
	230	#endif
	231	}, {
	232	.name = TYPE_BCM283X,
	233	.parent = TYPE_DEVICE,
	234	.instance_size = sizeof(BCM283XState),
	235	.instance_init = bcm2836_init,
	236	.class_size = sizeof(BCM283XClass),
	237	.class_init = bcm283x_class_init,
	238	.abstract = true,
0fd74f03	239	}
34d1a4f5	240	};
bad56236	241
34d1a4f5	242	DEFINE_TYPES(bcm283x_types)