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bad56236 AB |
1 | /* |
2 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | |
3 | * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous | |
4 | * | |
5 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | |
6 | * Written by Andrew Baumann | |
7 | * | |
6111a0c0 PMD |
8 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
9 | * See the COPYING file in the top-level directory. | |
bad56236 AB |
10 | */ |
11 | ||
c964b660 | 12 | #include "qemu/osdep.h" |
da34e65c | 13 | #include "qapi/error.h" |
0b8fa32f | 14 | #include "qemu/module.h" |
bad56236 AB |
15 | #include "hw/arm/bcm2836.h" |
16 | #include "hw/arm/raspi_platform.h" | |
17 | #include "hw/sysbus.h" | |
bad56236 | 18 | |
58b35028 PMD |
19 | typedef struct BCM283XClass { |
20 | /*< private >*/ | |
21 | DeviceClass parent_class; | |
22 | /*< public >*/ | |
0fd74f03 | 23 | const char *name; |
210f4784 | 24 | const char *cpu_type; |
25ea2884 | 25 | unsigned core_count; |
d0567e94 PMD |
26 | hwaddr peri_base; /* Peripheral base address seen by the CPU */ |
27 | hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ | |
1bcb4d16 | 28 | int clusterid; |
34d1a4f5 | 29 | } BCM283XClass; |
0fd74f03 | 30 | |
58b35028 PMD |
31 | #define BCM283X_CLASS(klass) \ |
32 | OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) | |
33 | #define BCM283X_GET_CLASS(obj) \ | |
34 | OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) | |
35 | ||
96c741d7 PMD |
36 | static Property bcm2836_enabled_cores_property = |
37 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); | |
38 | ||
bad56236 AB |
39 | static void bcm2836_init(Object *obj) |
40 | { | |
926dcdf0 | 41 | BCM283XState *s = BCM283X(obj); |
210f4784 | 42 | BCM283XClass *bc = BCM283X_GET_CLASS(obj); |
210f4784 PM |
43 | int n; |
44 | ||
25ea2884 | 45 | for (n = 0; n < bc->core_count; n++) { |
5e5e9ed6 | 46 | object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, |
34d1a4f5 | 47 | bc->cpu_type); |
210f4784 | 48 | } |
96c741d7 PMD |
49 | if (bc->core_count > 1) { |
50 | qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); | |
51 | qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); | |
52 | } | |
bad56236 | 53 | |
f5600924 PMD |
54 | if (bc->ctrl_base) { |
55 | object_initialize_child(obj, "control", &s->control, | |
56 | TYPE_BCM2836_CONTROL); | |
57 | } | |
bad56236 | 58 | |
db873cc5 MA |
59 | object_initialize_child(obj, "peripherals", &s->peripherals, |
60 | TYPE_BCM2835_PERIPHERALS); | |
f0afa731 | 61 | object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), |
d2623129 | 62 | "board-rev"); |
5e9c2a8d | 63 | object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), |
d2623129 | 64 | "vcram-size"); |
bad56236 AB |
65 | } |
66 | ||
f5600924 | 67 | static bool bcm283x_common_realize(DeviceState *dev, Error **errp) |
bad56236 | 68 | { |
926dcdf0 | 69 | BCM283XState *s = BCM283X(dev); |
1bcb4d16 | 70 | BCM283XClass *bc = BCM283X_GET_CLASS(dev); |
bad56236 | 71 | Object *obj; |
bad56236 AB |
72 | |
73 | /* common peripherals from bcm2835 */ | |
74 | ||
4d21fcd5 | 75 | obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); |
bad56236 | 76 | |
d2623129 | 77 | object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); |
bad56236 | 78 | |
668f62ec | 79 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { |
f5600924 | 80 | return false; |
bad56236 AB |
81 | } |
82 | ||
a55b53a2 | 83 | object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), |
d2623129 | 84 | "sd-bus"); |
a55b53a2 | 85 | |
bad56236 | 86 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, |
34d1a4f5 | 87 | bc->peri_base, 1); |
f5600924 PMD |
88 | return true; |
89 | } | |
90 | ||
df6cf08d PMD |
91 | static void bcm2835_realize(DeviceState *dev, Error **errp) |
92 | { | |
93 | BCM283XState *s = BCM283X(dev); | |
94 | ||
95 | if (!bcm283x_common_realize(dev, errp)) { | |
96 | return; | |
97 | } | |
98 | ||
99 | if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) { | |
100 | return; | |
101 | } | |
102 | ||
103 | /* Connect irq/fiq outputs from the interrupt controller. */ | |
104 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, | |
105 | qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); | |
106 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | |
107 | qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); | |
108 | } | |
109 | ||
f5600924 PMD |
110 | static void bcm2836_realize(DeviceState *dev, Error **errp) |
111 | { | |
112 | BCM283XState *s = BCM283X(dev); | |
113 | BCM283XClass *bc = BCM283X_GET_CLASS(dev); | |
114 | int n; | |
115 | ||
116 | if (!bcm283x_common_realize(dev, errp)) { | |
117 | return; | |
118 | } | |
bad56236 AB |
119 | |
120 | /* bcm2836 interrupt controller (and mailboxes, etc.) */ | |
668f62ec | 121 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { |
bad56236 AB |
122 | return; |
123 | } | |
124 | ||
34d1a4f5 | 125 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); |
bad56236 AB |
126 | |
127 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, | |
128 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); | |
129 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | |
130 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | |
131 | ||
926dcdf0 | 132 | for (n = 0; n < BCM283X_NCPUS; n++) { |
1bcb4d16 | 133 | /* TODO: this should be converted to a property of ARM_CPU */ |
34d1a4f5 | 134 | s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; |
bad56236 AB |
135 | |
136 | /* set periphbase/CBAR value for CPU-local registers */ | |
778a2dc5 | 137 | if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", |
34d1a4f5 | 138 | bc->peri_base, errp)) { |
bad56236 AB |
139 | return; |
140 | } | |
141 | ||
142 | /* start powered off if not enabled */ | |
778a2dc5 MA |
143 | if (!object_property_set_bool(OBJECT(&s->cpu[n].core), |
144 | "start-powered-off", | |
145 | n >= s->enabled_cpus, | |
668f62ec | 146 | errp)) { |
bad56236 AB |
147 | return; |
148 | } | |
149 | ||
668f62ec | 150 | if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { |
bad56236 AB |
151 | return; |
152 | } | |
153 | ||
154 | /* Connect irq/fiq outputs from the interrupt controller. */ | |
155 | qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, | |
5e5e9ed6 | 156 | qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); |
bad56236 | 157 | qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, |
5e5e9ed6 | 158 | qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); |
bad56236 AB |
159 | |
160 | /* Connect timers from the CPU to the interrupt controller */ | |
5e5e9ed6 | 161 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, |
0dc19823 | 162 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); |
5e5e9ed6 | 163 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, |
bad56236 | 164 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); |
5e5e9ed6 | 165 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, |
0dc19823 | 166 | qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); |
5e5e9ed6 | 167 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, |
0dc19823 | 168 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); |
bad56236 AB |
169 | } |
170 | } | |
171 | ||
0fd74f03 | 172 | static void bcm283x_class_init(ObjectClass *oc, void *data) |
bad56236 AB |
173 | { |
174 | DeviceClass *dc = DEVICE_CLASS(oc); | |
175 | ||
cccf96c3 TH |
176 | /* Reason: Must be wired up in code (see raspi_init() function) */ |
177 | dc->user_creatable = false; | |
bad56236 AB |
178 | } |
179 | ||
df6cf08d PMD |
180 | static void bcm2835_class_init(ObjectClass *oc, void *data) |
181 | { | |
182 | DeviceClass *dc = DEVICE_CLASS(oc); | |
183 | BCM283XClass *bc = BCM283X_CLASS(oc); | |
184 | ||
185 | bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
186 | bc->core_count = 1; | |
187 | bc->peri_base = 0x20000000; | |
188 | dc->realize = bcm2835_realize; | |
189 | }; | |
190 | ||
34d1a4f5 PMD |
191 | static void bcm2836_class_init(ObjectClass *oc, void *data) |
192 | { | |
193 | DeviceClass *dc = DEVICE_CLASS(oc); | |
194 | BCM283XClass *bc = BCM283X_CLASS(oc); | |
195 | ||
196 | bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); | |
25ea2884 | 197 | bc->core_count = BCM283X_NCPUS; |
34d1a4f5 PMD |
198 | bc->peri_base = 0x3f000000; |
199 | bc->ctrl_base = 0x40000000; | |
200 | bc->clusterid = 0xf; | |
201 | dc->realize = bcm2836_realize; | |
bad56236 AB |
202 | }; |
203 | ||
34d1a4f5 PMD |
204 | #ifdef TARGET_AARCH64 |
205 | static void bcm2837_class_init(ObjectClass *oc, void *data) | |
bad56236 | 206 | { |
34d1a4f5 PMD |
207 | DeviceClass *dc = DEVICE_CLASS(oc); |
208 | BCM283XClass *bc = BCM283X_CLASS(oc); | |
209 | ||
210 | bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); | |
25ea2884 | 211 | bc->core_count = BCM283X_NCPUS; |
34d1a4f5 PMD |
212 | bc->peri_base = 0x3f000000; |
213 | bc->ctrl_base = 0x40000000; | |
214 | bc->clusterid = 0x0; | |
215 | dc->realize = bcm2836_realize; | |
34d1a4f5 PMD |
216 | }; |
217 | #endif | |
218 | ||
219 | static const TypeInfo bcm283x_types[] = { | |
220 | { | |
df6cf08d PMD |
221 | .name = TYPE_BCM2835, |
222 | .parent = TYPE_BCM283X, | |
223 | .class_init = bcm2835_class_init, | |
224 | }, { | |
34d1a4f5 PMD |
225 | .name = TYPE_BCM2836, |
226 | .parent = TYPE_BCM283X, | |
227 | .class_init = bcm2836_class_init, | |
228 | #ifdef TARGET_AARCH64 | |
229 | }, { | |
230 | .name = TYPE_BCM2837, | |
231 | .parent = TYPE_BCM283X, | |
232 | .class_init = bcm2837_class_init, | |
233 | #endif | |
234 | }, { | |
235 | .name = TYPE_BCM283X, | |
236 | .parent = TYPE_DEVICE, | |
237 | .instance_size = sizeof(BCM283XState), | |
238 | .instance_init = bcm2836_init, | |
239 | .class_size = sizeof(BCM283XClass), | |
240 | .class_init = bcm283x_class_init, | |
241 | .abstract = true, | |
0fd74f03 | 242 | } |
34d1a4f5 | 243 | }; |
bad56236 | 244 | |
34d1a4f5 | 245 | DEFINE_TYPES(bcm283x_types) |