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bad56236 AB |
1 | /* |
2 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | |
3 | * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous | |
4 | * | |
5 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | |
6 | * Written by Andrew Baumann | |
7 | * | |
6111a0c0 PMD |
8 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
9 | * See the COPYING file in the top-level directory. | |
bad56236 AB |
10 | */ |
11 | ||
c964b660 | 12 | #include "qemu/osdep.h" |
da34e65c | 13 | #include "qapi/error.h" |
0b8fa32f | 14 | #include "qemu/module.h" |
bad56236 AB |
15 | #include "hw/arm/bcm2836.h" |
16 | #include "hw/arm/raspi_platform.h" | |
17 | #include "hw/sysbus.h" | |
d780d056 | 18 | #include "target/arm/cpu-qom.h" |
f4f318b4 | 19 | #include "target/arm/gtimer.h" |
bad56236 | 20 | |
a91179e7 | 21 | struct BCM283XClass { |
58b35028 PMD |
22 | /*< private >*/ |
23 | DeviceClass parent_class; | |
24 | /*< public >*/ | |
0fd74f03 | 25 | const char *name; |
210f4784 | 26 | const char *cpu_type; |
25ea2884 | 27 | unsigned core_count; |
d0567e94 PMD |
28 | hwaddr peri_base; /* Peripheral base address seen by the CPU */ |
29 | hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ | |
1bcb4d16 | 30 | int clusterid; |
a91179e7 | 31 | }; |
58b35028 | 32 | |
96c741d7 PMD |
33 | static Property bcm2836_enabled_cores_property = |
34 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); | |
35 | ||
bad56236 AB |
36 | static void bcm2836_init(Object *obj) |
37 | { | |
926dcdf0 | 38 | BCM283XState *s = BCM283X(obj); |
210f4784 | 39 | BCM283XClass *bc = BCM283X_GET_CLASS(obj); |
210f4784 PM |
40 | int n; |
41 | ||
25ea2884 | 42 | for (n = 0; n < bc->core_count; n++) { |
5e5e9ed6 | 43 | object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, |
34d1a4f5 | 44 | bc->cpu_type); |
210f4784 | 45 | } |
96c741d7 PMD |
46 | if (bc->core_count > 1) { |
47 | qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); | |
48 | qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); | |
49 | } | |
bad56236 | 50 | |
f5600924 PMD |
51 | if (bc->ctrl_base) { |
52 | object_initialize_child(obj, "control", &s->control, | |
53 | TYPE_BCM2836_CONTROL); | |
54 | } | |
bad56236 | 55 | |
db873cc5 MA |
56 | object_initialize_child(obj, "peripherals", &s->peripherals, |
57 | TYPE_BCM2835_PERIPHERALS); | |
f0afa731 | 58 | object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), |
d2623129 | 59 | "board-rev"); |
f802ff1e DB |
60 | object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), |
61 | "command-line"); | |
5e9c2a8d | 62 | object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), |
d2623129 | 63 | "vcram-size"); |
bad56236 AB |
64 | } |
65 | ||
f5600924 | 66 | static bool bcm283x_common_realize(DeviceState *dev, Error **errp) |
bad56236 | 67 | { |
926dcdf0 | 68 | BCM283XState *s = BCM283X(dev); |
1bcb4d16 | 69 | BCM283XClass *bc = BCM283X_GET_CLASS(dev); |
bad56236 | 70 | Object *obj; |
bad56236 AB |
71 | |
72 | /* common peripherals from bcm2835 */ | |
73 | ||
4d21fcd5 | 74 | obj = object_property_get_link(OBJECT(dev), "ram", &error_abort); |
bad56236 | 75 | |
d2623129 | 76 | object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); |
bad56236 | 77 | |
668f62ec | 78 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { |
f5600924 | 79 | return false; |
bad56236 AB |
80 | } |
81 | ||
a55b53a2 | 82 | object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), |
d2623129 | 83 | "sd-bus"); |
a55b53a2 | 84 | |
bad56236 | 85 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, |
34d1a4f5 | 86 | bc->peri_base, 1); |
f5600924 PMD |
87 | return true; |
88 | } | |
89 | ||
df6cf08d PMD |
90 | static void bcm2835_realize(DeviceState *dev, Error **errp) |
91 | { | |
92 | BCM283XState *s = BCM283X(dev); | |
93 | ||
94 | if (!bcm283x_common_realize(dev, errp)) { | |
95 | return; | |
96 | } | |
97 | ||
98 | if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) { | |
99 | return; | |
100 | } | |
101 | ||
102 | /* Connect irq/fiq outputs from the interrupt controller. */ | |
103 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, | |
104 | qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); | |
105 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | |
106 | qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); | |
107 | } | |
108 | ||
f5600924 PMD |
109 | static void bcm2836_realize(DeviceState *dev, Error **errp) |
110 | { | |
111 | BCM283XState *s = BCM283X(dev); | |
112 | BCM283XClass *bc = BCM283X_GET_CLASS(dev); | |
113 | int n; | |
114 | ||
115 | if (!bcm283x_common_realize(dev, errp)) { | |
116 | return; | |
117 | } | |
bad56236 AB |
118 | |
119 | /* bcm2836 interrupt controller (and mailboxes, etc.) */ | |
668f62ec | 120 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { |
bad56236 AB |
121 | return; |
122 | } | |
123 | ||
34d1a4f5 | 124 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); |
bad56236 AB |
125 | |
126 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, | |
127 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); | |
128 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | |
129 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | |
130 | ||
926dcdf0 | 131 | for (n = 0; n < BCM283X_NCPUS; n++) { |
79f51695 PMD |
132 | object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", |
133 | (bc->clusterid << 8) | n, &error_abort); | |
bad56236 AB |
134 | |
135 | /* set periphbase/CBAR value for CPU-local registers */ | |
ca1d323c PMD |
136 | object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", |
137 | bc->peri_base, &error_abort); | |
bad56236 AB |
138 | |
139 | /* start powered off if not enabled */ | |
287fa323 PMD |
140 | object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", |
141 | n >= s->enabled_cpus, &error_abort); | |
bad56236 | 142 | |
668f62ec | 143 | if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { |
bad56236 AB |
144 | return; |
145 | } | |
146 | ||
147 | /* Connect irq/fiq outputs from the interrupt controller. */ | |
148 | qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, | |
5e5e9ed6 | 149 | qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); |
bad56236 | 150 | qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, |
5e5e9ed6 | 151 | qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); |
bad56236 AB |
152 | |
153 | /* Connect timers from the CPU to the interrupt controller */ | |
5e5e9ed6 | 154 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, |
0dc19823 | 155 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); |
5e5e9ed6 | 156 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, |
bad56236 | 157 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); |
5e5e9ed6 | 158 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, |
0dc19823 | 159 | qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); |
5e5e9ed6 | 160 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, |
0dc19823 | 161 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); |
bad56236 AB |
162 | } |
163 | } | |
164 | ||
0fd74f03 | 165 | static void bcm283x_class_init(ObjectClass *oc, void *data) |
bad56236 AB |
166 | { |
167 | DeviceClass *dc = DEVICE_CLASS(oc); | |
168 | ||
cccf96c3 TH |
169 | /* Reason: Must be wired up in code (see raspi_init() function) */ |
170 | dc->user_creatable = false; | |
bad56236 AB |
171 | } |
172 | ||
df6cf08d PMD |
173 | static void bcm2835_class_init(ObjectClass *oc, void *data) |
174 | { | |
175 | DeviceClass *dc = DEVICE_CLASS(oc); | |
176 | BCM283XClass *bc = BCM283X_CLASS(oc); | |
177 | ||
178 | bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); | |
179 | bc->core_count = 1; | |
180 | bc->peri_base = 0x20000000; | |
181 | dc->realize = bcm2835_realize; | |
182 | }; | |
183 | ||
34d1a4f5 PMD |
184 | static void bcm2836_class_init(ObjectClass *oc, void *data) |
185 | { | |
186 | DeviceClass *dc = DEVICE_CLASS(oc); | |
187 | BCM283XClass *bc = BCM283X_CLASS(oc); | |
188 | ||
189 | bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); | |
25ea2884 | 190 | bc->core_count = BCM283X_NCPUS; |
34d1a4f5 PMD |
191 | bc->peri_base = 0x3f000000; |
192 | bc->ctrl_base = 0x40000000; | |
193 | bc->clusterid = 0xf; | |
194 | dc->realize = bcm2836_realize; | |
bad56236 AB |
195 | }; |
196 | ||
34d1a4f5 PMD |
197 | #ifdef TARGET_AARCH64 |
198 | static void bcm2837_class_init(ObjectClass *oc, void *data) | |
bad56236 | 199 | { |
34d1a4f5 PMD |
200 | DeviceClass *dc = DEVICE_CLASS(oc); |
201 | BCM283XClass *bc = BCM283X_CLASS(oc); | |
202 | ||
203 | bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); | |
25ea2884 | 204 | bc->core_count = BCM283X_NCPUS; |
34d1a4f5 PMD |
205 | bc->peri_base = 0x3f000000; |
206 | bc->ctrl_base = 0x40000000; | |
207 | bc->clusterid = 0x0; | |
208 | dc->realize = bcm2836_realize; | |
34d1a4f5 PMD |
209 | }; |
210 | #endif | |
211 | ||
212 | static const TypeInfo bcm283x_types[] = { | |
213 | { | |
df6cf08d PMD |
214 | .name = TYPE_BCM2835, |
215 | .parent = TYPE_BCM283X, | |
216 | .class_init = bcm2835_class_init, | |
217 | }, { | |
34d1a4f5 PMD |
218 | .name = TYPE_BCM2836, |
219 | .parent = TYPE_BCM283X, | |
220 | .class_init = bcm2836_class_init, | |
221 | #ifdef TARGET_AARCH64 | |
222 | }, { | |
223 | .name = TYPE_BCM2837, | |
224 | .parent = TYPE_BCM283X, | |
225 | .class_init = bcm2837_class_init, | |
226 | #endif | |
227 | }, { | |
228 | .name = TYPE_BCM283X, | |
229 | .parent = TYPE_DEVICE, | |
230 | .instance_size = sizeof(BCM283XState), | |
231 | .instance_init = bcm2836_init, | |
232 | .class_size = sizeof(BCM283XClass), | |
233 | .class_init = bcm283x_class_init, | |
234 | .abstract = true, | |
0fd74f03 | 235 | } |
34d1a4f5 | 236 | }; |
bad56236 | 237 | |
34d1a4f5 | 238 | DEFINE_TYPES(bcm283x_types) |