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bad56236 AB |
1 | /* |
2 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | |
3 | * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous | |
4 | * | |
5 | * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft | |
6 | * Written by Andrew Baumann | |
7 | * | |
8 | * This code is licensed under the GNU GPLv2 and later. | |
9 | */ | |
10 | ||
c964b660 | 11 | #include "qemu/osdep.h" |
da34e65c | 12 | #include "qapi/error.h" |
0b8fa32f | 13 | #include "qemu/module.h" |
4771d756 | 14 | #include "cpu.h" |
bad56236 AB |
15 | #include "hw/arm/bcm2836.h" |
16 | #include "hw/arm/raspi_platform.h" | |
17 | #include "hw/sysbus.h" | |
bad56236 | 18 | |
0fd74f03 PM |
19 | struct BCM283XInfo { |
20 | const char *name; | |
210f4784 | 21 | const char *cpu_type; |
d0567e94 PMD |
22 | hwaddr peri_base; /* Peripheral base address seen by the CPU */ |
23 | hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ | |
1bcb4d16 | 24 | int clusterid; |
0fd74f03 PM |
25 | }; |
26 | ||
27 | static const BCM283XInfo bcm283x_socs[] = { | |
28 | { | |
29 | .name = TYPE_BCM2836, | |
2b0b9321 | 30 | .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"), |
d0567e94 PMD |
31 | .peri_base = 0x3f000000, |
32 | .ctrl_base = 0x40000000, | |
1bcb4d16 | 33 | .clusterid = 0xf, |
0fd74f03 | 34 | }, |
210f4784 | 35 | #ifdef TARGET_AARCH64 |
0fd74f03 PM |
36 | { |
37 | .name = TYPE_BCM2837, | |
210f4784 | 38 | .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), |
d0567e94 PMD |
39 | .peri_base = 0x3f000000, |
40 | .ctrl_base = 0x40000000, | |
1bcb4d16 | 41 | .clusterid = 0x0, |
0fd74f03 | 42 | }, |
210f4784 | 43 | #endif |
0fd74f03 PM |
44 | }; |
45 | ||
bad56236 AB |
46 | static void bcm2836_init(Object *obj) |
47 | { | |
926dcdf0 | 48 | BCM283XState *s = BCM283X(obj); |
210f4784 PM |
49 | BCM283XClass *bc = BCM283X_GET_CLASS(obj); |
50 | const BCM283XInfo *info = bc->info; | |
51 | int n; | |
52 | ||
53 | for (n = 0; n < BCM283X_NCPUS; n++) { | |
5e5e9ed6 PMD |
54 | object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, |
55 | sizeof(s->cpu[n].core), info->cpu_type, | |
56 | &error_abort, NULL); | |
210f4784 | 57 | } |
bad56236 | 58 | |
14c520e3 TH |
59 | sysbus_init_child_obj(obj, "control", &s->control, sizeof(s->control), |
60 | TYPE_BCM2836_CONTROL); | |
bad56236 | 61 | |
14c520e3 TH |
62 | sysbus_init_child_obj(obj, "peripherals", &s->peripherals, |
63 | sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS); | |
f0afa731 SW |
64 | object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), |
65 | "board-rev", &error_abort); | |
5e9c2a8d GE |
66 | object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), |
67 | "vcram-size", &error_abort); | |
bad56236 AB |
68 | } |
69 | ||
70 | static void bcm2836_realize(DeviceState *dev, Error **errp) | |
71 | { | |
926dcdf0 | 72 | BCM283XState *s = BCM283X(dev); |
1bcb4d16 PM |
73 | BCM283XClass *bc = BCM283X_GET_CLASS(dev); |
74 | const BCM283XInfo *info = bc->info; | |
bad56236 AB |
75 | Object *obj; |
76 | Error *err = NULL; | |
77 | int n; | |
78 | ||
79 | /* common peripherals from bcm2835 */ | |
80 | ||
81 | obj = object_property_get_link(OBJECT(dev), "ram", &err); | |
82 | if (obj == NULL) { | |
83 | error_setg(errp, "%s: required ram link not found: %s", | |
84 | __func__, error_get_pretty(err)); | |
85 | return; | |
86 | } | |
87 | ||
88 | object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj, &err); | |
89 | if (err) { | |
90 | error_propagate(errp, err); | |
91 | return; | |
92 | } | |
93 | ||
94 | object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err); | |
95 | if (err) { | |
96 | error_propagate(errp, err); | |
97 | return; | |
98 | } | |
99 | ||
a55b53a2 AB |
100 | object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), |
101 | "sd-bus", &err); | |
102 | if (err) { | |
103 | error_propagate(errp, err); | |
104 | return; | |
105 | } | |
106 | ||
bad56236 | 107 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, |
d0567e94 | 108 | info->peri_base, 1); |
bad56236 AB |
109 | |
110 | /* bcm2836 interrupt controller (and mailboxes, etc.) */ | |
111 | object_property_set_bool(OBJECT(&s->control), true, "realized", &err); | |
112 | if (err) { | |
113 | error_propagate(errp, err); | |
114 | return; | |
115 | } | |
116 | ||
d0567e94 | 117 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base); |
bad56236 AB |
118 | |
119 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, | |
120 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); | |
121 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, | |
122 | qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); | |
123 | ||
926dcdf0 | 124 | for (n = 0; n < BCM283X_NCPUS; n++) { |
1bcb4d16 | 125 | /* TODO: this should be converted to a property of ARM_CPU */ |
5e5e9ed6 | 126 | s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n; |
bad56236 AB |
127 | |
128 | /* set periphbase/CBAR value for CPU-local registers */ | |
5e5e9ed6 | 129 | object_property_set_int(OBJECT(&s->cpu[n].core), |
d0567e94 | 130 | info->peri_base, |
bad56236 AB |
131 | "reset-cbar", &err); |
132 | if (err) { | |
133 | error_propagate(errp, err); | |
134 | return; | |
135 | } | |
136 | ||
137 | /* start powered off if not enabled */ | |
5e5e9ed6 | 138 | object_property_set_bool(OBJECT(&s->cpu[n].core), n >= s->enabled_cpus, |
bad56236 AB |
139 | "start-powered-off", &err); |
140 | if (err) { | |
141 | error_propagate(errp, err); | |
142 | return; | |
143 | } | |
144 | ||
5e5e9ed6 PMD |
145 | object_property_set_bool(OBJECT(&s->cpu[n].core), true, |
146 | "realized", &err); | |
bad56236 AB |
147 | if (err) { |
148 | error_propagate(errp, err); | |
149 | return; | |
150 | } | |
151 | ||
152 | /* Connect irq/fiq outputs from the interrupt controller. */ | |
153 | qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, | |
5e5e9ed6 | 154 | qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); |
bad56236 | 155 | qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, |
5e5e9ed6 | 156 | qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); |
bad56236 AB |
157 | |
158 | /* Connect timers from the CPU to the interrupt controller */ | |
5e5e9ed6 | 159 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, |
0dc19823 | 160 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); |
5e5e9ed6 | 161 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, |
bad56236 | 162 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); |
5e5e9ed6 | 163 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, |
0dc19823 | 164 | qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); |
5e5e9ed6 | 165 | qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, |
0dc19823 | 166 | qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); |
bad56236 AB |
167 | } |
168 | } | |
169 | ||
170 | static Property bcm2836_props[] = { | |
926dcdf0 PM |
171 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, |
172 | BCM283X_NCPUS), | |
bad56236 AB |
173 | DEFINE_PROP_END_OF_LIST() |
174 | }; | |
175 | ||
0fd74f03 | 176 | static void bcm283x_class_init(ObjectClass *oc, void *data) |
bad56236 AB |
177 | { |
178 | DeviceClass *dc = DEVICE_CLASS(oc); | |
0fd74f03 | 179 | BCM283XClass *bc = BCM283X_CLASS(oc); |
bad56236 | 180 | |
0fd74f03 | 181 | bc->info = data; |
bad56236 | 182 | dc->realize = bcm2836_realize; |
0fd74f03 | 183 | dc->props = bcm2836_props; |
cccf96c3 TH |
184 | /* Reason: Must be wired up in code (see raspi_init() function) */ |
185 | dc->user_creatable = false; | |
bad56236 AB |
186 | } |
187 | ||
0fd74f03 | 188 | static const TypeInfo bcm283x_type_info = { |
926dcdf0 | 189 | .name = TYPE_BCM283X, |
3d260cf3 | 190 | .parent = TYPE_DEVICE, |
926dcdf0 | 191 | .instance_size = sizeof(BCM283XState), |
bad56236 | 192 | .instance_init = bcm2836_init, |
0fd74f03 PM |
193 | .class_size = sizeof(BCM283XClass), |
194 | .abstract = true, | |
bad56236 AB |
195 | }; |
196 | ||
197 | static void bcm2836_register_types(void) | |
198 | { | |
0fd74f03 PM |
199 | int i; |
200 | ||
201 | type_register_static(&bcm283x_type_info); | |
202 | for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { | |
203 | TypeInfo ti = { | |
204 | .name = bcm283x_socs[i].name, | |
205 | .parent = TYPE_BCM283X, | |
206 | .class_init = bcm283x_class_init, | |
207 | .class_data = (void *) &bcm283x_socs[i], | |
208 | }; | |
209 | type_register(&ti); | |
210 | } | |
bad56236 AB |
211 | } |
212 | ||
213 | type_init(bcm2836_register_types) |