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Commit | Line | Data |
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5fafdf24 | 1 | /* |
16406950 PB |
2 | * ARM kernel loader. |
3 | * | |
9ee6e8bb | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
16406950 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
16406950 PB |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
2c65db5e | 11 | #include "qemu/datadir.h" |
c0dbca36 | 12 | #include "qemu/error-report.h" |
da34e65c | 13 | #include "qapi/error.h" |
b77257d7 | 14 | #include <libfdt.h> |
12ec8bd5 | 15 | #include "hw/arm/boot.h" |
d8b1ae42 | 16 | #include "hw/arm/linux-boot-if.h" |
baf6b681 | 17 | #include "sysemu/kvm.h" |
2b77ad4d | 18 | #include "sysemu/tcg.h" |
9c17d615 | 19 | #include "sysemu/sysemu.h" |
9695200a | 20 | #include "sysemu/numa.h" |
2744ece8 | 21 | #include "hw/boards.h" |
71e8a915 | 22 | #include "sysemu/reset.h" |
83c9f4ca | 23 | #include "hw/loader.h" |
ca20cf32 | 24 | #include "elf.h" |
9c17d615 | 25 | #include "sysemu/device_tree.h" |
1de7afc9 | 26 | #include "qemu/config-file.h" |
922a01a0 | 27 | #include "qemu/option.h" |
ea358872 | 28 | #include "qemu/units.h" |
16406950 | 29 | |
4d9ebf75 MH |
30 | /* Kernel boot protocol is specified in the kernel docs |
31 | * Documentation/arm/Booting and Documentation/arm64/booting.txt | |
32 | * They have different preferred image load offsets from system RAM base. | |
33 | */ | |
f831f955 NH |
34 | #define KERNEL_ARGS_ADDR 0x100 |
35 | #define KERNEL_NOLOAD_ADDR 0x02000000 | |
36 | #define KERNEL_LOAD_ADDR 0x00010000 | |
4d9ebf75 | 37 | #define KERNEL64_LOAD_ADDR 0x00080000 |
16406950 | 38 | |
68115ed5 AB |
39 | #define ARM64_TEXT_OFFSET_OFFSET 8 |
40 | #define ARM64_MAGIC_OFFSET 56 | |
41 | ||
ea358872 SH |
42 | #define BOOTLOADER_MAX_SIZE (4 * KiB) |
43 | ||
3b77f6c3 IM |
44 | AddressSpace *arm_boot_address_space(ARMCPU *cpu, |
45 | const struct arm_boot_info *info) | |
9f43d4c3 PM |
46 | { |
47 | /* Return the address space to use for bootloader reads and writes. | |
48 | * We prefer the secure address space if the CPU has it and we're | |
49 | * going to boot the guest into it. | |
50 | */ | |
51 | int asidx; | |
52 | CPUState *cs = CPU(cpu); | |
53 | ||
54 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { | |
55 | asidx = ARMASIdx_S; | |
56 | } else { | |
57 | asidx = ARMASIdx_NS; | |
58 | } | |
59 | ||
60 | return cpu_get_address_space(cs, asidx); | |
61 | } | |
62 | ||
4d9ebf75 MH |
63 | static const ARMInsnFixup bootloader_aarch64[] = { |
64 | { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ | |
65 | { 0xaa1f03e1 }, /* mov x1, xzr */ | |
66 | { 0xaa1f03e2 }, /* mov x2, xzr */ | |
67 | { 0xaa1f03e3 }, /* mov x3, xzr */ | |
68 | { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ | |
69 | { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ | |
751ebc13 RPB |
70 | { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ |
71 | { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ | |
72 | { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ | |
73 | { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ | |
4d9ebf75 MH |
74 | { 0, FIXUP_TERMINATOR } |
75 | }; | |
76 | ||
10b8ec73 PC |
77 | /* A very small bootloader: call the board-setup code (if needed), |
78 | * set r0-r2, then jump to the kernel. | |
79 | * If we're not calling boot setup code then we don't copy across | |
80 | * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. | |
81 | */ | |
82 | ||
47b1da81 | 83 | static const ARMInsnFixup bootloader[] = { |
b4850e5a | 84 | { 0xe28fe004 }, /* add lr, pc, #4 */ |
10b8ec73 PC |
85 | { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ |
86 | { 0, FIXUP_BOARD_SETUP }, | |
87 | #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 | |
47b1da81 PM |
88 | { 0xe3a00000 }, /* mov r0, #0 */ |
89 | { 0xe59f1004 }, /* ldr r1, [pc, #4] */ | |
90 | { 0xe59f2004 }, /* ldr r2, [pc, #4] */ | |
91 | { 0xe59ff004 }, /* ldr pc, [pc, #4] */ | |
92 | { 0, FIXUP_BOARDID }, | |
751ebc13 RPB |
93 | { 0, FIXUP_ARGPTR_LO }, |
94 | { 0, FIXUP_ENTRYPOINT_LO }, | |
47b1da81 | 95 | { 0, FIXUP_TERMINATOR } |
16406950 PB |
96 | }; |
97 | ||
9d5ba9bf ML |
98 | /* Handling for secondary CPU boot in a multicore system. |
99 | * Unlike the uniprocessor/primary CPU boot, this is platform | |
100 | * dependent. The default code here is based on the secondary | |
101 | * CPU boot protocol used on realview/vexpress boards, with | |
102 | * some parameterisation to increase its flexibility. | |
103 | * QEMU platform models for which this code is not appropriate | |
104 | * should override write_secondary_boot and secondary_cpu_reset_hook | |
105 | * instead. | |
106 | * | |
107 | * This code enables the interrupt controllers for the secondary | |
108 | * CPUs and then puts all the secondary CPUs into a loop waiting | |
109 | * for an interprocessor interrupt and polling a configurable | |
110 | * location for the kernel secondary CPU entry point. | |
111 | */ | |
bf471f79 PM |
112 | #define DSB_INSN 0xf57ff04f |
113 | #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ | |
114 | ||
47b1da81 PM |
115 | static const ARMInsnFixup smpboot[] = { |
116 | { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ | |
117 | { 0xe59f0028 }, /* ldr r0, bootreg_addr */ | |
118 | { 0xe3a01001 }, /* mov r1, #1 */ | |
119 | { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ | |
120 | { 0xe3a010ff }, /* mov r1, #0xff */ | |
121 | { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ | |
122 | { 0, FIXUP_DSB }, /* dsb */ | |
123 | { 0xe320f003 }, /* wfi */ | |
124 | { 0xe5901000 }, /* ldr r1, [r0] */ | |
125 | { 0xe1110001 }, /* tst r1, r1 */ | |
126 | { 0x0afffffb }, /* beq <wfi> */ | |
127 | { 0xe12fff11 }, /* bx r1 */ | |
128 | { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ | |
129 | { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ | |
130 | { 0, FIXUP_TERMINATOR } | |
9ee6e8bb PB |
131 | }; |
132 | ||
0fe43f0a CLG |
133 | void arm_write_bootloader(const char *name, |
134 | AddressSpace *as, hwaddr addr, | |
135 | const ARMInsnFixup *insns, | |
136 | const uint32_t *fixupcontext) | |
47b1da81 PM |
137 | { |
138 | /* Fix up the specified bootloader fragment and write it into | |
139 | * guest memory using rom_add_blob_fixed(). fixupcontext is | |
140 | * an array giving the values to write in for the fixup types | |
141 | * which write a value into the code array. | |
142 | */ | |
143 | int i, len; | |
144 | uint32_t *code; | |
145 | ||
146 | len = 0; | |
147 | while (insns[len].fixup != FIXUP_TERMINATOR) { | |
148 | len++; | |
149 | } | |
150 | ||
151 | code = g_new0(uint32_t, len); | |
152 | ||
153 | for (i = 0; i < len; i++) { | |
154 | uint32_t insn = insns[i].insn; | |
155 | FixupType fixup = insns[i].fixup; | |
156 | ||
157 | switch (fixup) { | |
158 | case FIXUP_NONE: | |
159 | break; | |
160 | case FIXUP_BOARDID: | |
10b8ec73 | 161 | case FIXUP_BOARD_SETUP: |
751ebc13 RPB |
162 | case FIXUP_ARGPTR_LO: |
163 | case FIXUP_ARGPTR_HI: | |
164 | case FIXUP_ENTRYPOINT_LO: | |
165 | case FIXUP_ENTRYPOINT_HI: | |
47b1da81 PM |
166 | case FIXUP_GIC_CPU_IF: |
167 | case FIXUP_BOOTREG: | |
168 | case FIXUP_DSB: | |
169 | insn = fixupcontext[fixup]; | |
170 | break; | |
171 | default: | |
172 | abort(); | |
173 | } | |
174 | code[i] = tswap32(insn); | |
175 | } | |
176 | ||
ea358872 SH |
177 | assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); |
178 | ||
9f43d4c3 | 179 | rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); |
47b1da81 PM |
180 | |
181 | g_free(code); | |
182 | } | |
183 | ||
9543b0cd | 184 | static void default_write_secondary(ARMCPU *cpu, |
9d5ba9bf ML |
185 | const struct arm_boot_info *info) |
186 | { | |
47b1da81 | 187 | uint32_t fixupcontext[FIXUP_MAX]; |
9f43d4c3 | 188 | AddressSpace *as = arm_boot_address_space(cpu, info); |
47b1da81 PM |
189 | |
190 | fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; | |
191 | fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; | |
192 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
193 | fixupcontext[FIXUP_DSB] = DSB_INSN; | |
194 | } else { | |
195 | fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; | |
9d5ba9bf | 196 | } |
47b1da81 | 197 | |
0fe43f0a CLG |
198 | arm_write_bootloader("smpboot", as, info->smp_loader_start, |
199 | smpboot, fixupcontext); | |
9d5ba9bf ML |
200 | } |
201 | ||
716536a9 AB |
202 | void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, |
203 | const struct arm_boot_info *info, | |
204 | hwaddr mvbar_addr) | |
205 | { | |
9f43d4c3 | 206 | AddressSpace *as = arm_boot_address_space(cpu, info); |
716536a9 AB |
207 | int n; |
208 | uint32_t mvbar_blob[] = { | |
209 | /* mvbar_addr: secure monitor vectors | |
210 | * Default unimplemented and unused vectors to spin. Makes it | |
211 | * easier to debug (as opposed to the CPU running away). | |
212 | */ | |
213 | 0xeafffffe, /* (spin) */ | |
214 | 0xeafffffe, /* (spin) */ | |
215 | 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ | |
216 | 0xeafffffe, /* (spin) */ | |
217 | 0xeafffffe, /* (spin) */ | |
218 | 0xeafffffe, /* (spin) */ | |
219 | 0xeafffffe, /* (spin) */ | |
220 | 0xeafffffe, /* (spin) */ | |
221 | }; | |
222 | uint32_t board_setup_blob[] = { | |
223 | /* board setup addr */ | |
45c078f1 CD |
224 | 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ |
225 | 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ | |
226 | 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ | |
716536a9 AB |
227 | 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ |
228 | 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ | |
229 | 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ | |
230 | 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ | |
231 | 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ | |
232 | 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ | |
233 | 0xe1600070, /* smc #0 ;call monitor to flush SCR */ | |
234 | 0xe1a0f001, /* mov pc, r1 ;return */ | |
235 | }; | |
236 | ||
237 | /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ | |
238 | assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); | |
239 | ||
240 | /* check that these blobs don't overlap */ | |
241 | assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) | |
242 | || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); | |
243 | ||
244 | for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { | |
245 | mvbar_blob[n] = tswap32(mvbar_blob[n]); | |
246 | } | |
9f43d4c3 PM |
247 | rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), |
248 | mvbar_addr, as); | |
716536a9 AB |
249 | |
250 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | |
251 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | |
252 | } | |
9f43d4c3 PM |
253 | rom_add_blob_fixed_as("board-setup", board_setup_blob, |
254 | sizeof(board_setup_blob), info->board_setup_addr, as); | |
716536a9 AB |
255 | } |
256 | ||
5d309320 | 257 | static void default_reset_secondary(ARMCPU *cpu, |
9d5ba9bf ML |
258 | const struct arm_boot_info *info) |
259 | { | |
9f43d4c3 | 260 | AddressSpace *as = arm_boot_address_space(cpu, info); |
4df81c6e | 261 | CPUState *cs = CPU(cpu); |
5d309320 | 262 | |
9f43d4c3 | 263 | address_space_stl_notdirty(as, info->smp_bootreg_addr, |
42874d3a | 264 | 0, MEMTXATTRS_UNSPECIFIED, NULL); |
4df81c6e | 265 | cpu_set_pc(cs, info->smp_loader_start); |
9d5ba9bf ML |
266 | } |
267 | ||
83bfffec PM |
268 | static inline bool have_dtb(const struct arm_boot_info *info) |
269 | { | |
270 | return info->dtb_filename || info->get_dtb; | |
271 | } | |
272 | ||
52b43737 | 273 | #define WRITE_WORD(p, value) do { \ |
9f43d4c3 | 274 | address_space_stl_notdirty(as, p, value, \ |
42874d3a | 275 | MEMTXATTRS_UNSPECIFIED, NULL); \ |
52b43737 PB |
276 | p += 4; \ |
277 | } while (0) | |
278 | ||
9f43d4c3 | 279 | static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) |
16406950 | 280 | { |
761c9eb0 | 281 | int initrd_size = info->initrd_size; |
a8170e5e AK |
282 | hwaddr base = info->loader_start; |
283 | hwaddr p; | |
16406950 | 284 | |
52b43737 | 285 | p = base + KERNEL_ARGS_ADDR; |
16406950 | 286 | /* ATAG_CORE */ |
52b43737 PB |
287 | WRITE_WORD(p, 5); |
288 | WRITE_WORD(p, 0x54410001); | |
289 | WRITE_WORD(p, 1); | |
290 | WRITE_WORD(p, 0x1000); | |
291 | WRITE_WORD(p, 0); | |
16406950 | 292 | /* ATAG_MEM */ |
f93eb9ff | 293 | /* TODO: handle multiple chips on one ATAG list */ |
52b43737 PB |
294 | WRITE_WORD(p, 4); |
295 | WRITE_WORD(p, 0x54410002); | |
296 | WRITE_WORD(p, info->ram_size); | |
297 | WRITE_WORD(p, info->loader_start); | |
16406950 PB |
298 | if (initrd_size) { |
299 | /* ATAG_INITRD2 */ | |
52b43737 PB |
300 | WRITE_WORD(p, 4); |
301 | WRITE_WORD(p, 0x54420005); | |
fc53b7d4 | 302 | WRITE_WORD(p, info->initrd_start); |
52b43737 | 303 | WRITE_WORD(p, initrd_size); |
16406950 | 304 | } |
f93eb9ff | 305 | if (info->kernel_cmdline && *info->kernel_cmdline) { |
16406950 PB |
306 | /* ATAG_CMDLINE */ |
307 | int cmdline_size; | |
308 | ||
f93eb9ff | 309 | cmdline_size = strlen(info->kernel_cmdline); |
9f43d4c3 | 310 | address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, |
b7cbebf2 | 311 | info->kernel_cmdline, cmdline_size + 1); |
16406950 | 312 | cmdline_size = (cmdline_size >> 2) + 1; |
52b43737 PB |
313 | WRITE_WORD(p, cmdline_size + 2); |
314 | WRITE_WORD(p, 0x54410009); | |
315 | p += cmdline_size * 4; | |
16406950 | 316 | } |
f93eb9ff AZ |
317 | if (info->atag_board) { |
318 | /* ATAG_BOARD */ | |
319 | int atag_board_len; | |
52b43737 | 320 | uint8_t atag_board_buf[0x1000]; |
f93eb9ff | 321 | |
52b43737 PB |
322 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; |
323 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | |
324 | WRITE_WORD(p, 0x414f4d50); | |
9f43d4c3 PM |
325 | address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, |
326 | atag_board_buf, atag_board_len); | |
f93eb9ff AZ |
327 | p += atag_board_len; |
328 | } | |
16406950 | 329 | /* ATAG_END */ |
52b43737 PB |
330 | WRITE_WORD(p, 0); |
331 | WRITE_WORD(p, 0); | |
16406950 PB |
332 | } |
333 | ||
9f43d4c3 PM |
334 | static void set_kernel_args_old(const struct arm_boot_info *info, |
335 | AddressSpace *as) | |
2b8f2d41 | 336 | { |
a8170e5e | 337 | hwaddr p; |
52b43737 | 338 | const char *s; |
761c9eb0 | 339 | int initrd_size = info->initrd_size; |
a8170e5e | 340 | hwaddr base = info->loader_start; |
2b8f2d41 AZ |
341 | |
342 | /* see linux/include/asm-arm/setup.h */ | |
52b43737 | 343 | p = base + KERNEL_ARGS_ADDR; |
2b8f2d41 | 344 | /* page_size */ |
52b43737 | 345 | WRITE_WORD(p, 4096); |
2b8f2d41 | 346 | /* nr_pages */ |
52b43737 | 347 | WRITE_WORD(p, info->ram_size / 4096); |
2b8f2d41 | 348 | /* ramdisk_size */ |
52b43737 | 349 | WRITE_WORD(p, 0); |
2b8f2d41 AZ |
350 | #define FLAG_READONLY 1 |
351 | #define FLAG_RDLOAD 4 | |
352 | #define FLAG_RDPROMPT 8 | |
353 | /* flags */ | |
52b43737 | 354 | WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); |
2b8f2d41 | 355 | /* rootdev */ |
52b43737 | 356 | WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ |
2b8f2d41 | 357 | /* video_num_cols */ |
52b43737 | 358 | WRITE_WORD(p, 0); |
2b8f2d41 | 359 | /* video_num_rows */ |
52b43737 | 360 | WRITE_WORD(p, 0); |
2b8f2d41 | 361 | /* video_x */ |
52b43737 | 362 | WRITE_WORD(p, 0); |
2b8f2d41 | 363 | /* video_y */ |
52b43737 | 364 | WRITE_WORD(p, 0); |
2b8f2d41 | 365 | /* memc_control_reg */ |
52b43737 | 366 | WRITE_WORD(p, 0); |
2b8f2d41 AZ |
367 | /* unsigned char sounddefault */ |
368 | /* unsigned char adfsdrives */ | |
369 | /* unsigned char bytes_per_char_h */ | |
370 | /* unsigned char bytes_per_char_v */ | |
52b43737 | 371 | WRITE_WORD(p, 0); |
2b8f2d41 | 372 | /* pages_in_bank[4] */ |
52b43737 PB |
373 | WRITE_WORD(p, 0); |
374 | WRITE_WORD(p, 0); | |
375 | WRITE_WORD(p, 0); | |
376 | WRITE_WORD(p, 0); | |
2b8f2d41 | 377 | /* pages_in_vram */ |
52b43737 | 378 | WRITE_WORD(p, 0); |
2b8f2d41 | 379 | /* initrd_start */ |
fc53b7d4 PM |
380 | if (initrd_size) { |
381 | WRITE_WORD(p, info->initrd_start); | |
382 | } else { | |
52b43737 | 383 | WRITE_WORD(p, 0); |
fc53b7d4 | 384 | } |
2b8f2d41 | 385 | /* initrd_size */ |
52b43737 | 386 | WRITE_WORD(p, initrd_size); |
2b8f2d41 | 387 | /* rd_start */ |
52b43737 | 388 | WRITE_WORD(p, 0); |
2b8f2d41 | 389 | /* system_rev */ |
52b43737 | 390 | WRITE_WORD(p, 0); |
2b8f2d41 | 391 | /* system_serial_low */ |
52b43737 | 392 | WRITE_WORD(p, 0); |
2b8f2d41 | 393 | /* system_serial_high */ |
52b43737 | 394 | WRITE_WORD(p, 0); |
2b8f2d41 | 395 | /* mem_fclk_21285 */ |
52b43737 | 396 | WRITE_WORD(p, 0); |
2b8f2d41 | 397 | /* zero unused fields */ |
52b43737 PB |
398 | while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { |
399 | WRITE_WORD(p, 0); | |
400 | } | |
401 | s = info->kernel_cmdline; | |
402 | if (s) { | |
b7cbebf2 | 403 | address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); |
52b43737 PB |
404 | } else { |
405 | WRITE_WORD(p, 0); | |
406 | } | |
2b8f2d41 AZ |
407 | } |
408 | ||
f08ced69 SK |
409 | static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, |
410 | uint32_t scells, hwaddr mem_len, | |
411 | int numa_node_id) | |
412 | { | |
413 | char *nodename; | |
414 | int ret; | |
415 | ||
416 | nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); | |
417 | qemu_fdt_add_subnode(fdt, nodename); | |
418 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
419 | ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, | |
420 | scells, mem_len); | |
421 | if (ret < 0) { | |
422 | goto out; | |
423 | } | |
424 | ||
425 | /* only set the NUMA ID if it is specified */ | |
426 | if (numa_node_id >= 0) { | |
427 | ret = qemu_fdt_setprop_cell(fdt, nodename, | |
428 | "numa-node-id", numa_node_id); | |
429 | } | |
430 | out: | |
431 | g_free(nodename); | |
432 | return ret; | |
433 | } | |
434 | ||
4cbca7d9 AS |
435 | static void fdt_add_psci_node(void *fdt) |
436 | { | |
437 | uint32_t cpu_suspend_fn; | |
438 | uint32_t cpu_off_fn; | |
439 | uint32_t cpu_on_fn; | |
440 | uint32_t migrate_fn; | |
441 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); | |
442 | const char *psci_method; | |
443 | int64_t psci_conduit; | |
c39770cd | 444 | int rc; |
4cbca7d9 AS |
445 | |
446 | psci_conduit = object_property_get_int(OBJECT(armcpu), | |
447 | "psci-conduit", | |
448 | &error_abort); | |
449 | switch (psci_conduit) { | |
450 | case QEMU_PSCI_CONDUIT_DISABLED: | |
451 | return; | |
452 | case QEMU_PSCI_CONDUIT_HVC: | |
453 | psci_method = "hvc"; | |
454 | break; | |
455 | case QEMU_PSCI_CONDUIT_SMC: | |
456 | psci_method = "smc"; | |
457 | break; | |
458 | default: | |
459 | g_assert_not_reached(); | |
460 | } | |
461 | ||
c39770cd | 462 | /* |
e4b0bb80 PM |
463 | * A pre-existing /psci node might specify function ID values |
464 | * that don't match QEMU's PSCI implementation. Delete the whole | |
465 | * node and put our own in instead. | |
c39770cd AS |
466 | */ |
467 | rc = fdt_path_offset(fdt, "/psci"); | |
468 | if (rc >= 0) { | |
e4b0bb80 | 469 | qemu_fdt_nop_node(fdt, "/psci"); |
c39770cd AS |
470 | } |
471 | ||
4cbca7d9 | 472 | qemu_fdt_add_subnode(fdt, "/psci"); |
dc8bc9d6 PM |
473 | if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { |
474 | if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { | |
0dc71c70 AO |
475 | const char comp[] = "arm,psci-0.2\0arm,psci"; |
476 | qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | |
477 | } else { | |
478 | const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; | |
479 | qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | |
480 | } | |
4cbca7d9 AS |
481 | |
482 | cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; | |
483 | if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { | |
484 | cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; | |
485 | cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; | |
486 | migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; | |
487 | } else { | |
488 | cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; | |
489 | cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; | |
490 | migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; | |
491 | } | |
492 | } else { | |
493 | qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); | |
494 | ||
495 | cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; | |
496 | cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; | |
497 | cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; | |
498 | migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; | |
499 | } | |
500 | ||
501 | /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer | |
502 | * to the instruction that should be used to invoke PSCI functions. | |
503 | * However, the device tree binding uses 'method' instead, so that is | |
504 | * what we should use here. | |
505 | */ | |
506 | qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); | |
507 | ||
508 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); | |
509 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); | |
510 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); | |
511 | qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); | |
512 | } | |
513 | ||
3b77f6c3 | 514 | int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, |
2744ece8 | 515 | hwaddr addr_limit, AddressSpace *as, MachineState *ms) |
412beee6 | 516 | { |
412beee6 | 517 | void *fdt = NULL; |
e2eb3d29 | 518 | int size, rc, n = 0; |
70976c41 | 519 | uint32_t acells, scells; |
9695200a SZ |
520 | unsigned int i; |
521 | hwaddr mem_base, mem_len; | |
e2eb3d29 EA |
522 | char **node_path; |
523 | Error *err = NULL; | |
412beee6 | 524 | |
0fb79851 JR |
525 | if (binfo->dtb_filename) { |
526 | char *filename; | |
527 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); | |
528 | if (!filename) { | |
529 | fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); | |
530 | goto fail; | |
531 | } | |
412beee6 | 532 | |
0fb79851 JR |
533 | fdt = load_device_tree(filename, &size); |
534 | if (!fdt) { | |
535 | fprintf(stderr, "Couldn't open dtb file %s\n", filename); | |
536 | g_free(filename); | |
537 | goto fail; | |
538 | } | |
412beee6 | 539 | g_free(filename); |
a554ecb4 | 540 | } else { |
0fb79851 JR |
541 | fdt = binfo->get_dtb(binfo, &size); |
542 | if (!fdt) { | |
543 | fprintf(stderr, "Board was unable to create a dtb blob\n"); | |
544 | goto fail; | |
545 | } | |
412beee6 | 546 | } |
412beee6 | 547 | |
fee8ea12 AB |
548 | if (addr_limit > addr && size > (addr_limit - addr)) { |
549 | /* Installing the device tree blob at addr would exceed addr_limit. | |
550 | * Whether this constitutes failure is up to the caller to decide, | |
551 | * so just return 0 as size, i.e., no error. | |
552 | */ | |
553 | g_free(fdt); | |
554 | return 0; | |
555 | } | |
556 | ||
58e71097 EA |
557 | acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", |
558 | NULL, &error_fatal); | |
559 | scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", | |
560 | NULL, &error_fatal); | |
9bfa659e PM |
561 | if (acells == 0 || scells == 0) { |
562 | fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); | |
c23045de | 563 | goto fail; |
9bfa659e PM |
564 | } |
565 | ||
e4e34855 | 566 | if (scells < 2 && binfo->ram_size >= 4 * GiB) { |
70976c41 PM |
567 | /* This is user error so deserves a friendlier error message |
568 | * than the failure of setprop_sized_cells would provide | |
569 | */ | |
9bfa659e PM |
570 | fprintf(stderr, "qemu: dtb file not compatible with " |
571 | "RAM size > 4GB\n"); | |
c23045de | 572 | goto fail; |
9bfa659e PM |
573 | } |
574 | ||
e2eb3d29 EA |
575 | /* nop all root nodes matching /memory or /memory@unit-address */ |
576 | node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); | |
577 | if (err) { | |
578 | error_report_err(err); | |
579 | goto fail; | |
580 | } | |
581 | while (node_path[n]) { | |
582 | if (g_str_has_prefix(node_path[n], "/memory")) { | |
583 | qemu_fdt_nop_node(fdt, node_path[n]); | |
584 | } | |
585 | n++; | |
586 | } | |
587 | g_strfreev(node_path); | |
588 | ||
99abb725 GS |
589 | /* |
590 | * We drop all the memory nodes which correspond to empty NUMA nodes | |
591 | * from the device tree, because the Linux NUMA binding document | |
592 | * states they should not be generated. Linux will get the NUMA node | |
593 | * IDs of the empty NUMA nodes from the distance map if they are needed. | |
594 | * This means QEMU users may be obliged to provide command lines which | |
595 | * configure distance maps when the empty NUMA node IDs are needed and | |
596 | * Linux's default distance map isn't sufficient. | |
597 | */ | |
aa570207 | 598 | if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { |
9695200a | 599 | mem_base = binfo->loader_start; |
aa570207 | 600 | for (i = 0; i < ms->numa_state->num_nodes; i++) { |
7e721e7b | 601 | mem_len = ms->numa_state->nodes[i].node_mem; |
99abb725 GS |
602 | if (!mem_len) { |
603 | continue; | |
604 | } | |
605 | ||
f08ced69 SK |
606 | rc = fdt_add_memory_node(fdt, acells, mem_base, |
607 | scells, mem_len, i); | |
9695200a | 608 | if (rc < 0) { |
f08ced69 SK |
609 | fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", |
610 | mem_base); | |
9695200a SZ |
611 | goto fail; |
612 | } | |
613 | ||
9695200a | 614 | mem_base += mem_len; |
9695200a SZ |
615 | } |
616 | } else { | |
f08ced69 SK |
617 | rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, |
618 | scells, binfo->ram_size, -1); | |
9695200a | 619 | if (rc < 0) { |
f08ced69 SK |
620 | fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", |
621 | binfo->loader_start); | |
9695200a SZ |
622 | goto fail; |
623 | } | |
412beee6 GL |
624 | } |
625 | ||
b77257d7 GR |
626 | rc = fdt_path_offset(fdt, "/chosen"); |
627 | if (rc < 0) { | |
628 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
629 | } | |
630 | ||
2744ece8 | 631 | if (ms->kernel_cmdline && *ms->kernel_cmdline) { |
5a4348d1 | 632 | rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
2744ece8 | 633 | ms->kernel_cmdline); |
5e87975c PC |
634 | if (rc < 0) { |
635 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
c23045de | 636 | goto fail; |
5e87975c | 637 | } |
412beee6 GL |
638 | } |
639 | ||
640 | if (binfo->initrd_size) { | |
990f49cf SS |
641 | rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", |
642 | acells, binfo->initrd_start); | |
412beee6 GL |
643 | if (rc < 0) { |
644 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
c23045de | 645 | goto fail; |
412beee6 GL |
646 | } |
647 | ||
990f49cf SS |
648 | rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", |
649 | acells, | |
650 | binfo->initrd_start + | |
651 | binfo->initrd_size); | |
412beee6 GL |
652 | if (rc < 0) { |
653 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
c23045de | 654 | goto fail; |
412beee6 GL |
655 | } |
656 | } | |
3b1cceb8 | 657 | |
4cbca7d9 AS |
658 | fdt_add_psci_node(fdt); |
659 | ||
3b1cceb8 PM |
660 | if (binfo->modify_dtb) { |
661 | binfo->modify_dtb(binfo, fdt); | |
662 | } | |
663 | ||
5a4348d1 | 664 | qemu_fdt_dumpdtb(fdt, size); |
412beee6 | 665 | |
4c4bf654 AB |
666 | /* Put the DTB into the memory map as a ROM image: this will ensure |
667 | * the DTB is copied again upon reset, even if addr points into RAM. | |
668 | */ | |
9f43d4c3 | 669 | rom_add_blob_fixed_as("dtb", fdt, size, addr, as); |
98aa4c83 JD |
670 | qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, |
671 | rom_ptr_for_as(as, addr, size)); | |
412beee6 | 672 | |
12148d44 MA |
673 | if (fdt != ms->fdt) { |
674 | g_free(ms->fdt); | |
675 | ms->fdt = fdt; | |
676 | } | |
c23045de | 677 | |
fee8ea12 | 678 | return size; |
c23045de PM |
679 | |
680 | fail: | |
681 | g_free(fdt); | |
682 | return -1; | |
412beee6 GL |
683 | } |
684 | ||
6ed221b6 | 685 | static void do_cpu_reset(void *opaque) |
f2d74978 | 686 | { |
351d5666 | 687 | ARMCPU *cpu = opaque; |
4df81c6e | 688 | CPUState *cs = CPU(cpu); |
351d5666 | 689 | CPUARMState *env = &cpu->env; |
462a8bc6 | 690 | const struct arm_boot_info *info = env->boot_info; |
f2d74978 | 691 | |
4df81c6e | 692 | cpu_reset(cs); |
f2d74978 PB |
693 | if (info) { |
694 | if (!info->is_linux) { | |
9776f636 | 695 | int i; |
f2d74978 | 696 | /* Jump to the entry point. */ |
4df81c6e PC |
697 | uint64_t entry = info->entry; |
698 | ||
9776f636 PC |
699 | switch (info->endianness) { |
700 | case ARM_ENDIANNESS_LE: | |
701 | env->cp15.sctlr_el[1] &= ~SCTLR_E0E; | |
702 | for (i = 1; i < 4; ++i) { | |
703 | env->cp15.sctlr_el[i] &= ~SCTLR_EE; | |
704 | } | |
705 | env->uncached_cpsr &= ~CPSR_E; | |
706 | break; | |
707 | case ARM_ENDIANNESS_BE8: | |
708 | env->cp15.sctlr_el[1] |= SCTLR_E0E; | |
709 | for (i = 1; i < 4; ++i) { | |
710 | env->cp15.sctlr_el[i] |= SCTLR_EE; | |
711 | } | |
712 | env->uncached_cpsr |= CPSR_E; | |
713 | break; | |
714 | case ARM_ENDIANNESS_BE32: | |
715 | env->cp15.sctlr_el[1] |= SCTLR_B; | |
716 | break; | |
717 | case ARM_ENDIANNESS_UNKNOWN: | |
718 | break; /* Board's decision */ | |
719 | default: | |
720 | g_assert_not_reached(); | |
721 | } | |
722 | ||
4df81c6e | 723 | cpu_set_pc(cs, entry); |
f2d74978 | 724 | } else { |
3a45f4f5 PM |
725 | /* |
726 | * If we are booting Linux then we might need to do so at: | |
727 | * - AArch64 NS EL2 or NS EL1 | |
728 | * - AArch32 Secure SVC (EL3) | |
729 | * - AArch32 NS Hyp (EL2) | |
730 | * - AArch32 NS SVC (EL1) | |
731 | * Configure the CPU in the way boot firmware would do to | |
732 | * drop us down to the appropriate level. | |
c8e829b7 | 733 | */ |
3a45f4f5 | 734 | int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; |
5097227c | 735 | |
3a45f4f5 | 736 | if (env->aarch64) { |
299953b9 | 737 | /* |
3a45f4f5 PM |
738 | * AArch64 kernels never boot in secure mode, and we don't |
739 | * support the secure_board_setup hook for AArch64. | |
299953b9 | 740 | */ |
3a45f4f5 PM |
741 | assert(!info->secure_boot); |
742 | assert(!info->secure_board_setup); | |
743 | } else { | |
744 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
745 | (info->secure_boot || | |
746 | (info->secure_board_setup && cs == first_cpu))) { | |
747 | /* Start this CPU in Secure SVC */ | |
748 | target_el = 3; | |
749 | } | |
299953b9 PM |
750 | } |
751 | ||
3a45f4f5 PM |
752 | arm_emulate_firmware_reset(cs, target_el); |
753 | ||
4df81c6e | 754 | if (cs == first_cpu) { |
9f43d4c3 PM |
755 | AddressSpace *as = arm_boot_address_space(cpu, info); |
756 | ||
4df81c6e | 757 | cpu_set_pc(cs, info->loader_start); |
4d9ebf75 | 758 | |
83bfffec | 759 | if (!have_dtb(info)) { |
412beee6 | 760 | if (old_param) { |
9f43d4c3 | 761 | set_kernel_args_old(info, as); |
412beee6 | 762 | } else { |
9f43d4c3 | 763 | set_kernel_args(info, as); |
412beee6 | 764 | } |
6ed221b6 | 765 | } |
d4a29ed6 | 766 | } else if (info->secondary_cpu_reset_hook) { |
5d309320 | 767 | info->secondary_cpu_reset_hook(cpu, info); |
f2d74978 PB |
768 | } |
769 | } | |
2b77ad4d FR |
770 | |
771 | if (tcg_enabled()) { | |
772 | arm_rebuild_hflags(env); | |
773 | } | |
f2d74978 | 774 | } |
f2d74978 PB |
775 | } |
776 | ||
d8b1ae42 PM |
777 | static int do_arm_linux_init(Object *obj, void *opaque) |
778 | { | |
779 | if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { | |
780 | ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); | |
781 | ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); | |
782 | struct arm_boot_info *info = opaque; | |
783 | ||
784 | if (albifc->arm_linux_init) { | |
785 | albifc->arm_linux_init(albif, info->secure_boot); | |
786 | } | |
787 | } | |
788 | return 0; | |
789 | } | |
790 | ||
af975131 | 791 | static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, |
a3f0ecfd AL |
792 | uint64_t *lowaddr, uint64_t *highaddr, |
793 | int elf_machine, AddressSpace *as) | |
9776f636 PC |
794 | { |
795 | bool elf_is64; | |
796 | union { | |
797 | Elf32_Ehdr h32; | |
798 | Elf64_Ehdr h64; | |
799 | } elf_header; | |
800 | int data_swab = 0; | |
801 | bool big_endian; | |
af975131 | 802 | ssize_t ret = -1; |
9776f636 PC |
803 | Error *err = NULL; |
804 | ||
805 | ||
806 | load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); | |
807 | if (err) { | |
36f876ce | 808 | error_free(err); |
9776f636 PC |
809 | return ret; |
810 | } | |
811 | ||
812 | if (elf_is64) { | |
813 | big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB; | |
814 | info->endianness = big_endian ? ARM_ENDIANNESS_BE8 | |
815 | : ARM_ENDIANNESS_LE; | |
816 | } else { | |
817 | big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB; | |
818 | if (big_endian) { | |
819 | if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { | |
820 | info->endianness = ARM_ENDIANNESS_BE8; | |
821 | } else { | |
822 | info->endianness = ARM_ENDIANNESS_BE32; | |
823 | /* In BE32, the CPU has a different view of the per-byte | |
824 | * address map than the rest of the system. BE32 ELF files | |
825 | * are organised such that they can be programmed through | |
826 | * the CPU's per-word byte-reversed view of the world. QEMU | |
827 | * however loads ELF files independently of the CPU. So | |
828 | * tell the ELF loader to byte reverse the data for us. | |
829 | */ | |
830 | data_swab = 2; | |
831 | } | |
832 | } else { | |
833 | info->endianness = ARM_ENDIANNESS_LE; | |
834 | } | |
835 | } | |
836 | ||
4366e1db | 837 | ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, |
6cdda0ff | 838 | pentry, lowaddr, highaddr, NULL, big_endian, elf_machine, |
9f43d4c3 | 839 | 1, data_swab, as); |
9776f636 PC |
840 | if (ret <= 0) { |
841 | /* The header loaded but the image didn't */ | |
842 | exit(1); | |
843 | } | |
844 | ||
845 | return ret; | |
846 | } | |
847 | ||
68115ed5 | 848 | static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, |
9f43d4c3 | 849 | hwaddr *entry, AddressSpace *as) |
68115ed5 AB |
850 | { |
851 | hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; | |
5e6dbe1e | 852 | uint64_t kernel_size = 0; |
68115ed5 AB |
853 | uint8_t *buffer; |
854 | int size; | |
855 | ||
856 | /* On aarch64, it's the bootloader's job to uncompress the kernel. */ | |
857 | size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, | |
858 | &buffer); | |
859 | ||
860 | if (size < 0) { | |
861 | gsize len; | |
862 | ||
863 | /* Load as raw file otherwise */ | |
864 | if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { | |
865 | return -1; | |
866 | } | |
867 | size = len; | |
ff114228 AB |
868 | |
869 | /* Unpack the image if it is a EFI zboot image */ | |
870 | if (unpack_efi_zboot_image(&buffer, &size) < 0) { | |
871 | g_free(buffer); | |
872 | return -1; | |
873 | } | |
68115ed5 AB |
874 | } |
875 | ||
876 | /* check the arm64 magic header value -- very old kernels may not have it */ | |
27640407 MAL |
877 | if (size > ARM64_MAGIC_OFFSET + 4 && |
878 | memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { | |
68115ed5 AB |
879 | uint64_t hdrvals[2]; |
880 | ||
881 | /* The arm64 Image header has text_offset and image_size fields at 8 and | |
882 | * 16 bytes into the Image header, respectively. The text_offset field | |
883 | * is only valid if the image_size is non-zero. | |
884 | */ | |
885 | memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); | |
5e6dbe1e PM |
886 | |
887 | kernel_size = le64_to_cpu(hdrvals[1]); | |
888 | ||
889 | if (kernel_size != 0) { | |
68115ed5 | 890 | kernel_load_offset = le64_to_cpu(hdrvals[0]); |
ea358872 SH |
891 | |
892 | /* | |
893 | * We write our startup "bootloader" at the very bottom of RAM, | |
894 | * so that bit can't be used for the image. Luckily the Image | |
895 | * format specification is that the image requests only an offset | |
896 | * from a 2MB boundary, not an absolute load address. So if the | |
897 | * image requests an offset that might mean it overlaps with the | |
898 | * bootloader, we can just load it starting at 2MB+offset rather | |
899 | * than 0MB + offset. | |
900 | */ | |
901 | if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { | |
902 | kernel_load_offset += 2 * MiB; | |
903 | } | |
68115ed5 AB |
904 | } |
905 | } | |
906 | ||
5e6dbe1e PM |
907 | /* |
908 | * Kernels before v3.17 don't populate the image_size field, and | |
909 | * raw images have no header. For those our best guess at the size | |
910 | * is the size of the Image file itself. | |
911 | */ | |
912 | if (kernel_size == 0) { | |
913 | kernel_size = size; | |
914 | } | |
915 | ||
68115ed5 | 916 | *entry = mem_base + kernel_load_offset; |
9f43d4c3 | 917 | rom_add_blob_fixed_as(filename, buffer, size, *entry, as); |
68115ed5 AB |
918 | |
919 | g_free(buffer); | |
920 | ||
5e6dbe1e | 921 | return kernel_size; |
68115ed5 AB |
922 | } |
923 | ||
d33774ee PM |
924 | static void arm_setup_direct_kernel_boot(ARMCPU *cpu, |
925 | struct arm_boot_info *info) | |
16406950 | 926 | { |
d33774ee | 927 | /* Set up for a direct boot of a kernel image file. */ |
c6faa758 | 928 | CPUState *cs; |
d33774ee | 929 | AddressSpace *as = arm_boot_address_space(cpu, info); |
af975131 | 930 | ssize_t kernel_size; |
16406950 | 931 | int initrd_size; |
1c7b3754 | 932 | int is_linux = 0; |
d5fef92f PM |
933 | uint64_t elf_entry; |
934 | /* Addresses of first byte used and first byte not used by the image */ | |
67505c11 | 935 | uint64_t image_low_addr = 0, image_high_addr = 0; |
da0af40d | 936 | int elf_machine; |
68115ed5 | 937 | hwaddr entry; |
4d9ebf75 | 938 | static const ARMInsnFixup *primary_loader; |
e70af24b | 939 | uint64_t ram_end = info->loader_start + info->ram_size; |
daf90626 | 940 | |
4d9ebf75 MH |
941 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
942 | primary_loader = bootloader_aarch64; | |
da0af40d | 943 | elf_machine = EM_AARCH64; |
4d9ebf75 MH |
944 | } else { |
945 | primary_loader = bootloader; | |
10b8ec73 PC |
946 | if (!info->write_board_setup) { |
947 | primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; | |
948 | } | |
da0af40d | 949 | elf_machine = EM_ARM; |
4d9ebf75 MH |
950 | } |
951 | ||
1c7b3754 | 952 | /* Assume that raw images are linux kernels, and ELF images are not. */ |
d5fef92f PM |
953 | kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, |
954 | &image_high_addr, elf_machine, as); | |
92df8450 | 955 | if (kernel_size > 0 && have_dtb(info)) { |
c3a42358 PM |
956 | /* |
957 | * If there is still some room left at the base of RAM, try and put | |
92df8450 AB |
958 | * the DTB there like we do for images loaded with -bios or -pflash. |
959 | */ | |
d5fef92f PM |
960 | if (image_low_addr > info->loader_start |
961 | || image_high_addr < info->loader_start) { | |
c3a42358 | 962 | /* |
d5fef92f | 963 | * Set image_low_addr as address limit for arm_load_dtb if it may be |
92df8450 AB |
964 | * pointing into RAM, otherwise pass '0' (no limit) |
965 | */ | |
d5fef92f PM |
966 | if (image_low_addr < info->loader_start) { |
967 | image_low_addr = 0; | |
92df8450 | 968 | } |
3b77f6c3 | 969 | info->dtb_start = info->loader_start; |
d5fef92f | 970 | info->dtb_limit = image_low_addr; |
92df8450 AB |
971 | } |
972 | } | |
1c7b3754 PB |
973 | entry = elf_entry; |
974 | if (kernel_size < 0) { | |
f831f955 NH |
975 | uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; |
976 | kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, | |
9f43d4c3 | 977 | &is_linux, NULL, NULL, as); |
67505c11 PM |
978 | if (kernel_size >= 0) { |
979 | image_low_addr = loadaddr; | |
980 | image_high_addr = image_low_addr + kernel_size; | |
981 | } | |
1c7b3754 | 982 | } |
6f5d3cbe | 983 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { |
68115ed5 | 984 | kernel_size = load_aarch64_image(info->kernel_filename, |
9f43d4c3 | 985 | info->loader_start, &entry, as); |
6f5d3cbe | 986 | is_linux = 1; |
67505c11 PM |
987 | if (kernel_size >= 0) { |
988 | image_low_addr = entry; | |
989 | image_high_addr = image_low_addr + kernel_size; | |
990 | } | |
68115ed5 AB |
991 | } else if (kernel_size < 0) { |
992 | /* 32-bit ARM */ | |
993 | entry = info->loader_start + KERNEL_LOAD_ADDR; | |
9f43d4c3 | 994 | kernel_size = load_image_targphys_as(info->kernel_filename, entry, |
e70af24b | 995 | ram_end - KERNEL_LOAD_ADDR, as); |
1c7b3754 | 996 | is_linux = 1; |
67505c11 PM |
997 | if (kernel_size >= 0) { |
998 | image_low_addr = entry; | |
999 | image_high_addr = image_low_addr + kernel_size; | |
1000 | } | |
1c7b3754 PB |
1001 | } |
1002 | if (kernel_size < 0) { | |
c0dbca36 | 1003 | error_report("could not load kernel '%s'", info->kernel_filename); |
1c7b3754 PB |
1004 | exit(1); |
1005 | } | |
852dc64d PM |
1006 | |
1007 | if (kernel_size > info->ram_size) { | |
1008 | error_report("kernel '%s' is too large to fit in RAM " | |
af975131 | 1009 | "(kernel size %zd, RAM size %" PRId64 ")", |
852dc64d PM |
1010 | info->kernel_filename, kernel_size, info->ram_size); |
1011 | exit(1); | |
1012 | } | |
1013 | ||
f2d74978 | 1014 | info->entry = entry; |
e6b2b20d PM |
1015 | |
1016 | /* | |
1017 | * We want to put the initrd far enough into RAM that when the | |
1018 | * kernel is uncompressed it will not clobber the initrd. However | |
1019 | * on boards without much RAM we must ensure that we still leave | |
1020 | * enough room for a decent sized initrd, and on boards with large | |
1021 | * amounts of RAM we must avoid the initrd being so far up in RAM | |
1022 | * that it is outside lowmem and inaccessible to the kernel. | |
1023 | * So for boards with less than 256MB of RAM we put the initrd | |
1024 | * halfway into RAM, and for boards with 256MB of RAM or more we put | |
1025 | * the initrd at 128MB. | |
1026 | * We also refuse to put the initrd somewhere that will definitely | |
1027 | * overlay the kernel we just loaded, though for kernel formats which | |
1028 | * don't tell us their exact size (eg self-decompressing 32-bit kernels) | |
1029 | * we might still make a bad choice here. | |
1030 | */ | |
1031 | info->initrd_start = info->loader_start + | |
e4e34855 | 1032 | MIN(info->ram_size / 2, 128 * MiB); |
67505c11 PM |
1033 | if (image_high_addr) { |
1034 | info->initrd_start = MAX(info->initrd_start, image_high_addr); | |
1035 | } | |
e6b2b20d PM |
1036 | info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); |
1037 | ||
f2d74978 | 1038 | if (is_linux) { |
47b1da81 PM |
1039 | uint32_t fixupcontext[FIXUP_MAX]; |
1040 | ||
f93eb9ff | 1041 | if (info->initrd_filename) { |
852dc64d PM |
1042 | |
1043 | if (info->initrd_start >= ram_end) { | |
1044 | error_report("not enough space after kernel to load initrd"); | |
1045 | exit(1); | |
1046 | } | |
1047 | ||
9f43d4c3 PM |
1048 | initrd_size = load_ramdisk_as(info->initrd_filename, |
1049 | info->initrd_start, | |
e70af24b | 1050 | ram_end - info->initrd_start, as); |
fd76663e | 1051 | if (initrd_size < 0) { |
9f43d4c3 PM |
1052 | initrd_size = load_image_targphys_as(info->initrd_filename, |
1053 | info->initrd_start, | |
e70af24b | 1054 | ram_end - |
9f43d4c3 PM |
1055 | info->initrd_start, |
1056 | as); | |
fd76663e | 1057 | } |
daf90626 | 1058 | if (initrd_size < 0) { |
c0dbca36 AF |
1059 | error_report("could not load initrd '%s'", |
1060 | info->initrd_filename); | |
daf90626 PB |
1061 | exit(1); |
1062 | } | |
b48b0640 | 1063 | if (info->initrd_start + initrd_size > ram_end) { |
852dc64d PM |
1064 | error_report("could not load initrd '%s': " |
1065 | "too big to fit into RAM after the kernel", | |
1066 | info->initrd_filename); | |
b48b0640 | 1067 | exit(1); |
852dc64d | 1068 | } |
daf90626 PB |
1069 | } else { |
1070 | initrd_size = 0; | |
1071 | } | |
412beee6 GL |
1072 | info->initrd_size = initrd_size; |
1073 | ||
47b1da81 | 1074 | fixupcontext[FIXUP_BOARDID] = info->board_id; |
10b8ec73 | 1075 | fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; |
412beee6 | 1076 | |
c3a42358 PM |
1077 | /* |
1078 | * for device tree boot, we pass the DTB directly in r2. Otherwise | |
412beee6 GL |
1079 | * we point to the kernel args. |
1080 | */ | |
83bfffec | 1081 | if (have_dtb(info)) { |
76e2aef3 | 1082 | hwaddr align; |
76e2aef3 AG |
1083 | |
1084 | if (elf_machine == EM_AARCH64) { | |
1085 | /* | |
1086 | * Some AArch64 kernels on early bootup map the fdt region as | |
1087 | * | |
1088 | * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] | |
1089 | * | |
1090 | * Let's play safe and prealign it to 2MB to give us some space. | |
1091 | */ | |
e4e34855 | 1092 | align = 2 * MiB; |
76e2aef3 AG |
1093 | } else { |
1094 | /* | |
1095 | * Some 32bit kernels will trash anything in the 4K page the | |
1096 | * initrd ends in, so make sure the DTB isn't caught up in that. | |
1097 | */ | |
e4e34855 | 1098 | align = 4 * KiB; |
76e2aef3 AG |
1099 | } |
1100 | ||
1101 | /* Place the DTB after the initrd in memory with alignment. */ | |
3b77f6c3 IM |
1102 | info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, |
1103 | align); | |
852dc64d PM |
1104 | if (info->dtb_start >= ram_end) { |
1105 | error_report("Not enough space for DTB after kernel/initrd"); | |
1106 | exit(1); | |
1107 | } | |
751ebc13 RPB |
1108 | fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; |
1109 | fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; | |
412beee6 | 1110 | } else { |
751ebc13 RPB |
1111 | fixupcontext[FIXUP_ARGPTR_LO] = |
1112 | info->loader_start + KERNEL_ARGS_ADDR; | |
1113 | fixupcontext[FIXUP_ARGPTR_HI] = | |
1114 | (info->loader_start + KERNEL_ARGS_ADDR) >> 32; | |
e4e34855 | 1115 | if (info->ram_size >= 4 * GiB) { |
c0dbca36 AF |
1116 | error_report("RAM size must be less than 4GB to boot" |
1117 | " Linux kernel using ATAGS (try passing a device tree" | |
1118 | " using -dtb)"); | |
3871481c PM |
1119 | exit(1); |
1120 | } | |
412beee6 | 1121 | } |
751ebc13 RPB |
1122 | fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; |
1123 | fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; | |
47b1da81 | 1124 | |
0fe43f0a CLG |
1125 | arm_write_bootloader("bootloader", as, info->loader_start, |
1126 | primary_loader, fixupcontext); | |
47b1da81 | 1127 | |
10b8ec73 PC |
1128 | if (info->write_board_setup) { |
1129 | info->write_board_setup(cpu, info); | |
1130 | } | |
d8b1ae42 | 1131 | |
c3a42358 PM |
1132 | /* |
1133 | * Notify devices which need to fake up firmware initialization | |
d8b1ae42 PM |
1134 | * that we're doing a direct kernel boot. |
1135 | */ | |
1136 | object_child_foreach_recursive(object_get_root(), | |
1137 | do_arm_linux_init, info); | |
16406950 | 1138 | } |
f2d74978 | 1139 | info->is_linux = is_linux; |
6ed221b6 | 1140 | |
0c949276 | 1141 | for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { |
c6faa758 | 1142 | ARM_CPU(cs)->env.boot_info = info; |
6ed221b6 | 1143 | } |
d33774ee PM |
1144 | } |
1145 | ||
4c0f2687 PM |
1146 | static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) |
1147 | { | |
1148 | /* Set up for booting firmware (which might load a kernel via fw_cfg) */ | |
1149 | ||
1150 | if (have_dtb(info)) { | |
1151 | /* | |
1152 | * If we have a device tree blob, but no kernel to supply it to (or | |
1153 | * the kernel is supposed to be loaded by the bootloader), copy the | |
1154 | * DTB to the base of RAM for the bootloader to pick up. | |
1155 | */ | |
1156 | info->dtb_start = info->loader_start; | |
1157 | } | |
1158 | ||
1159 | if (info->kernel_filename) { | |
1160 | FWCfgState *fw_cfg; | |
1161 | bool try_decompressing_kernel; | |
1162 | ||
1163 | fw_cfg = fw_cfg_find(); | |
dae25739 PM |
1164 | |
1165 | if (!fw_cfg) { | |
1166 | error_report("This machine type does not support loading both " | |
1167 | "a guest firmware/BIOS image and a guest kernel at " | |
1168 | "the same time. You should change your QEMU command " | |
1169 | "line to specify one or the other, but not both."); | |
1170 | exit(1); | |
1171 | } | |
1172 | ||
4c0f2687 PM |
1173 | try_decompressing_kernel = arm_feature(&cpu->env, |
1174 | ARM_FEATURE_AARCH64); | |
1175 | ||
1176 | /* | |
1177 | * Expose the kernel, the command line, and the initrd in fw_cfg. | |
1178 | * We don't process them here at all, it's all left to the | |
1179 | * firmware. | |
1180 | */ | |
1181 | load_image_to_fw_cfg(fw_cfg, | |
1182 | FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | |
1183 | info->kernel_filename, | |
1184 | try_decompressing_kernel); | |
1185 | load_image_to_fw_cfg(fw_cfg, | |
1186 | FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | |
1187 | info->initrd_filename, false); | |
1188 | ||
1189 | if (info->kernel_cmdline) { | |
1190 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
1191 | strlen(info->kernel_cmdline) + 1); | |
1192 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
1193 | info->kernel_cmdline); | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | /* | |
1198 | * We will start from address 0 (typically a boot ROM image) in the | |
2a5bdfc8 PM |
1199 | * same way as hardware. Leave env->boot_info NULL, so that |
1200 | * do_cpu_reset() knows it does not need to alter the PC on reset. | |
4c0f2687 PM |
1201 | */ |
1202 | } | |
1203 | ||
2744ece8 | 1204 | void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) |
d33774ee PM |
1205 | { |
1206 | CPUState *cs; | |
1207 | AddressSpace *as = arm_boot_address_space(cpu, info); | |
817e2db8 PM |
1208 | int boot_el; |
1209 | CPUARMState *env = &cpu->env; | |
d6dc926e | 1210 | int nb_cpus = 0; |
d33774ee PM |
1211 | |
1212 | /* | |
1213 | * CPU objects (unlike devices) are not automatically reset on system | |
1214 | * reset, so we must always register a handler to do so. If we're | |
1215 | * actually loading a kernel, the handler is also responsible for | |
1216 | * arranging that we start it correctly. | |
1217 | */ | |
1218 | for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | |
1219 | qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); | |
d6dc926e | 1220 | nb_cpus++; |
d33774ee PM |
1221 | } |
1222 | ||
1223 | /* | |
1224 | * The board code is not supposed to set secure_board_setup unless | |
1225 | * running its code in secure mode is actually possible, and KVM | |
1226 | * doesn't support secure. | |
1227 | */ | |
1228 | assert(!(info->secure_board_setup && kvm_enabled())); | |
2744ece8 TX |
1229 | info->kernel_filename = ms->kernel_filename; |
1230 | info->kernel_cmdline = ms->kernel_cmdline; | |
1231 | info->initrd_filename = ms->initrd_filename; | |
f2ce39b4 | 1232 | info->dtb_filename = ms->dtb; |
d33774ee PM |
1233 | info->dtb_limit = 0; |
1234 | ||
1235 | /* Load the kernel. */ | |
1236 | if (!info->kernel_filename || info->firmware_loaded) { | |
4c0f2687 | 1237 | arm_setup_firmware_boot(cpu, info); |
d33774ee PM |
1238 | } else { |
1239 | arm_setup_direct_kernel_boot(cpu, info); | |
1240 | } | |
63a183ed | 1241 | |
817e2db8 PM |
1242 | /* |
1243 | * Disable the PSCI conduit if it is set up to target the same | |
1244 | * or a lower EL than the one we're going to start the guest code in. | |
1245 | * This logic needs to agree with the code in do_cpu_reset() which | |
1246 | * decides whether we're going to boot the guest in the highest | |
1247 | * supported exception level or in a lower one. | |
1248 | */ | |
1249 | ||
dc888dd4 PM |
1250 | /* |
1251 | * If PSCI is enabled, then SMC calls all go to the PSCI handler and | |
1252 | * are never emulated to trap into guest code. It therefore does not | |
1253 | * make sense for the board to have a setup code fragment that runs | |
1254 | * in Secure, because this will probably need to itself issue an SMC of some | |
1255 | * kind as part of its operation. | |
1256 | */ | |
1257 | assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || | |
1258 | !info->secure_board_setup); | |
1259 | ||
817e2db8 PM |
1260 | /* Boot into highest supported EL ... */ |
1261 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1262 | boot_el = 3; | |
1263 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
1264 | boot_el = 2; | |
1265 | } else { | |
1266 | boot_el = 1; | |
1267 | } | |
1268 | /* ...except that if we're booting Linux we adjust the EL we boot into */ | |
1269 | if (info->is_linux && !info->secure_boot) { | |
1270 | boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; | |
1271 | } | |
1272 | ||
1273 | if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || | |
1274 | (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { | |
1275 | info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | |
1276 | } | |
1277 | ||
1278 | if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { | |
1279 | for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | |
1280 | Object *cpuobj = OBJECT(cs); | |
1281 | ||
1282 | object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, | |
1283 | &error_abort); | |
1284 | /* | |
1285 | * Secondary CPUs start in PSCI powered-down state. Like the | |
1286 | * code in do_cpu_reset(), we assume first_cpu is the primary | |
1287 | * CPU. | |
1288 | */ | |
1289 | if (cs != first_cpu) { | |
1290 | object_property_set_bool(cpuobj, "start-powered-off", true, | |
1291 | &error_abort); | |
1292 | } | |
1293 | } | |
1294 | } | |
1295 | ||
d4a29ed6 | 1296 | if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && |
d6dc926e | 1297 | info->is_linux && nb_cpus > 1) { |
d4a29ed6 PM |
1298 | /* |
1299 | * We're booting Linux but not using PSCI, so for SMP we need | |
1300 | * to write a custom secondary CPU boot loader stub, and arrange | |
1301 | * for the secondary CPU reset to make the accompanying initialization. | |
1302 | */ | |
1303 | if (!info->secondary_cpu_reset_hook) { | |
1304 | info->secondary_cpu_reset_hook = default_reset_secondary; | |
1305 | } | |
1306 | if (!info->write_secondary_boot) { | |
1307 | info->write_secondary_boot = default_write_secondary; | |
1308 | } | |
1309 | info->write_secondary_boot(cpu, info); | |
1310 | } else { | |
1311 | /* | |
1312 | * No secondary boot stub; don't use the reset hook that would | |
1313 | * have set the CPU up to call it | |
1314 | */ | |
1315 | info->write_secondary_boot = NULL; | |
1316 | info->secondary_cpu_reset_hook = NULL; | |
1317 | } | |
1318 | ||
817e2db8 PM |
1319 | /* |
1320 | * arm_load_dtb() may add a PSCI node so it must be called after we have | |
1321 | * decided whether to enable PSCI and set the psci-conduit CPU properties. | |
1322 | */ | |
3b77f6c3 | 1323 | if (!info->skip_dtb_autoload && have_dtb(info)) { |
2744ece8 | 1324 | if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { |
3b77f6c3 IM |
1325 | exit(1); |
1326 | } | |
1327 | } | |
ac9d32e3 | 1328 | } |
d8b1ae42 PM |
1329 | |
1330 | static const TypeInfo arm_linux_boot_if_info = { | |
1331 | .name = TYPE_ARM_LINUX_BOOT_IF, | |
1332 | .parent = TYPE_INTERFACE, | |
1333 | .class_size = sizeof(ARMLinuxBootIfClass), | |
1334 | }; | |
1335 | ||
1336 | static void arm_linux_boot_register_types(void) | |
1337 | { | |
1338 | type_register_static(&arm_linux_boot_if_info); | |
1339 | } | |
1340 | ||
1341 | type_init(arm_linux_boot_register_types) |