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hw/arm/exynos4210: Put external GIC into state struct
[mirror_qemu.git] / hw / arm / exynos4210.c
CommitLineData
0caa7113
EV		 1/*
2 * Samsung exynos4210 SoC emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
5 * Maksim Kozlov <m.kozlov@samsung.com>
6 * Evgeny Voevodin <e.voevodin@samsung.com>
7 * Igor Mitsyanko <i.mitsyanko@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
12b16722 24#include "qemu/osdep.h"
da34e65c 25#include "qapi/error.h"
4771d756 26#include "cpu.h"
9e883790 27#include "hw/cpu/a9mpcore.h"
64552b6b 28#include "hw/irq.h"
12e9493d 29#include "sysemu/blockdev.h"
9c17d615 30#include "sysemu/sysemu.h"
83c9f4ca 31#include "hw/sysbus.h"
12ec8bd5 32#include "hw/arm/boot.h"
83c9f4ca 33#include "hw/loader.h"
a27bd6c7 34#include "hw/qdev-properties.h"
0d09e41a 35#include "hw/arm/exynos4210.h"
c2de81e2 36#include "hw/sd/sdhci.h"
83c9f4ca 37#include "hw/usb/hcd-ehci.h"
0caa7113
EV		 38
39#define EXYNOS4210_CHIPID_ADDR 0x10000000
40
62db8bf3
EV		 41/* PWM */
42#define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
43
7bdf43a7
OO		 44/* RTC */
45#define EXYNOS4210_RTC_BASE_ADDR 0x10070000
46
12c775db
EV		 47/* MCT */
48#define EXYNOS4210_MCT_BASE_ADDR 0x10050000
49
ffbbe7d0
MI		 50/* I2C */
51#define EXYNOS4210_I2C_SHIFT 0x00010000
52#define EXYNOS4210_I2C_BASE_ADDR 0x13860000
53/* Interrupt Group of External Interrupt Combiner for I2C */
54#define EXYNOS4210_I2C_INTG 27
55#define EXYNOS4210_HDMI_INTG 16
56
e5a4914e
MK		 57/* UART's definitions */
58#define EXYNOS4210_UART0_BASE_ADDR 0x13800000
59#define EXYNOS4210_UART1_BASE_ADDR 0x13810000
60#define EXYNOS4210_UART2_BASE_ADDR 0x13820000
61#define EXYNOS4210_UART3_BASE_ADDR 0x13830000
62#define EXYNOS4210_UART0_FIFO_SIZE 256
63#define EXYNOS4210_UART1_FIFO_SIZE 64
64#define EXYNOS4210_UART2_FIFO_SIZE 16
65#define EXYNOS4210_UART3_FIFO_SIZE 16
66/* Interrupt Group of External Interrupt Combiner for UART */
67#define EXYNOS4210_UART_INT_GRP 26
68
0caa7113
EV		 69/* External GIC */
70#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000
71#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000
72
73/* Combiner */
74#define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000
75#define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000
76
d77b71c2
KK		 77/* SD/MMC host controllers */
78#define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080
79#define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000
80#define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \
81 0x00010000 * (n))
82#define EXYNOS4210_SDHCI_NUMBER 4
83
df91b48f
MK		 84/* PMU SFR base address */
85#define EXYNOS4210_PMU_BASE_ADDR 0x10020000
86
1e0228fd
KK		 87/* Clock controller SFR base address */
88#define EXYNOS4210_CLK_BASE_ADDR 0x10030000
89
499ca137
KK		 90/* PRNG/HASH SFR base address */
91#define EXYNOS4210_RNG_BASE_ADDR 0x10830400
92
30628cb1
MI		 93/* Display controllers (FIMD) */
94#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000
95
358d615b
LW		 96/* EHCI */
97#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
98
59520dc6
GR		 99/* DMA */
100#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
101#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
102#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
103
93afe073
PM		 104enum ExtGicId {
105 EXT_GIC_ID_MDMA_LCD0 = 66,
106 EXT_GIC_ID_PDMA0,
107 EXT_GIC_ID_PDMA1,
108 EXT_GIC_ID_TIMER0,
109 EXT_GIC_ID_TIMER1,
110 EXT_GIC_ID_TIMER2,
111 EXT_GIC_ID_TIMER3,
112 EXT_GIC_ID_TIMER4,
113 EXT_GIC_ID_MCT_L0,
114 EXT_GIC_ID_WDT,
115 EXT_GIC_ID_RTC_ALARM,
116 EXT_GIC_ID_RTC_TIC,
117 EXT_GIC_ID_GPIO_XB,
118 EXT_GIC_ID_GPIO_XA,
119 EXT_GIC_ID_MCT_L1,
120 EXT_GIC_ID_IEM_APC,
121 EXT_GIC_ID_IEM_IEC,
122 EXT_GIC_ID_NFC,
123 EXT_GIC_ID_UART0,
124 EXT_GIC_ID_UART1,
125 EXT_GIC_ID_UART2,
126 EXT_GIC_ID_UART3,
127 EXT_GIC_ID_UART4,
128 EXT_GIC_ID_MCT_G0,
129 EXT_GIC_ID_I2C0,
130 EXT_GIC_ID_I2C1,
131 EXT_GIC_ID_I2C2,
132 EXT_GIC_ID_I2C3,
133 EXT_GIC_ID_I2C4,
134 EXT_GIC_ID_I2C5,
135 EXT_GIC_ID_I2C6,
136 EXT_GIC_ID_I2C7,
137 EXT_GIC_ID_SPI0,
138 EXT_GIC_ID_SPI1,
139 EXT_GIC_ID_SPI2,
140 EXT_GIC_ID_MCT_G1,
141 EXT_GIC_ID_USB_HOST,
142 EXT_GIC_ID_USB_DEVICE,
143 EXT_GIC_ID_MODEMIF,
144 EXT_GIC_ID_HSMMC0,
145 EXT_GIC_ID_HSMMC1,
146 EXT_GIC_ID_HSMMC2,
147 EXT_GIC_ID_HSMMC3,
148 EXT_GIC_ID_SDMMC,
149 EXT_GIC_ID_MIPI_CSI_4LANE,
150 EXT_GIC_ID_MIPI_DSI_4LANE,
151 EXT_GIC_ID_MIPI_CSI_2LANE,
152 EXT_GIC_ID_MIPI_DSI_2LANE,
153 EXT_GIC_ID_ONENAND_AUDI,
154 EXT_GIC_ID_ROTATOR,
155 EXT_GIC_ID_FIMC0,
156 EXT_GIC_ID_FIMC1,
157 EXT_GIC_ID_FIMC2,
158 EXT_GIC_ID_FIMC3,
159 EXT_GIC_ID_JPEG,
160 EXT_GIC_ID_2D,
161 EXT_GIC_ID_PCIe,
162 EXT_GIC_ID_MIXER,
163 EXT_GIC_ID_HDMI,
164 EXT_GIC_ID_HDMI_I2C,
165 EXT_GIC_ID_MFC,
166 EXT_GIC_ID_TVENC,
167};
168
169enum ExtInt {
170 EXT_GIC_ID_EXTINT0 = 48,
171 EXT_GIC_ID_EXTINT1,
172 EXT_GIC_ID_EXTINT2,
173 EXT_GIC_ID_EXTINT3,
174 EXT_GIC_ID_EXTINT4,
175 EXT_GIC_ID_EXTINT5,
176 EXT_GIC_ID_EXTINT6,
177 EXT_GIC_ID_EXTINT7,
178 EXT_GIC_ID_EXTINT8,
179 EXT_GIC_ID_EXTINT9,
180 EXT_GIC_ID_EXTINT10,
181 EXT_GIC_ID_EXTINT11,
182 EXT_GIC_ID_EXTINT12,
183 EXT_GIC_ID_EXTINT13,
184 EXT_GIC_ID_EXTINT14,
185 EXT_GIC_ID_EXTINT15
186};
187
188/*
189 * External GIC sources which are not from External Interrupt Combiner or
190 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
191 * which is INTG16 in Internal Interrupt Combiner.
192 */
193
194static const uint32_t
195combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
196 /* int combiner groups 16-19 */
197 { }, { }, { }, { },
198 /* int combiner group 20 */
199 { 0, EXT_GIC_ID_MDMA_LCD0 },
200 /* int combiner group 21 */
201 { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
202 /* int combiner group 22 */
203 { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
204 EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
205 /* int combiner group 23 */
206 { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
207 /* int combiner group 24 */
208 { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
209 /* int combiner group 25 */
210 { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
211 /* int combiner group 26 */
212 { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
213 EXT_GIC_ID_UART4 },
214 /* int combiner group 27 */
215 { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
216 EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
217 EXT_GIC_ID_I2C7 },
218 /* int combiner group 28 */
219 { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
220 /* int combiner group 29 */
221 { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
222 EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
223 /* int combiner group 30 */
224 { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
225 /* int combiner group 31 */
226 { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
227 /* int combiner group 32 */
228 { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
229 /* int combiner group 33 */
230 { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
231 /* int combiner group 34 */
232 { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
233 /* int combiner group 35 */
234 { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
235 /* int combiner group 36 */
236 { EXT_GIC_ID_MIXER },
237 /* int combiner group 37 */
238 { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
239 EXT_GIC_ID_EXTINT7 },
240 /* groups 38-50 */
241 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
242 /* int combiner group 51 */
243 { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
244 /* group 52 */
245 { },
246 /* int combiner group 53 */
247 { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
248 /* groups 54-63 */
249 { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
250};
251
252/*
253 * Initialize board IRQs.
254 * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
255 */
256static void exynos4210_init_board_irqs(Exynos4210State *s)
257{
258 uint32_t grp, bit, irq_id, n;
259 Exynos4210Irq *is = &s->irqs;
260
261 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
262 irq_id = 0;
263 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
264 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
265 /* MCT_G0 is passed to External GIC */
266 irq_id = EXT_GIC_ID_MCT_G0;
267 }
268 if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
269 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
270 /* MCT_G1 is passed to External and GIC */
271 irq_id = EXT_GIC_ID_MCT_G1;
272 }
273 if (irq_id) {
274 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
275 is->ext_gic_irq[irq_id - 32]);
276 } else {
277 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
278 is->ext_combiner_irq[n]);
279 }
280 }
281 for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
282 /* these IDs are passed to Internal Combiner and External GIC */
283 grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
284 bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
285 irq_id = combiner_grp_to_gic_id[grp -
286 EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
287
288 if (irq_id) {
289 s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
290 is->ext_gic_irq[irq_id - 32]);
291 }
292 }
293}
294
295/*
296 * Get IRQ number from exynos4210 IRQ subsystem stub.
297 * To identify IRQ source use internal combiner group and bit number
298 * grp - group number
299 * bit - bit number inside group
300 */
301uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
302{
303 return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
304}
305
0caa7113
EV		 306static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
307 0x09, 0x00, 0x00, 0x00 };
308
11a5e482
IM		 309static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
310 unsigned size)
311{
312 assert(offset < sizeof(chipid_and_omr));
313 return chipid_and_omr[offset];
314}
315
316static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
317 uint64_t value, unsigned size)
318{
319 return;
320}
321
322static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
323 .read = exynos4210_chipid_and_omr_read,
324 .write = exynos4210_chipid_and_omr_write,
325 .endianness = DEVICE_NATIVE_ENDIAN,
326 .impl = {
327 .max_access_size = 1,
328 }
329};
330
9543b0cd 331void exynos4210_write_secondary(ARMCPU *cpu,
3f088e36
EV		 332 const struct arm_boot_info *info)
333{
334 int n;
335 uint32_t smpboot[] = {
bf471f79
PM		 336 0xe59f3034, /* ldr r3, External gic_cpu_if */
337 0xe59f2034, /* ldr r2, Internal gic_cpu_if */
338 0xe59f0034, /* ldr r0, startaddr */
3f088e36
EV		 339 0xe3a01001, /* mov r1, #1 */
340 0xe5821000, /* str r1, [r2] */
341 0xe5831000, /* str r1, [r3] */
bf471f79
PM		 342 0xe3a010ff, /* mov r1, #0xff */
343 0xe5821004, /* str r1, [r2, #4] */
344 0xe5831004, /* str r1, [r3, #4] */
345 0xf57ff04f, /* dsb */
3f088e36
EV		 346 0xe320f003, /* wfi */
347 0xe5901000, /* ldr r1, [r0] */
348 0xe1110001, /* tst r1, r1 */
349 0x0afffffb, /* beq <wfi> */
350 0xe12fff11, /* bx r1 */
351 EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
352 0, /* gic_cpu_if: base address of Internal GIC CPU interface */
353 0 /* bootreg: Boot register address is held here */
354 };
355 smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
356 smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
357 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
358 smpboot[n] = tswap32(smpboot[n]);
359 }
360 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
361 info->smp_loader_start);
362}
363
f3a6339a
KK		 364static uint64_t exynos4210_calc_affinity(int cpu)
365{
f3a6339a 366 /* Exynos4210 has 0x9 as cluster ID */
4a4ff4c5 367 return (0x9 << ARM_AFF1_SHIFT) | cpu;
f3a6339a
KK		 368}
369
e9d20b55
GR		 370static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
371 qemu_irq irq, int nreq, int nevents, int width)
59520dc6
GR		 372{
373 SysBusDevice *busdev;
374 DeviceState *dev;
dab15fbe 375 int i;
59520dc6 376
3e80f690 377 dev = qdev_new("pl330");
77844cc5
WJ		 378 object_property_set_link(OBJECT(dev), "memory",
379 OBJECT(get_system_memory()),
380 &error_fatal);
dab15fbe
GR		 381 qdev_prop_set_uint8(dev, "num_events", nevents);
382 qdev_prop_set_uint8(dev, "num_chnls", 8);
59520dc6 383 qdev_prop_set_uint8(dev, "num_periph_req", nreq);
dab15fbe
GR		 384
385 qdev_prop_set_uint8(dev, "wr_cap", 4);
386 qdev_prop_set_uint8(dev, "wr_q_dep", 8);
387 qdev_prop_set_uint8(dev, "rd_cap", 4);
388 qdev_prop_set_uint8(dev, "rd_q_dep", 8);
389 qdev_prop_set_uint8(dev, "data_width", width);
390 qdev_prop_set_uint16(dev, "data_buffer_dep", width);
59520dc6 391 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 392 sysbus_realize_and_unref(busdev, &error_fatal);
59520dc6 393 sysbus_mmio_map(busdev, 0, base);
dab15fbe 394
5325cc34 395 object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1,
dab15fbe 396 &error_abort);
ce189ab2 397 qdev_realize(DEVICE(orgate), NULL, &error_abort);
dab15fbe
GR		 398
399 for (i = 0; i < nevents + 1; i++) {
400 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));
401 }
402 qdev_connect_gpio_out(DEVICE(orgate), 0, irq);
e9d20b55 403 return dev;
59520dc6
GR		 404}
405
98e4f4fd 406static void exynos4210_realize(DeviceState *socdev, Error **errp)
0caa7113 407{
98e4f4fd
PMD		 408 Exynos4210State *s = EXYNOS4210_SOC(socdev);
409 MemoryRegion *system_mem = get_system_memory();
0caa7113 410 SysBusDevice *busdev;
e9d20b55 411 DeviceState *dev, *uart[4], *pl330[3];
310150c0 412 int i, n;
4719ab91 413
0caa7113 414 for (n = 0; n < EXYNOS4210_NCPUS; n++) {
ba1ba5cc 415 Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
4719ab91 416
61e2f352
GB		 417 /* By default A9 CPUs have EL3 enabled. This board does not currently
418 * support EL3 so the CPU EL3 property is disabled before realization.
419 */
efba1595 420 if (object_property_find(cpuobj, "has_el3")) {
5325cc34 421 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
61e2f352
GB		 422 }
423
4719ab91 424 s->cpu[n] = ARM_CPU(cpuobj);
5325cc34
MA		 425 object_property_set_int(cpuobj, "mp-affinity",
426 exynos4210_calc_affinity(n), &error_abort);
427 object_property_set_int(cpuobj, "reset-cbar",
428 EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
429 &error_abort);
ce189ab2 430 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
0caa7113
EV		 431 }
432
0caa7113 433 /* IRQ Gate */
61558e7a 434 for (i = 0; i < EXYNOS4210_NCPUS; i++) {
2bd84b68
PM		 435 DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
436 object_property_set_int(OBJECT(orgate), "num-lines",
437 EXYNOS4210_IRQ_GATE_NINPUTS,
438 &error_abort);
439 qdev_realize(orgate, NULL, &error_abort);
440 qdev_connect_gpio_out(orgate, 0,
441 qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
0caa7113
EV		 442 }
443
444 /* Private memory region and Internal GIC */
5b241728
PM		 445 qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
446 busdev = SYS_BUS_DEVICE(&s->a9mpcore);
447 sysbus_realize(busdev, &error_fatal);
0caa7113
EV		 448 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
449 for (n = 0; n < EXYNOS4210_NCPUS; n++) {
2bd84b68
PM		 450 sysbus_connect_irq(busdev, n,
451 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
0caa7113 452 }
0caa7113
EV		 453
454 /* Cache controller */
455 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
456
457 /* External GIC */
78cb12a9
PM		 458 qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
459 busdev = SYS_BUS_DEVICE(&s->ext_gic);
460 sysbus_realize(busdev, &error_fatal);
0caa7113
EV		 461 /* Map CPU interface */
462 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
463 /* Map Distributer interface */
464 sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
465 for (n = 0; n < EXYNOS4210_NCPUS; n++) {
2bd84b68
PM		 466 sysbus_connect_irq(busdev, n,
467 qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
0caa7113
EV		 468 }
469 for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
78cb12a9 470 s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
0caa7113
EV		 471 }
472
473 /* Internal Interrupt Combiner */
3e80f690 474 dev = qdev_new("exynos4210.combiner");
1356b98d 475 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 476 sysbus_realize_and_unref(busdev, &error_fatal);
0caa7113 477 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
c9d4940a
PM		 478 sysbus_connect_irq(busdev, n,
479 qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
0caa7113
EV		 480 }
481 exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
482 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
483
484 /* External Interrupt Combiner */
3e80f690 485 dev = qdev_new("exynos4210.combiner");
0caa7113 486 qdev_prop_set_uint32(dev, "external", 1);
1356b98d 487 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 488 sysbus_realize_and_unref(busdev, &error_fatal);
0caa7113
EV		 489 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
490 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
491 }
492 exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
493 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
494
495 /* Initialize board IRQs. */
771dee52 496 exynos4210_init_board_irqs(s);
0caa7113
EV		 497
498 /*** Memory ***/
499
500 /* Chip-ID and OMR */
32b9523a
PMD		 501 memory_region_init_io(&s->chipid_mem, OBJECT(socdev),
502 &exynos4210_chipid_and_omr_ops, NULL,
503 "exynos4210.chipid", sizeof(chipid_and_omr));
0caa7113
EV		 504 memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
505 &s->chipid_mem);
506
507 /* Internal ROM */
32b9523a 508 memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom",
f8ed85ac 509 EXYNOS4210_IROM_SIZE, &error_fatal);
0caa7113
EV		 510 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
511 &s->irom_mem);
512 /* mirror of iROM */
32b9523a
PMD		 513 memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev),
514 "exynos4210.irom_alias", &s->irom_mem, 0,
0caa7113 515 EXYNOS4210_IROM_SIZE);
0caa7113
EV		 516 memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
517 &s->irom_alias_mem);
518
519 /* Internal RAM */
98a99ce0 520 memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
f8ed85ac 521 EXYNOS4210_IRAM_SIZE, &error_fatal);
0caa7113
EV		 522 memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
523 &s->iram_mem);
524
df91b48f
MK		 525 /* PMU.
526 * The only reason of existence at the moment is that secondary CPU boot
527 * loader uses PMU INFORM5 register as a holding pen.
528 */
529 sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
530
1e0228fd 531 sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
499ca137 532 sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
1e0228fd 533
62db8bf3
EV		 534 /* PWM */
535 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
536 s->irq_table[exynos4210_get_irq(22, 0)],
537 s->irq_table[exynos4210_get_irq(22, 1)],
538 s->irq_table[exynos4210_get_irq(22, 2)],
539 s->irq_table[exynos4210_get_irq(22, 3)],
540 s->irq_table[exynos4210_get_irq(22, 4)],
541 NULL);
7bdf43a7
OO		 542 /* RTC */
543 sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
544 s->irq_table[exynos4210_get_irq(23, 0)],
545 s->irq_table[exynos4210_get_irq(23, 1)],
546 NULL);
62db8bf3 547
12c775db 548 /* Multi Core Timer */
3e80f690 549 dev = qdev_new("exynos4210.mct");
1356b98d 550 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 551 sysbus_realize_and_unref(busdev, &error_fatal);
12c775db
EV		 552 for (n = 0; n < 4; n++) {
553 /* Connect global timer interrupts to Combiner gpio_in */
554 sysbus_connect_irq(busdev, n,
555 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
556 }
557 /* Connect local timer interrupts to Combiner gpio_in */
558 sysbus_connect_irq(busdev, 4,
559 s->irq_table[exynos4210_get_irq(51, 0)]);
560 sysbus_connect_irq(busdev, 5,
561 s->irq_table[exynos4210_get_irq(35, 3)]);
562 sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
563
ffbbe7d0
MI		 564 /*** I2C ***/
565 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
566 uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
567 qemu_irq i2c_irq;
568
569 if (n < 8) {
570 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
571 } else {
572 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
573 }
574
3e80f690 575 dev = qdev_new("exynos4210.i2c");
1356b98d 576 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 577 sysbus_realize_and_unref(busdev, &error_fatal);
ffbbe7d0
MI		 578 sysbus_connect_irq(busdev, 0, i2c_irq);
579 sysbus_mmio_map(busdev, 0, addr);
a5c82852 580 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
ffbbe7d0
MI		 581 }
582
583
e5a4914e 584 /*** UARTs ***/
e9d20b55 585 uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
5561adf0 586 EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
e5a4914e
MK		 587 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
588
e9d20b55 589 uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
5561adf0 590 EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
e5a4914e
MK		 591 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
592
e9d20b55 593 uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
5561adf0 594 EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
e5a4914e
MK		 595 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
596
e9d20b55 597 uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
5561adf0 598 EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
e5a4914e
MK		 599 s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
600
d77b71c2
KK		 601 /*** SD/MMC host controllers ***/
602 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
603 DeviceState *carddev;
604 BlockBackend *blk;
605 DriveInfo *di;
606
2edb4434
PMD		 607 /* Compatible with:
608 * - SD Host Controller Specification Version 2.0
609 * - SDIO Specification Version 2.0
610 * - MMC Specification Version 4.3
611 * - SDMA
612 * - ADMA2
613 *
614 * As this part of the Exynos4210 is not publically available,
615 * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
616 * public datasheet which is very similar (implementing
617 * MMC Specification Version 4.0 being the only difference noted)
618 */
3e80f690 619 dev = qdev_new(TYPE_S3C_SDHCI);
3c675da5 620 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
d77b71c2
KK		 621
622 busdev = SYS_BUS_DEVICE(dev);
3c6ef471 623 sysbus_realize_and_unref(busdev, &error_fatal);
d77b71c2
KK		 624 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
625 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
626
627 di = drive_get(IF_SD, 0, n);
628 blk = di ? blk_by_legacy_dinfo(di) : NULL;
3e80f690 629 carddev = qdev_new(TYPE_SD_CARD);
934df912 630 qdev_prop_set_drive(carddev, "drive", blk);
3e80f690
MA		 631 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
632 &error_fatal);
d77b71c2
KK		 633 }
634
30628cb1
MI		 635 /*** Display controller (FIMD) ***/
636 sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
637 s->irq_table[exynos4210_get_irq(11, 0)],
638 s->irq_table[exynos4210_get_irq(11, 1)],
639 s->irq_table[exynos4210_get_irq(11, 2)],
640 NULL);
641
358d615b
LW		 642 sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
643 s->irq_table[exynos4210_get_irq(28, 3)]);
644
59520dc6 645 /*** DMA controllers ***/
e9d20b55
GR		 646 pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
647 &s->pl330_irq_orgate[0],
648 s->irq_table[exynos4210_get_irq(21, 0)],
649 32, 32, 32);
650 pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
651 &s->pl330_irq_orgate[1],
652 s->irq_table[exynos4210_get_irq(21, 1)],
653 32, 32, 32);
654 pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
655 &s->pl330_irq_orgate[2],
656 s->irq_table[exynos4210_get_irq(20, 1)],
657 1, 31, 64);
658
659 sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1,
660 qdev_get_gpio_in(pl330[0], 15));
661 sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1,
662 qdev_get_gpio_in(pl330[1], 15));
663 sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1,
664 qdev_get_gpio_in(pl330[0], 17));
665 sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1,
666 qdev_get_gpio_in(pl330[1], 17));
dab15fbe
GR		 667}
668
669static void exynos4210_init(Object *obj)
670{
671 Exynos4210State *s = EXYNOS4210_SOC(obj);
672 int i;
673
674 for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
675 char *name = g_strdup_printf("pl330-irq-orgate%d", i);
676 qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
677
9fc7fc4d 678 object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
dab15fbe
GR		 679 g_free(name);
680 }
2bd84b68
PM		 681
682 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
683 g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
684 object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
685 }
5b241728
PM		 686
687 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
78cb12a9 688 object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
98e4f4fd
PMD		 689}
690
691static void exynos4210_class_init(ObjectClass *klass, void *data)
692{
693 DeviceClass *dc = DEVICE_CLASS(klass);
59520dc6 694
98e4f4fd 695 dc->realize = exynos4210_realize;
0caa7113 696}
98e4f4fd
PMD		 697
698static const TypeInfo exynos4210_info = {
699 .name = TYPE_EXYNOS4210_SOC,
700 .parent = TYPE_SYS_BUS_DEVICE,
701 .instance_size = sizeof(Exynos4210State),
dab15fbe 702 .instance_init = exynos4210_init,
98e4f4fd
PMD		 703 .class_init = exynos4210_class_init,
704};
705
706static void exynos4210_register_types(void)
707{
708 type_register_static(&exynos4210_info);
709}
710
711type_init(exynos4210_register_types)
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