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ee708c99 JCD |
1 | /* |
2 | * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> | |
3 | * | |
4 | * i.MX25 SOC emulation. | |
5 | * | |
6 | * Based on hw/arm/xlnx-zynqmp.c | |
7 | * | |
8 | * Copyright (C) 2015 Xilinx Inc | |
9 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
19 | * for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
12b16722 | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 | 27 | #include "cpu.h" |
ee708c99 JCD |
28 | #include "hw/arm/fsl-imx25.h" |
29 | #include "sysemu/sysemu.h" | |
30 | #include "exec/address-spaces.h" | |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
8228e353 | 32 | #include "chardev/char.h" |
ee708c99 | 33 | |
bfae1772 GR |
34 | #define IMX25_ESDHC_CAPABILITIES 0x07e20000 |
35 | ||
ee708c99 JCD |
36 | static void fsl_imx25_init(Object *obj) |
37 | { | |
38 | FslIMX25State *s = FSL_IMX25(obj); | |
39 | int i; | |
40 | ||
eaa9a878 PMD |
41 | object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), |
42 | ARM_CPU_TYPE_NAME("arm926"), | |
43 | &error_abort, NULL); | |
ee708c99 | 44 | |
51dd12ac TH |
45 | sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), |
46 | TYPE_IMX_AVIC); | |
ee708c99 | 47 | |
51dd12ac | 48 | sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM); |
ee708c99 JCD |
49 | |
50 | for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { | |
51dd12ac TH |
51 | sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]), |
52 | TYPE_IMX_SERIAL); | |
ee708c99 JCD |
53 | } |
54 | ||
55 | for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { | |
51dd12ac TH |
56 | sysbus_init_child_obj(obj, "gpt[*]", &s->gpt[i], sizeof(s->gpt[i]), |
57 | TYPE_IMX25_GPT); | |
ee708c99 JCD |
58 | } |
59 | ||
60 | for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { | |
51dd12ac TH |
61 | sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]), |
62 | TYPE_IMX_EPIT); | |
ee708c99 JCD |
63 | } |
64 | ||
51dd12ac | 65 | sysbus_init_child_obj(obj, "fec", &s->fec, sizeof(s->fec), TYPE_IMX_FEC); |
ee708c99 | 66 | |
f0396549 MK |
67 | sysbus_init_child_obj(obj, "rngc", &s->rngc, sizeof(s->rngc), |
68 | TYPE_IMX_RNGC); | |
69 | ||
ee708c99 | 70 | for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { |
51dd12ac TH |
71 | sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]), |
72 | TYPE_IMX_I2C); | |
ee708c99 | 73 | } |
6abc7158 JCD |
74 | |
75 | for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { | |
51dd12ac TH |
76 | sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), |
77 | TYPE_IMX_GPIO); | |
6abc7158 | 78 | } |
bfae1772 GR |
79 | |
80 | for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { | |
81 | sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]), | |
82 | TYPE_IMX_USDHC); | |
83 | } | |
67f52ebe GR |
84 | |
85 | for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { | |
86 | sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]), | |
87 | TYPE_CHIPIDEA); | |
88 | } | |
89 | ||
4f0aff00 | 90 | sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT); |
ee708c99 JCD |
91 | } |
92 | ||
93 | static void fsl_imx25_realize(DeviceState *dev, Error **errp) | |
94 | { | |
95 | FslIMX25State *s = FSL_IMX25(dev); | |
96 | uint8_t i; | |
97 | Error *err = NULL; | |
98 | ||
99 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | |
100 | if (err) { | |
101 | error_propagate(errp, err); | |
102 | return; | |
103 | } | |
104 | ||
105 | object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); | |
106 | if (err) { | |
107 | error_propagate(errp, err); | |
108 | return; | |
109 | } | |
110 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); | |
111 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, | |
112 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); | |
113 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, | |
114 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); | |
115 | ||
116 | object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); | |
117 | if (err) { | |
118 | error_propagate(errp, err); | |
119 | return; | |
120 | } | |
121 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); | |
122 | ||
123 | /* Initialize all UARTs */ | |
124 | for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { | |
125 | static const struct { | |
126 | hwaddr addr; | |
127 | unsigned int irq; | |
128 | } serial_table[FSL_IMX25_NUM_UARTS] = { | |
129 | { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, | |
130 | { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, | |
131 | { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, | |
132 | { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, | |
133 | { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } | |
134 | }; | |
135 | ||
fc38a112 | 136 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
ee708c99 JCD |
137 | |
138 | object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); | |
139 | if (err) { | |
140 | error_propagate(errp, err); | |
141 | return; | |
142 | } | |
143 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); | |
144 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, | |
145 | qdev_get_gpio_in(DEVICE(&s->avic), | |
146 | serial_table[i].irq)); | |
147 | } | |
148 | ||
149 | /* Initialize all GPT timers */ | |
150 | for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { | |
151 | static const struct { | |
152 | hwaddr addr; | |
153 | unsigned int irq; | |
154 | } gpt_table[FSL_IMX25_NUM_GPTS] = { | |
155 | { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, | |
156 | { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, | |
157 | { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, | |
158 | { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } | |
159 | }; | |
160 | ||
cb54d868 | 161 | s->gpt[i].ccm = IMX_CCM(&s->ccm); |
ee708c99 JCD |
162 | |
163 | object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); | |
164 | if (err) { | |
165 | error_propagate(errp, err); | |
166 | return; | |
167 | } | |
168 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); | |
169 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, | |
170 | qdev_get_gpio_in(DEVICE(&s->avic), | |
171 | gpt_table[i].irq)); | |
172 | } | |
173 | ||
174 | /* Initialize all EPIT timers */ | |
175 | for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { | |
176 | static const struct { | |
177 | hwaddr addr; | |
178 | unsigned int irq; | |
179 | } epit_table[FSL_IMX25_NUM_EPITS] = { | |
180 | { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, | |
181 | { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } | |
182 | }; | |
183 | ||
cb54d868 | 184 | s->epit[i].ccm = IMX_CCM(&s->ccm); |
ee708c99 JCD |
185 | |
186 | object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); | |
187 | if (err) { | |
188 | error_propagate(errp, err); | |
189 | return; | |
190 | } | |
191 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); | |
192 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, | |
193 | qdev_get_gpio_in(DEVICE(&s->avic), | |
194 | epit_table[i].irq)); | |
195 | } | |
196 | ||
197 | qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); | |
a699b410 | 198 | |
ee708c99 JCD |
199 | object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); |
200 | if (err) { | |
201 | error_propagate(errp, err); | |
202 | return; | |
203 | } | |
204 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); | |
205 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, | |
206 | qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); | |
207 | ||
f0396549 MK |
208 | object_property_set_bool(OBJECT(&s->rngc), true, "realized", &err); |
209 | if (err) { | |
210 | error_propagate(errp, err); | |
211 | return; | |
212 | } | |
213 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); | |
214 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, | |
215 | qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); | |
ee708c99 JCD |
216 | |
217 | /* Initialize all I2C */ | |
218 | for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { | |
219 | static const struct { | |
220 | hwaddr addr; | |
221 | unsigned int irq; | |
222 | } i2c_table[FSL_IMX25_NUM_I2CS] = { | |
223 | { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, | |
224 | { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, | |
225 | { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } | |
226 | }; | |
227 | ||
228 | object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); | |
229 | if (err) { | |
230 | error_propagate(errp, err); | |
231 | return; | |
232 | } | |
233 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); | |
234 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, | |
235 | qdev_get_gpio_in(DEVICE(&s->avic), | |
236 | i2c_table[i].irq)); | |
237 | } | |
238 | ||
6abc7158 JCD |
239 | /* Initialize all GPIOs */ |
240 | for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { | |
241 | static const struct { | |
242 | hwaddr addr; | |
243 | unsigned int irq; | |
244 | } gpio_table[FSL_IMX25_NUM_GPIOS] = { | |
245 | { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, | |
246 | { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, | |
247 | { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, | |
248 | { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } | |
249 | }; | |
250 | ||
251 | object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); | |
252 | if (err) { | |
253 | error_propagate(errp, err); | |
254 | return; | |
255 | } | |
256 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); | |
257 | /* Connect GPIO IRQ to PIC */ | |
258 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, | |
259 | qdev_get_gpio_in(DEVICE(&s->avic), | |
260 | gpio_table[i].irq)); | |
261 | } | |
262 | ||
bfae1772 GR |
263 | /* Initialize all SDHC */ |
264 | for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { | |
265 | static const struct { | |
266 | hwaddr addr; | |
267 | unsigned int irq; | |
268 | } esdhc_table[FSL_IMX25_NUM_ESDHCS] = { | |
269 | { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ }, | |
270 | { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, | |
271 | }; | |
272 | ||
273 | object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version", | |
274 | &err); | |
275 | object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, | |
276 | "capareg", &err); | |
277 | object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); | |
278 | if (err) { | |
279 | error_propagate(errp, err); | |
280 | return; | |
281 | } | |
282 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); | |
283 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, | |
284 | qdev_get_gpio_in(DEVICE(&s->avic), | |
285 | esdhc_table[i].irq)); | |
286 | } | |
287 | ||
67f52ebe GR |
288 | /* USB */ |
289 | for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { | |
290 | static const struct { | |
291 | hwaddr addr; | |
292 | unsigned int irq; | |
293 | } usb_table[FSL_IMX25_NUM_USBS] = { | |
294 | { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ }, | |
295 | { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ }, | |
296 | }; | |
297 | ||
298 | object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", | |
299 | &error_abort); | |
300 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); | |
301 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, | |
302 | qdev_get_gpio_in(DEVICE(&s->avic), | |
303 | usb_table[i].irq)); | |
304 | } | |
305 | ||
4f0aff00 GR |
306 | /* Watchdog */ |
307 | object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support", | |
308 | &error_abort); | |
309 | object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort); | |
310 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR); | |
311 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0, | |
312 | qdev_get_gpio_in(DEVICE(&s->avic), | |
313 | FSL_IMX25_WDT_IRQ)); | |
314 | ||
ee708c99 | 315 | /* initialize 2 x 16 KB ROM */ |
32b9523a PMD |
316 | memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0", |
317 | FSL_IMX25_ROM0_SIZE, &err); | |
ee708c99 JCD |
318 | if (err) { |
319 | error_propagate(errp, err); | |
320 | return; | |
321 | } | |
322 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, | |
323 | &s->rom[0]); | |
32b9523a PMD |
324 | memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1", |
325 | FSL_IMX25_ROM1_SIZE, &err); | |
ee708c99 JCD |
326 | if (err) { |
327 | error_propagate(errp, err); | |
328 | return; | |
329 | } | |
330 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, | |
331 | &s->rom[1]); | |
332 | ||
333 | /* initialize internal RAM (128 KB) */ | |
98a99ce0 | 334 | memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, |
ee708c99 JCD |
335 | &err); |
336 | if (err) { | |
337 | error_propagate(errp, err); | |
338 | return; | |
339 | } | |
340 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, | |
341 | &s->iram); | |
ee708c99 JCD |
342 | |
343 | /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ | |
32b9523a | 344 | memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias", |
ee708c99 JCD |
345 | &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); |
346 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, | |
347 | &s->iram_alias); | |
348 | } | |
349 | ||
350 | static void fsl_imx25_class_init(ObjectClass *oc, void *data) | |
351 | { | |
352 | DeviceClass *dc = DEVICE_CLASS(oc); | |
353 | ||
354 | dc->realize = fsl_imx25_realize; | |
eccfa35e | 355 | dc->desc = "i.MX25 SOC"; |
5e0c7044 TH |
356 | /* |
357 | * Reason: uses serial_hds in realize and the imx25 board does not | |
358 | * support multiple CPUs | |
359 | */ | |
360 | dc->user_creatable = false; | |
ee708c99 JCD |
361 | } |
362 | ||
363 | static const TypeInfo fsl_imx25_type_info = { | |
364 | .name = TYPE_FSL_IMX25, | |
365 | .parent = TYPE_DEVICE, | |
366 | .instance_size = sizeof(FslIMX25State), | |
367 | .instance_init = fsl_imx25_init, | |
368 | .class_init = fsl_imx25_class_init, | |
369 | }; | |
370 | ||
371 | static void fsl_imx25_register_types(void) | |
372 | { | |
373 | type_register_static(&fsl_imx25_type_info); | |
374 | } | |
375 | ||
376 | type_init(fsl_imx25_register_types) |