[mirror_qemu.git] / hw / arm / fsl-imx25.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * i.MX25 SOC emulation.
 *
 * Based on hw/arm/xlnx-zynqmp.c
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/fsl-imx25.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "chardev/char.h"

static void fsl_imx25_init(Object *obj)
{
    FslIMX25State *s = FSL_IMX25(obj);
    int i;

    object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);

    object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
    qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());

    object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
    qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());

    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX25_GPT);
        qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
        qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
    }

    object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
    qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());

    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
        qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
        qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
    }
}

static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{
    FslIMX25State *s = FSL_IMX25(dev);
    uint8_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);

    /* Initialize all UARTs */
    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX25_NUM_UARTS] = {
            { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
            { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
            { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
            { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
            { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
        };

        if (i < MAX_SERIAL_PORTS) {
            Chardev *chr;

            chr = serial_hds[i];

            if (!chr) {
                char label[20];
                snprintf(label, sizeof(label), "imx31.uart%d", i);
                chr = qemu_chr_new(label, "null");
            }

            qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
        }

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    /* Initialize all GPT timers */
    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpt_table[FSL_IMX25_NUM_GPTS] = {
            { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
            { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
            { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
            { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
        };

        s->gpt[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpt_table[i].irq));
    }

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX25_NUM_EPITS] = {
            { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
            { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);

    object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));


    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX25_NUM_I2CS] = {
            { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
            { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
            { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX25_NUM_GPIOS] = {
            { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
            { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
            { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
            { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* initialize 2 x 16 KB ROM */
    memory_region_init_rom_nomigrate(&s->rom[0], NULL,
                           "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
                                &s->rom[0]);
    memory_region_init_rom_nomigrate(&s->rom[1], NULL,
                           "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
                                &s->rom[1]);

    /* initialize internal RAM (128 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
                                &s->iram);

    /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
    memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
                             &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx25_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx25_realize;

    dc->desc = "i.MX25 SOC";
}

static const TypeInfo fsl_imx25_type_info = {
    .name = TYPE_FSL_IMX25,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX25State),
    .instance_init = fsl_imx25_init,
    .class_init = fsl_imx25_class_init,
};

static void fsl_imx25_register_types(void)
{
    type_register_static(&fsl_imx25_type_info);
}

type_init(fsl_imx25_register_types)
Commit	Line	Data
ee708c99 JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
	3	*
	4	* i.MX25 SOC emulation.
	5	*
	6	* Based on hw/arm/xlnx-zynqmp.c
	7	*
	8	* Copyright (C) 2015 Xilinx Inc
	9	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	19	* for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License along
	22	* with this program; if not, see <http://www.gnu.org/licenses/>.
	23	*/
	24
12b16722	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
4771d756 PB	27	#include "qemu-common.h"
4771d756 PB	28	#include "cpu.h"
ee708c99 JCD	29	#include "hw/arm/fsl-imx25.h"
	30	#include "sysemu/sysemu.h"
	31	#include "exec/address-spaces.h"
	32	#include "hw/boards.h"
8228e353	33	#include "chardev/char.h"
ee708c99 JCD	34
	35	static void fsl_imx25_init(Object *obj)
	36	{
	37	FslIMX25State *s = FSL_IMX25(obj);
	38	int i;
	39
	40	object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
	41
	42	object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
	43	qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
	44
92eccc6e	45	object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
ee708c99 JCD	46	qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
	47
	48	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
	49	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
	50	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	51	}
	52
	53	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
66542f63	54	object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX25_GPT);
ee708c99 JCD	55	qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
	56	}
	57
	58	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
	59	object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
	60	qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
	61	}
	62
	63	object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
	64	qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());
	65
	66	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
	67	object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
	68	qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
	69	}
6abc7158 JCD	70
	71	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
	72	object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
	73	qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
	74	}
ee708c99 JCD	75	}
	76
	77	static void fsl_imx25_realize(DeviceState dev, Error *errp)
	78	{
	79	FslIMX25State *s = FSL_IMX25(dev);
	80	uint8_t i;
	81	Error *err = NULL;
	82
	83	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	84	if (err) {
	85	error_propagate(errp, err);
	86	return;
	87	}
	88
	89	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	90	if (err) {
	91	error_propagate(errp, err);
	92	return;
	93	}
	94	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
	95	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	96	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	97	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	98	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	99
	100	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	101	if (err) {
	102	error_propagate(errp, err);
	103	return;
	104	}
	105	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
	106
	107	/* Initialize all UARTs */
	108	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
	109	static const struct {
	110	hwaddr addr;
	111	unsigned int irq;
	112	} serial_table[FSL_IMX25_NUM_UARTS] = {
	113	{ FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
	114	{ FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
	115	{ FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
	116	{ FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
	117	{ FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
	118	};
	119
	120	if (i < MAX_SERIAL_PORTS) {
0ec7b3e7	121	Chardev *chr;
ee708c99 JCD	122
	123	chr = serial_hds[i];
	124
	125	if (!chr) {
	126	char label[20];
	127	snprintf(label, sizeof(label), "imx31.uart%d", i);
b4948be9	128	chr = qemu_chr_new(label, "null");
ee708c99 JCD	129	}
	130
	131	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
	132	}
	133
	134	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	135	if (err) {
	136	error_propagate(errp, err);
	137	return;
	138	}
	139	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	140	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	141	qdev_get_gpio_in(DEVICE(&s->avic),
	142	serial_table[i].irq));
	143	}
	144
	145	/* Initialize all GPT timers */
	146	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
	147	static const struct {
	148	hwaddr addr;
	149	unsigned int irq;
	150	} gpt_table[FSL_IMX25_NUM_GPTS] = {
	151	{ FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
	152	{ FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
	153	{ FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
	154	{ FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
	155	};
	156
cb54d868	157	s->gpt[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	158
	159	object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
	160	if (err) {
	161	error_propagate(errp, err);
	162	return;
	163	}
	164	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
	165	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
	166	qdev_get_gpio_in(DEVICE(&s->avic),
	167	gpt_table[i].irq));
	168	}
	169
	170	/* Initialize all EPIT timers */
	171	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
	172	static const struct {
	173	hwaddr addr;
	174	unsigned int irq;
	175	} epit_table[FSL_IMX25_NUM_EPITS] = {
	176	{ FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
	177	{ FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
	178	};
	179
cb54d868	180	s->epit[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	181
	182	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	183	if (err) {
	184	error_propagate(errp, err);
	185	return;
	186	}
	187	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	188	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	189	qdev_get_gpio_in(DEVICE(&s->avic),
	190	epit_table[i].irq));
	191	}
	192
	193	qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
a699b410	194
ee708c99 JCD	195	object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
	196	if (err) {
	197	error_propagate(errp, err);
	198	return;
	199	}
	200	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
	201	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
	202	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
	203
	204
	205	/* Initialize all I2C */
	206	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
	207	static const struct {
	208	hwaddr addr;
	209	unsigned int irq;
	210	} i2c_table[FSL_IMX25_NUM_I2CS] = {
	211	{ FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
	212	{ FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
	213	{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
	214	};
	215
	216	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	217	if (err) {
	218	error_propagate(errp, err);
	219	return;
	220	}
	221	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	222	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	223	qdev_get_gpio_in(DEVICE(&s->avic),
	224	i2c_table[i].irq));
	225	}
	226
6abc7158 JCD	227	/* Initialize all GPIOs */
	228	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
	229	static const struct {
	230	hwaddr addr;
	231	unsigned int irq;
	232	} gpio_table[FSL_IMX25_NUM_GPIOS] = {
	233	{ FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
	234	{ FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
	235	{ FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
	236	{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
	237	};
	238
	239	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	240	if (err) {
	241	error_propagate(errp, err);
	242	return;
	243	}
	244	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	245	/* Connect GPIO IRQ to PIC */
	246	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	247	qdev_get_gpio_in(DEVICE(&s->avic),
	248	gpio_table[i].irq));
	249	}
	250
ee708c99	251	/* initialize 2 x 16 KB ROM */
b59821a9	252	memory_region_init_rom_nomigrate(&s->rom[0], NULL,
a7aeb5f7	253	"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
ee708c99 JCD	254	if (err) {
	255	error_propagate(errp, err);
	256	return;
	257	}
	258	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
	259	&s->rom[0]);
b59821a9	260	memory_region_init_rom_nomigrate(&s->rom[1], NULL,
a7aeb5f7	261	"imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
ee708c99 JCD	262	if (err) {
	263	error_propagate(errp, err);
	264	return;
	265	}
	266	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
	267	&s->rom[1]);
	268
	269	/* initialize internal RAM (128 KB) */
98a99ce0	270	memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
ee708c99 JCD	271	&err);
	272	if (err) {
	273	error_propagate(errp, err);
	274	return;
	275	}
	276	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
	277	&s->iram);
ee708c99 JCD	278
	279	/* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
	280	memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
	281	&s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
	282	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
	283	&s->iram_alias);
	284	}
	285
	286	static void fsl_imx25_class_init(ObjectClass oc, void data)
	287	{
	288	DeviceClass *dc = DEVICE_CLASS(oc);
	289
	290	dc->realize = fsl_imx25_realize;
4c315c27	291
eccfa35e	292	dc->desc = "i.MX25 SOC";
ee708c99 JCD	293	}
	294
	295	static const TypeInfo fsl_imx25_type_info = {
	296	.name = TYPE_FSL_IMX25,
	297	.parent = TYPE_DEVICE,
	298	.instance_size = sizeof(FslIMX25State),
	299	.instance_init = fsl_imx25_init,
	300	.class_init = fsl_imx25_class_init,
	301	};
	302
	303	static void fsl_imx25_register_types(void)
	304	{
	305	type_register_static(&fsl_imx25_type_info);
	306	}
	307
	308	type_init(fsl_imx25_register_types)