[mirror_qemu.git] / hw / arm / fsl-imx25.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * i.MX25 SOC emulation.
 *
 * Based on hw/arm/xlnx-zynqmp.c
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/fsl-imx25.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "sysemu/char.h"

static void fsl_imx25_init(Object *obj)
{
    FslIMX25State *s = FSL_IMX25(obj);
    int i;

    object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);

    object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
    qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());

    object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
    qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());

    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);
        qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
        qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
    }

    object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
    qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());

    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
        qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
        qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
    }
}

static void fsl_imx25_realize(DeviceState *dev, Error **errp)
{
    FslIMX25State *s = FSL_IMX25(dev);
    uint8_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);

    /* Initialize all UARTs */
    for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX25_NUM_UARTS] = {
            { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
            { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
            { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
            { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
            { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
        };

        if (i < MAX_SERIAL_PORTS) {
            CharDriverState *chr;

            chr = serial_hds[i];

            if (!chr) {
                char label[20];
                snprintf(label, sizeof(label), "imx31.uart%d", i);
                chr = qemu_chr_new(label, "null", NULL);
            }

            qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
        }

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    /* Initialize all GPT timers */
    for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpt_table[FSL_IMX25_NUM_GPTS] = {
            { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
            { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
            { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
            { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
        };

        s->gpt[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpt_table[i].irq));
    }

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX25_NUM_EPITS] = {
            { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
            { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
    object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));


    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX25_NUM_I2CS] = {
            { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
            { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
            { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX25_NUM_GPIOS] = {
            { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
            { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
            { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
            { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* initialize 2 x 16 KB ROM */
    memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL,
                                  "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
                                &s->rom[0]);
    memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL,
                                  "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
                                &s->rom[1]);

    /* initialize internal RAM (128 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
                                &s->iram);
    vmstate_register_ram_global(&s->iram);

    /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
    memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
                             &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx25_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx25_realize;

    /*
     * Reason: creates an ARM CPU, thus use after free(), see
     * arm_cpu_class_init()
     */
    dc->cannot_destroy_with_object_finalize_yet = true;
    dc->desc = "i.MX25 SOC";
}

static const TypeInfo fsl_imx25_type_info = {
    .name = TYPE_FSL_IMX25,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX25State),
    .instance_init = fsl_imx25_init,
    .class_init = fsl_imx25_class_init,
};

static void fsl_imx25_register_types(void)
{
    type_register_static(&fsl_imx25_type_info);
}

type_init(fsl_imx25_register_types)
Commit	Line	Data
ee708c99 JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
	3	*
	4	* i.MX25 SOC emulation.
	5	*
	6	* Based on hw/arm/xlnx-zynqmp.c
	7	*
	8	* Copyright (C) 2015 Xilinx Inc
	9	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but WITHOUT
	17	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	19	* for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License along
	22	* with this program; if not, see <http://www.gnu.org/licenses/>.
	23	*/
	24
12b16722	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
ee708c99 JCD	27	#include "hw/arm/fsl-imx25.h"
	28	#include "sysemu/sysemu.h"
	29	#include "exec/address-spaces.h"
	30	#include "hw/boards.h"
	31	#include "sysemu/char.h"
	32
	33	static void fsl_imx25_init(Object *obj)
	34	{
	35	FslIMX25State *s = FSL_IMX25(obj);
	36	int i;
	37
	38	object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
	39
	40	object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
	41	qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
	42
92eccc6e	43	object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
ee708c99 JCD	44	qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
	45
	46	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
	47	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
	48	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	49	}
	50
	51	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
	52	object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);
	53	qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
	54	}
	55
	56	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
	57	object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
	58	qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
	59	}
	60
	61	object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
	62	qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());
	63
	64	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
	65	object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
	66	qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
	67	}
6abc7158 JCD	68
	69	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
	70	object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
	71	qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
	72	}
ee708c99 JCD	73	}
	74
	75	static void fsl_imx25_realize(DeviceState dev, Error *errp)
	76	{
	77	FslIMX25State *s = FSL_IMX25(dev);
	78	uint8_t i;
	79	Error *err = NULL;
	80
	81	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	82	if (err) {
	83	error_propagate(errp, err);
	84	return;
	85	}
	86
	87	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	88	if (err) {
	89	error_propagate(errp, err);
	90	return;
	91	}
	92	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
	93	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	94	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	95	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	96	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	97
	98	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	99	if (err) {
	100	error_propagate(errp, err);
	101	return;
	102	}
	103	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
	104
	105	/* Initialize all UARTs */
	106	for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
	107	static const struct {
	108	hwaddr addr;
	109	unsigned int irq;
	110	} serial_table[FSL_IMX25_NUM_UARTS] = {
	111	{ FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
	112	{ FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
	113	{ FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
	114	{ FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
	115	{ FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
	116	};
	117
	118	if (i < MAX_SERIAL_PORTS) {
	119	CharDriverState *chr;
	120
	121	chr = serial_hds[i];
	122
	123	if (!chr) {
	124	char label[20];
	125	snprintf(label, sizeof(label), "imx31.uart%d", i);
	126	chr = qemu_chr_new(label, "null", NULL);
	127	}
	128
	129	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
	130	}
	131
	132	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	133	if (err) {
	134	error_propagate(errp, err);
	135	return;
	136	}
137	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
138	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
139	qdev_get_gpio_in(DEVICE(&s->avic),
140	serial_table[i].irq));
141	}
142
143	/* Initialize all GPT timers */
144	for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
145	static const struct {
146	hwaddr addr;
147	unsigned int irq;
148	} gpt_table[FSL_IMX25_NUM_GPTS] = {
149	{ FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
150	{ FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
151	{ FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
152	{ FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
153	};
154
cb54d868	155	s->gpt[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	156
	157	object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
	158	if (err) {
	159	error_propagate(errp, err);
	160	return;
	161	}
	162	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
	163	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
	164	qdev_get_gpio_in(DEVICE(&s->avic),
	165	gpt_table[i].irq));
	166	}
	167
	168	/* Initialize all EPIT timers */
	169	for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
	170	static const struct {
	171	hwaddr addr;
	172	unsigned int irq;
	173	} epit_table[FSL_IMX25_NUM_EPITS] = {
	174	{ FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
	175	{ FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
	176	};
	177
cb54d868	178	s->epit[i].ccm = IMX_CCM(&s->ccm);
ee708c99 JCD	179
	180	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	181	if (err) {
	182	error_propagate(errp, err);
	183	return;
	184	}
	185	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	186	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	187	qdev_get_gpio_in(DEVICE(&s->avic),
	188	epit_table[i].irq));
	189	}
	190
	191	qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
	192	object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
	193	if (err) {
	194	error_propagate(errp, err);
	195	return;
	196	}
	197	sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
	198	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
	199	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
	200
	201
	202	/* Initialize all I2C */
	203	for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
	204	static const struct {
	205	hwaddr addr;
	206	unsigned int irq;
	207	} i2c_table[FSL_IMX25_NUM_I2CS] = {
	208	{ FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
	209	{ FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
	210	{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
	211	};
	212
	213	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	214	if (err) {
	215	error_propagate(errp, err);
	216	return;
	217	}
	218	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	219	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	220	qdev_get_gpio_in(DEVICE(&s->avic),
	221	i2c_table[i].irq));
	222	}
	223
6abc7158 JCD	224	/* Initialize all GPIOs */
	225	for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
	226	static const struct {
	227	hwaddr addr;
	228	unsigned int irq;
	229	} gpio_table[FSL_IMX25_NUM_GPIOS] = {
	230	{ FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
	231	{ FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
	232	{ FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
	233	{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
	234	};
	235
	236	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	237	if (err) {
	238	error_propagate(errp, err);
	239	return;
	240	}
	241	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	242	/* Connect GPIO IRQ to PIC */
	243	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	244	qdev_get_gpio_in(DEVICE(&s->avic),
	245	gpio_table[i].irq));
	246	}
	247
ee708c99 JCD	248	/* initialize 2 x 16 KB ROM */
	249	memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL,
	250	"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
	251	if (err) {
	252	error_propagate(errp, err);
	253	return;
	254	}
	255	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
	256	&s->rom[0]);
	257	memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL,
	258	"imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
	259	if (err) {
	260	error_propagate(errp, err);
	261	return;
	262	}
	263	memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
	264	&s->rom[1]);
	265
	266	/* initialize internal RAM (128 KB) */
	267	memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
	268	&err);
	269	if (err) {
	270	error_propagate(errp, err);
	271	return;
	272	}
	273	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
	274	&s->iram);
	275	vmstate_register_ram_global(&s->iram);
	276
	277	/* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
	278	memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
	279	&s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
	280	memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
	281	&s->iram_alias);
	282	}
	283
	284	static void fsl_imx25_class_init(ObjectClass oc, void data)
	285	{
	286	DeviceClass *dc = DEVICE_CLASS(oc);
	287
	288	dc->realize = fsl_imx25_realize;
4c315c27 MA	289
	290	/*
	291	* Reason: creates an ARM CPU, thus use after free(), see
	292	* arm_cpu_class_init()
	293	*/
	294	dc->cannot_destroy_with_object_finalize_yet = true;
eccfa35e	295	dc->desc = "i.MX25 SOC";
ee708c99 JCD	296	}
	297
	298	static const TypeInfo fsl_imx25_type_info = {
	299	.name = TYPE_FSL_IMX25,
	300	.parent = TYPE_DEVICE,
	301	.instance_size = sizeof(FslIMX25State),
	302	.instance_init = fsl_imx25_init,
	303	.class_init = fsl_imx25_class_init,
	304	};
	305
	306	static void fsl_imx25_register_types(void)
	307	{
	308	type_register_static(&fsl_imx25_type_info);
	309	}
	310
	311	type_init(fsl_imx25_register_types)