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558df83d JCD |
1 | /* |
2 | * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> | |
3 | * | |
4 | * i.MX31 SOC emulation. | |
5 | * | |
6 | * Based on hw/arm/fsl-imx31.c | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
12b16722 | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
558df83d JCD |
24 | #include "hw/arm/fsl-imx31.h" |
25 | #include "sysemu/sysemu.h" | |
26 | #include "exec/address-spaces.h" | |
27 | #include "hw/boards.h" | |
28 | #include "sysemu/char.h" | |
29 | ||
30 | static void fsl_imx31_init(Object *obj) | |
31 | { | |
32 | FslIMX31State *s = FSL_IMX31(obj); | |
33 | int i; | |
34 | ||
35 | object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); | |
36 | ||
37 | object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); | |
38 | qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); | |
39 | ||
cb54d868 | 40 | object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM); |
558df83d JCD |
41 | qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); |
42 | ||
43 | for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { | |
44 | object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); | |
45 | qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); | |
46 | } | |
47 | ||
48 | object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT); | |
49 | qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); | |
50 | ||
51 | for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { | |
52 | object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); | |
53 | qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); | |
54 | } | |
d4e26d10 JCD |
55 | |
56 | for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { | |
57 | object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); | |
58 | qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); | |
59 | } | |
dde0c4ca JCD |
60 | |
61 | for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { | |
62 | object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); | |
63 | qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); | |
64 | } | |
558df83d JCD |
65 | } |
66 | ||
67 | static void fsl_imx31_realize(DeviceState *dev, Error **errp) | |
68 | { | |
69 | FslIMX31State *s = FSL_IMX31(dev); | |
70 | uint16_t i; | |
71 | Error *err = NULL; | |
72 | ||
73 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | |
74 | if (err) { | |
75 | error_propagate(errp, err); | |
76 | return; | |
77 | } | |
78 | ||
79 | object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); | |
80 | if (err) { | |
81 | error_propagate(errp, err); | |
82 | return; | |
83 | } | |
84 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); | |
85 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, | |
86 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); | |
87 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, | |
88 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); | |
89 | ||
90 | object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); | |
91 | if (err) { | |
92 | error_propagate(errp, err); | |
93 | return; | |
94 | } | |
95 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); | |
96 | ||
97 | /* Initialize all UARTS */ | |
98 | for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { | |
99 | static const struct { | |
100 | hwaddr addr; | |
101 | unsigned int irq; | |
102 | } serial_table[FSL_IMX31_NUM_UARTS] = { | |
103 | { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, | |
104 | { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, | |
105 | }; | |
106 | ||
107 | if (i < MAX_SERIAL_PORTS) { | |
108 | CharDriverState *chr; | |
109 | ||
110 | chr = serial_hds[i]; | |
111 | ||
112 | if (!chr) { | |
113 | char label[20]; | |
114 | snprintf(label, sizeof(label), "imx31.uart%d", i); | |
115 | chr = qemu_chr_new(label, "null", NULL); | |
116 | } | |
117 | ||
118 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); | |
119 | } | |
120 | ||
121 | object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); | |
122 | if (err) { | |
123 | error_propagate(errp, err); | |
124 | return; | |
125 | } | |
126 | ||
127 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); | |
128 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, | |
129 | qdev_get_gpio_in(DEVICE(&s->avic), | |
130 | serial_table[i].irq)); | |
131 | } | |
132 | ||
cb54d868 | 133 | s->gpt.ccm = IMX_CCM(&s->ccm); |
558df83d JCD |
134 | |
135 | object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); | |
136 | if (err) { | |
137 | error_propagate(errp, err); | |
138 | return; | |
139 | } | |
140 | ||
141 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); | |
142 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, | |
143 | qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); | |
144 | ||
145 | /* Initialize all EPIT timers */ | |
146 | for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { | |
147 | static const struct { | |
148 | hwaddr addr; | |
149 | unsigned int irq; | |
150 | } epit_table[FSL_IMX31_NUM_EPITS] = { | |
151 | { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, | |
152 | { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, | |
153 | }; | |
154 | ||
cb54d868 | 155 | s->epit[i].ccm = IMX_CCM(&s->ccm); |
558df83d JCD |
156 | |
157 | object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); | |
158 | if (err) { | |
159 | error_propagate(errp, err); | |
160 | return; | |
161 | } | |
162 | ||
163 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); | |
164 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, | |
165 | qdev_get_gpio_in(DEVICE(&s->avic), | |
166 | epit_table[i].irq)); | |
167 | } | |
d4e26d10 JCD |
168 | |
169 | /* Initialize all I2C */ | |
170 | for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { | |
171 | static const struct { | |
172 | hwaddr addr; | |
173 | unsigned int irq; | |
174 | } i2c_table[FSL_IMX31_NUM_I2CS] = { | |
175 | { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, | |
176 | { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, | |
177 | { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } | |
178 | }; | |
179 | ||
180 | /* Initialize the I2C */ | |
181 | object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); | |
182 | if (err) { | |
183 | error_propagate(errp, err); | |
184 | return; | |
185 | } | |
186 | /* Map I2C memory */ | |
187 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); | |
188 | /* Connect I2C IRQ to PIC */ | |
189 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, | |
190 | qdev_get_gpio_in(DEVICE(&s->avic), | |
191 | i2c_table[i].irq)); | |
192 | } | |
dde0c4ca JCD |
193 | |
194 | /* Initialize all GPIOs */ | |
195 | for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { | |
196 | static const struct { | |
197 | hwaddr addr; | |
198 | unsigned int irq; | |
199 | } gpio_table[FSL_IMX31_NUM_GPIOS] = { | |
200 | { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, | |
201 | { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, | |
202 | { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } | |
203 | }; | |
204 | ||
205 | object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", | |
206 | &error_abort); | |
207 | object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); | |
208 | if (err) { | |
209 | error_propagate(errp, err); | |
210 | return; | |
211 | } | |
212 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); | |
213 | /* Connect GPIO IRQ to PIC */ | |
214 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, | |
215 | qdev_get_gpio_in(DEVICE(&s->avic), | |
216 | gpio_table[i].irq)); | |
217 | } | |
558df83d JCD |
218 | |
219 | /* On a real system, the first 16k is a `secure boot rom' */ | |
220 | memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL, | |
221 | "imx31.secure_rom", | |
222 | FSL_IMX31_SECURE_ROM_SIZE, &err); | |
223 | if (err) { | |
224 | error_propagate(errp, err); | |
225 | return; | |
226 | } | |
227 | memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, | |
228 | &s->secure_rom); | |
229 | ||
230 | /* There is also a 16k ROM */ | |
231 | memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom", | |
232 | FSL_IMX31_ROM_SIZE, &err); | |
233 | if (err) { | |
234 | error_propagate(errp, err); | |
235 | return; | |
236 | } | |
237 | memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, | |
238 | &s->rom); | |
239 | ||
240 | /* initialize internal RAM (16 KB) */ | |
241 | memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, | |
242 | &err); | |
243 | if (err) { | |
244 | error_propagate(errp, err); | |
245 | return; | |
246 | } | |
247 | memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, | |
248 | &s->iram); | |
249 | vmstate_register_ram_global(&s->iram); | |
250 | ||
251 | /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ | |
252 | memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias", | |
253 | &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); | |
254 | memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, | |
255 | &s->iram_alias); | |
256 | } | |
257 | ||
258 | static void fsl_imx31_class_init(ObjectClass *oc, void *data) | |
259 | { | |
260 | DeviceClass *dc = DEVICE_CLASS(oc); | |
261 | ||
262 | dc->realize = fsl_imx31_realize; | |
4c315c27 MA |
263 | |
264 | /* | |
265 | * Reason: creates an ARM CPU, thus use after free(), see | |
266 | * arm_cpu_class_init() | |
267 | */ | |
268 | dc->cannot_destroy_with_object_finalize_yet = true; | |
eccfa35e | 269 | dc->desc = "i.MX31 SOC"; |
558df83d JCD |
270 | } |
271 | ||
272 | static const TypeInfo fsl_imx31_type_info = { | |
273 | .name = TYPE_FSL_IMX31, | |
274 | .parent = TYPE_DEVICE, | |
275 | .instance_size = sizeof(FslIMX31State), | |
276 | .instance_init = fsl_imx31_init, | |
277 | .class_init = fsl_imx31_class_init, | |
278 | }; | |
279 | ||
280 | static void fsl_imx31_register_types(void) | |
281 | { | |
282 | type_register_static(&fsl_imx31_type_info); | |
283 | } | |
284 | ||
285 | type_init(fsl_imx31_register_types) |