[mirror_qemu.git] / hw / arm / fsl-imx6.c

/*
 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * i.MX6 SOC emulation.
 *
 * Based on hw/arm/fsl-imx31.c
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "sysemu/sysemu.h"
#include "chardev/char.h"
#include "qemu/error-report.h"
#include "qemu/module.h"

#define IMX6_ESDHC_CAPABILITIES     0x057834b4

#define NAME_SIZE 20

static void fsl_imx6_init(Object *obj)
{
    MachineState *ms = MACHINE(qdev_get_machine());
    FslIMX6State *s = FSL_IMX6(obj);
    char name[NAME_SIZE];
    int i;

    for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
        snprintf(name, NAME_SIZE, "cpu%d", i);
        object_initialize_child(obj, name, &s->cpu[i],
                                ARM_CPU_TYPE_NAME("cortex-a9"));
    }

    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);

    object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);

    object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);

    object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);

    for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
        snprintf(name, NAME_SIZE, "uart%d", i + 1);
        object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
    }

    object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);

    for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
        snprintf(name, NAME_SIZE, "epit%d", i + 1);
        object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
    }

    for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
        snprintf(name, NAME_SIZE, "i2c%d", i + 1);
        object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
    }

    for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
        snprintf(name, NAME_SIZE, "gpio%d", i + 1);
        object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
    }

    for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
        snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
        object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
    }

    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
        snprintf(name, NAME_SIZE, "usbphy%d", i);
        object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
    }
    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
        snprintf(name, NAME_SIZE, "usb%d", i);
        object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
    }

    for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
        snprintf(name, NAME_SIZE, "spi%d", i + 1);
        object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
    }
    for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
        snprintf(name, NAME_SIZE, "wdt%d", i);
        object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
    }


    object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
}

static void fsl_imx6_realize(DeviceState *dev, Error **errp)
{
    MachineState *ms = MACHINE(qdev_get_machine());
    FslIMX6State *s = FSL_IMX6(dev);
    uint16_t i;
    Error *err = NULL;
    unsigned int smp_cpus = ms->smp.cpus;

    if (smp_cpus > FSL_IMX6_NUM_CPUS) {
        error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
                   TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
        return;
    }

    for (i = 0; i < smp_cpus; i++) {

        /* On uniprocessor, the CBAR is set to 0 */
        if (smp_cpus > 1) {
            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
                                    FSL_IMX6_A9MPCORE_ADDR, &error_abort);
        }

        /* All CPU but CPU 0 start in power off mode */
        if (i) {
            object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
                                     true, &error_abort);
        }

        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
            return;
        }
    }

    object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus,
                            &error_abort);

    object_property_set_int(OBJECT(&s->a9mpcore), "num-irq",
                            FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) {
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);

    for (i = 0; i < smp_cpus; i++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
    }

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) {
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);

    /* Initialize all UARTs */
    for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX6_NUM_UARTS] = {
            { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
            { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
            { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
            { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
            { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
        };

        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));

        if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            serial_table[i].irq));
    }

    s->gpt.ccm = IMX_CCM(&s->ccm);

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
                       qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                        FSL_IMX6_GPT_IRQ));

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX6_NUM_EPITS] = {
            { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
            { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) {
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            epit_table[i].irq));
    }

    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX6_NUM_I2CS] = {
            { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
            { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
            { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
        };

        if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq_low;
            unsigned int irq_high;
        } gpio_table[FSL_IMX6_NUM_GPIOS] = {
            {
                FSL_IMX6_GPIO1_ADDR,
                FSL_IMX6_GPIO1_LOW_IRQ,
                FSL_IMX6_GPIO1_HIGH_IRQ
            },
            {
                FSL_IMX6_GPIO2_ADDR,
                FSL_IMX6_GPIO2_LOW_IRQ,
                FSL_IMX6_GPIO2_HIGH_IRQ
            },
            {
                FSL_IMX6_GPIO3_ADDR,
                FSL_IMX6_GPIO3_LOW_IRQ,
                FSL_IMX6_GPIO3_HIGH_IRQ
            },
            {
                FSL_IMX6_GPIO4_ADDR,
                FSL_IMX6_GPIO4_LOW_IRQ,
                FSL_IMX6_GPIO4_HIGH_IRQ
            },
            {
                FSL_IMX6_GPIO5_ADDR,
                FSL_IMX6_GPIO5_LOW_IRQ,
                FSL_IMX6_GPIO5_HIGH_IRQ
            },
            {
                FSL_IMX6_GPIO6_ADDR,
                FSL_IMX6_GPIO6_LOW_IRQ,
                FSL_IMX6_GPIO6_HIGH_IRQ
            },
            {
                FSL_IMX6_GPIO7_ADDR,
                FSL_IMX6_GPIO7_LOW_IRQ,
                FSL_IMX6_GPIO7_HIGH_IRQ
            },
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
                                 true, &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            gpio_table[i].irq_low));
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            gpio_table[i].irq_high));
    }

    /* Initialize all SDHC */
    for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
            { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
            { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
            { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
            { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
        };

        /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
        object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3,
                                 &error_abort);
        object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg",
                                 IMX6_ESDHC_CAPABILITIES, &error_abort);
        object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor",
                                 SDHCI_VENDOR_IMX, &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) {
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            esdhc_table[i].irq));
    }

    /* USB */
    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
        sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
                        FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
    }
    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
        static const int FSL_IMX6_USBn_IRQ[] = {
            FSL_IMX6_USB_OTG_IRQ,
            FSL_IMX6_USB_HOST1_IRQ,
            FSL_IMX6_USB_HOST2_IRQ,
            FSL_IMX6_USB_HOST3_IRQ,
        };

        sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
                        FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            FSL_IMX6_USBn_IRQ[i]));
    }

    /* Initialize all ECSPI */
    for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } spi_table[FSL_IMX6_NUM_ECSPIS] = {
            { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
            { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
            { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
            { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
            { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
        };

        /* Initialize the SPI */
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            spi_table[i].irq));
    }

    object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
    qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
                       qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                        FSL_IMX6_ENET_MAC_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
                       qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                        FSL_IMX6_ENET_MAC_1588_IRQ));

    /*
     * SNVS
     */
    sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR);

    /*
     * Watchdog
     */
    for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
        static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
            FSL_IMX6_WDOG1_ADDR,
            FSL_IMX6_WDOG2_ADDR,
        };
        static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
            FSL_IMX6_WDOG1_IRQ,
            FSL_IMX6_WDOG2_IRQ,
        };

        object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
                                 true, &error_abort);
        sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
                                            FSL_IMX6_WDOGn_IRQ[i]));
    }

    /* ROM memory */
    memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
                           FSL_IMX6_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
                                &s->rom);

    /* CAAM memory */
    memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
                           FSL_IMX6_CAAM_MEM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
                                &s->caam);

    /* OCRAM memory */
    memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
                                &s->ocram);

    /* internal OCRAM (256 KB) is aliased over 1 MB */
    memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
                             &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
                                &s->ocram_alias);
}

static Property fsl_imx6_properties[] = {
    DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void fsl_imx6_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    device_class_set_props(dc, fsl_imx6_properties);
    dc->realize = fsl_imx6_realize;
    dc->desc = "i.MX6 SOC";
    /* Reason: Uses serial_hd() in the realize() function */
    dc->user_creatable = false;
}

static const TypeInfo fsl_imx6_type_info = {
    .name = TYPE_FSL_IMX6,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX6State),
    .instance_init = fsl_imx6_init,
    .class_init = fsl_imx6_class_init,
};

static void fsl_imx6_register_types(void)
{
    type_register_static(&fsl_imx6_type_info);
}

type_init(fsl_imx6_register_types)
Commit	Line	Data
ec46eaa8 JCD	1	/*
	2	* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
	3	*
	4	* i.MX6 SOC emulation.
	5	*
	6	* Based on hw/arm/fsl-imx31.c
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "qemu/osdep.h"
	23	#include "qapi/error.h"
ec46eaa8	24	#include "hw/arm/fsl-imx6.h"
49cd5578	25	#include "hw/usb/imx-usb-phy.h"
cc7d44c2	26	#include "hw/boards.h"
a27bd6c7	27	#include "hw/qdev-properties.h"
ec46eaa8	28	#include "sysemu/sysemu.h"
8228e353	29	#include "chardev/char.h"
ec46eaa8	30	#include "qemu/error-report.h"
0b8fa32f	31	#include "qemu/module.h"
ec46eaa8	32
7f072603 PMD	33	#define IMX6_ESDHC_CAPABILITIES 0x057834b4
7f072603 PMD	34
ec46eaa8 JCD	35	#define NAME_SIZE 20
	36
	37	static void fsl_imx6_init(Object *obj)
	38	{
cc7d44c2	39	MachineState *ms = MACHINE(qdev_get_machine());
ec46eaa8 JCD	40	FslIMX6State *s = FSL_IMX6(obj);
	41	char name[NAME_SIZE];
	42	int i;
	43
cc7d44c2	44	for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
ec46eaa8	45	snprintf(name, NAME_SIZE, "cpu%d", i);
9fc7fc4d MA	46	object_initialize_child(obj, name, &s->cpu[i],
9fc7fc4d MA	47	ARM_CPU_TYPE_NAME("cortex-a9"));
ec46eaa8 JCD	48	}
ec46eaa8 JCD	49
db873cc5	50	object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
ec46eaa8	51
db873cc5	52	object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
ec46eaa8	53
db873cc5	54	object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
ec46eaa8	55
bbb02509 VC	56	object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
bbb02509 VC	57
ec46eaa8	58	for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
ec46eaa8	59	snprintf(name, NAME_SIZE, "uart%d", i + 1);
db873cc5	60	object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
ec46eaa8 JCD	61	}
ec46eaa8 JCD	62
db873cc5	63	object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
ec46eaa8 JCD	64
ec46eaa8 JCD	65	for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
ec46eaa8	66	snprintf(name, NAME_SIZE, "epit%d", i + 1);
db873cc5	67	object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
ec46eaa8 JCD	68	}
	69
	70	for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
ec46eaa8	71	snprintf(name, NAME_SIZE, "i2c%d", i + 1);
db873cc5	72	object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
ec46eaa8 JCD	73	}
	74
	75	for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
ec46eaa8	76	snprintf(name, NAME_SIZE, "gpio%d", i + 1);
db873cc5	77	object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
ec46eaa8 JCD	78	}
	79
	80	for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
ec46eaa8	81	snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
db873cc5	82	object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
ec46eaa8 JCD	83	}
ec46eaa8 JCD	84
49cd5578 GR	85	for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
49cd5578 GR	86	snprintf(name, NAME_SIZE, "usbphy%d", i);
db873cc5	87	object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
49cd5578 GR	88	}
	89	for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
	90	snprintf(name, NAME_SIZE, "usb%d", i);
db873cc5	91	object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
49cd5578 GR	92	}
49cd5578 GR	93
ec46eaa8	94	for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
ec46eaa8	95	snprintf(name, NAME_SIZE, "spi%d", i + 1);
db873cc5	96	object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
ec46eaa8	97	}
5fecbf0f RK	98	for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
5fecbf0f RK	99	snprintf(name, NAME_SIZE, "wdt%d", i);
db873cc5	100	object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
5fecbf0f RK	101	}
5fecbf0f RK	102
517b5e9a	103
db873cc5	104	object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
ec46eaa8 JCD	105	}
	106
	107	static void fsl_imx6_realize(DeviceState dev, Error *errp)
	108	{
cc7d44c2	109	MachineState *ms = MACHINE(qdev_get_machine());
ec46eaa8 JCD	110	FslIMX6State *s = FSL_IMX6(dev);
	111	uint16_t i;
	112	Error *err = NULL;
cc7d44c2	113	unsigned int smp_cpus = ms->smp.cpus;
ec46eaa8	114
f640a591 TH	115	if (smp_cpus > FSL_IMX6_NUM_CPUS) {
	116	error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
	117	TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
	118	return;
	119	}
	120
ec46eaa8 JCD	121	for (i = 0; i < smp_cpus; i++) {
	122
	123	/* On uniprocessor, the CBAR is set to 0 */
	124	if (smp_cpus > 1) {
5325cc34 MA	125	object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
5325cc34 MA	126	FSL_IMX6_A9MPCORE_ADDR, &error_abort);
ec46eaa8 JCD	127	}
	128
	129	/* All CPU but CPU 0 start in power off mode */
	130	if (i) {
5325cc34 MA	131	object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
5325cc34 MA	132	true, &error_abort);
ec46eaa8 JCD	133	}
ec46eaa8 JCD	134
668f62ec	135	if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
ec46eaa8 JCD	136	return;
	137	}
	138	}
	139
5325cc34	140	object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus,
ec46eaa8 JCD	141	&error_abort);
ec46eaa8 JCD	142
5325cc34 MA	143	object_property_set_int(OBJECT(&s->a9mpcore), "num-irq",
5325cc34 MA	144	FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
ec46eaa8	145
668f62ec	146	if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) {
ec46eaa8 JCD	147	return;
	148	}
	149	sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
	150
	151	for (i = 0; i < smp_cpus; i++) {
	152	sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
	153	qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
	154	sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
	155	qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
	156	}
	157
668f62ec	158	if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
ec46eaa8 JCD	159	return;
	160	}
	161	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
	162
668f62ec	163	if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) {
ec46eaa8 JCD	164	return;
	165	}
	166	sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
	167
	168	/* Initialize all UARTs */
	169	for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
	170	static const struct {
	171	hwaddr addr;
	172	unsigned int irq;
	173	} serial_table[FSL_IMX6_NUM_UARTS] = {
	174	{ FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
	175	{ FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
	176	{ FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
	177	{ FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
	178	{ FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
	179	};
	180
fc38a112	181	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
ec46eaa8	182
668f62ec	183	if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
ec46eaa8 JCD	184	return;
	185	}
	186
	187	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	188	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	189	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	190	serial_table[i].irq));
	191	}
	192
	193	s->gpt.ccm = IMX_CCM(&s->ccm);
	194
668f62ec	195	if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) {
ec46eaa8 JCD	196	return;
	197	}
	198
	199	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
	200	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
	201	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	202	FSL_IMX6_GPT_IRQ));
	203
	204	/* Initialize all EPIT timers */
	205	for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
	206	static const struct {
	207	hwaddr addr;
	208	unsigned int irq;
	209	} epit_table[FSL_IMX6_NUM_EPITS] = {
	210	{ FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
	211	{ FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
	212	};
	213
	214	s->epit[i].ccm = IMX_CCM(&s->ccm);
	215
668f62ec	216	if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) {
ec46eaa8 JCD	217	return;
	218	}
	219
	220	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	221	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	222	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	223	epit_table[i].irq));
	224	}
	225
	226	/* Initialize all I2C */
	227	for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
	228	static const struct {
	229	hwaddr addr;
	230	unsigned int irq;
	231	} i2c_table[FSL_IMX6_NUM_I2CS] = {
	232	{ FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
	233	{ FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
	234	{ FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
	235	};
	236
668f62ec	237	if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
ec46eaa8 JCD	238	return;
	239	}
	240
	241	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	242	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	243	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	244	i2c_table[i].irq));
	245	}
	246
	247	/* Initialize all GPIOs */
	248	for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
	249	static const struct {
	250	hwaddr addr;
	251	unsigned int irq_low;
	252	unsigned int irq_high;
	253	} gpio_table[FSL_IMX6_NUM_GPIOS] = {
	254	{
	255	FSL_IMX6_GPIO1_ADDR,
	256	FSL_IMX6_GPIO1_LOW_IRQ,
	257	FSL_IMX6_GPIO1_HIGH_IRQ
	258	},
	259	{
	260	FSL_IMX6_GPIO2_ADDR,
	261	FSL_IMX6_GPIO2_LOW_IRQ,
	262	FSL_IMX6_GPIO2_HIGH_IRQ
	263	},
	264	{
	265	FSL_IMX6_GPIO3_ADDR,
	266	FSL_IMX6_GPIO3_LOW_IRQ,
	267	FSL_IMX6_GPIO3_HIGH_IRQ
	268	},
	269	{
	270	FSL_IMX6_GPIO4_ADDR,
	271	FSL_IMX6_GPIO4_LOW_IRQ,
	272	FSL_IMX6_GPIO4_HIGH_IRQ
	273	},
	274	{
	275	FSL_IMX6_GPIO5_ADDR,
	276	FSL_IMX6_GPIO5_LOW_IRQ,
	277	FSL_IMX6_GPIO5_HIGH_IRQ
	278	},
	279	{
	280	FSL_IMX6_GPIO6_ADDR,
	281	FSL_IMX6_GPIO6_LOW_IRQ,
	282	FSL_IMX6_GPIO6_HIGH_IRQ
	283	},
	284	{
	285	FSL_IMX6_GPIO7_ADDR,
	286	FSL_IMX6_GPIO7_LOW_IRQ,
	287	FSL_IMX6_GPIO7_HIGH_IRQ
	288	},
	289	};
	290
5325cc34	291	object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
ec46eaa8	292	&error_abort);
5325cc34 MA	293	object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
5325cc34 MA	294	true, &error_abort);
668f62ec	295	if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
ec46eaa8 JCD	296	return;
	297	}
	298
	299	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	300	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	301	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	302	gpio_table[i].irq_low));
	303	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
	304	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	305	gpio_table[i].irq_high));
	306	}
	307
	308	/* Initialize all SDHC */
	309	for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
	310	static const struct {
	311	hwaddr addr;
	312	unsigned int irq;
	313	} esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
	314	{ FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
	315	{ FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
	316	{ FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
	317	{ FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
	318	};
	319
7f072603	320	/* UHS-I SDIO3.0 SDR104 1.8V ADMA */
5325cc34	321	object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3,
7cd1c981	322	&error_abort);
5325cc34 MA	323	object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg",
	324	IMX6_ESDHC_CAPABILITIES, &error_abort);
	325	object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor",
	326	SDHCI_VENDOR_IMX, &error_abort);
668f62ec	327	if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) {
ec46eaa8 JCD	328	return;
	329	}
	330	sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
	331	sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
	332	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	333	esdhc_table[i].irq));
	334	}
	335
49cd5578 GR	336	/* USB */
49cd5578 GR	337	for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
db873cc5	338	sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
49cd5578 GR	339	sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
	340	FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
	341	}
	342	for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
	343	static const int FSL_IMX6_USBn_IRQ[] = {
	344	FSL_IMX6_USB_OTG_IRQ,
	345	FSL_IMX6_USB_HOST1_IRQ,
	346	FSL_IMX6_USB_HOST2_IRQ,
	347	FSL_IMX6_USB_HOST3_IRQ,
	348	};
	349
db873cc5	350	sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
49cd5578 GR	351	sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
	352	FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
	353	sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
	354	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	355	FSL_IMX6_USBn_IRQ[i]));
	356	}
	357
ec46eaa8 JCD	358	/* Initialize all ECSPI */
	359	for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
	360	static const struct {
	361	hwaddr addr;
	362	unsigned int irq;
	363	} spi_table[FSL_IMX6_NUM_ECSPIS] = {
	364	{ FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
	365	{ FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
	366	{ FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
	367	{ FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
	368	{ FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
	369	};
	370
	371	/* Initialize the SPI */
668f62ec	372	if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
ec46eaa8 JCD	373	return;
	374	}
	375
	376	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
	377	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	378	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	379	spi_table[i].irq));
	380	}
	381
a9c167a3	382	object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err);
1fdde653	383	qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
668f62ec	384	if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) {
517b5e9a JCD	385	return;
	386	}
	387	sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
	388	sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
	389	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	390	FSL_IMX6_ENET_MAC_IRQ));
	391	sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
	392	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	393	FSL_IMX6_ENET_MAC_1588_IRQ));
	394
bbb02509 VC	395	/*
	396	* SNVS
	397	*/
	398	sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
	399	sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR);
	400
5fecbf0f RK	401	/*
	402	* Watchdog
	403	*/
	404	for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
	405	static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
	406	FSL_IMX6_WDOG1_ADDR,
	407	FSL_IMX6_WDOG2_ADDR,
	408	};
bd8045a7 GR	409	static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
	410	FSL_IMX6_WDOG1_IRQ,
	411	FSL_IMX6_WDOG2_IRQ,
	412	};
5fecbf0f	413
5325cc34 MA	414	object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
5325cc34 MA	415	true, &error_abort);
db873cc5	416	sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
5fecbf0f RK	417
5fecbf0f RK	418	sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
bd8045a7 GR	419	sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
	420	qdev_get_gpio_in(DEVICE(&s->a9mpcore),
	421	FSL_IMX6_WDOGn_IRQ[i]));
5fecbf0f RK	422	}
5fecbf0f RK	423
ec46eaa8	424	/* ROM memory */
32b9523a	425	memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
a7aeb5f7	426	FSL_IMX6_ROM_SIZE, &err);
ec46eaa8 JCD	427	if (err) {
	428	error_propagate(errp, err);
	429	return;
	430	}
	431	memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
	432	&s->rom);
	433
	434	/* CAAM memory */
32b9523a	435	memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
a7aeb5f7	436	FSL_IMX6_CAAM_MEM_SIZE, &err);
ec46eaa8 JCD	437	if (err) {
	438	error_propagate(errp, err);
	439	return;
	440	}
	441	memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
	442	&s->caam);
	443
	444	/* OCRAM memory */
98a99ce0	445	memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
ec46eaa8 JCD	446	&err);
	447	if (err) {
	448	error_propagate(errp, err);
	449	return;
	450	}
	451	memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
	452	&s->ocram);
ec46eaa8 JCD	453
ec46eaa8 JCD	454	/* internal OCRAM (256 KB) is aliased over 1 MB */
32b9523a	455	memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
ec46eaa8 JCD	456	&s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
	457	memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
	458	&s->ocram_alias);
	459	}
	460
a9c167a3 JCD	461	static Property fsl_imx6_properties[] = {
	462	DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0),
	463	DEFINE_PROP_END_OF_LIST(),
	464	};
	465
ec46eaa8 JCD	466	static void fsl_imx6_class_init(ObjectClass oc, void data)
	467	{
	468	DeviceClass *dc = DEVICE_CLASS(oc);
	469
a9c167a3	470	device_class_set_props(dc, fsl_imx6_properties);
ec46eaa8	471	dc->realize = fsl_imx6_realize;
ec46eaa8	472	dc->desc = "i.MX6 SOC";
9bca0edb	473	/* Reason: Uses serial_hd() in the realize() function */
70fbd3c4	474	dc->user_creatable = false;
ec46eaa8 JCD	475	}
	476
	477	static const TypeInfo fsl_imx6_type_info = {
	478	.name = TYPE_FSL_IMX6,
	479	.parent = TYPE_DEVICE,
	480	.instance_size = sizeof(FslIMX6State),
	481	.instance_init = fsl_imx6_init,
	482	.class_init = fsl_imx6_class_init,
	483	};
	484
	485	static void fsl_imx6_register_types(void)
	486	{
	487	type_register_static(&fsl_imx6_type_info);
	488	}
	489
	490	type_init(fsl_imx6_register_types)