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757282ad AS |
1 | /* |
2 | * Copyright (c) 2018, Impinj, Inc. | |
3 | * | |
4 | * i.MX7 SoC definitions | |
5 | * | |
6 | * Author: Andrey Smirnov <andrew.smirnov@gmail.com> | |
7 | * | |
8 | * Based on hw/arm/fsl-imx6.c | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "qapi/error.h" | |
757282ad AS |
23 | #include "hw/arm/fsl-imx7.h" |
24 | #include "hw/misc/unimp.h" | |
25 | #include "sysemu/sysemu.h" | |
26 | #include "qemu/error-report.h" | |
0b8fa32f | 27 | #include "qemu/module.h" |
757282ad AS |
28 | |
29 | #define NAME_SIZE 20 | |
30 | ||
31 | static void fsl_imx7_init(Object *obj) | |
32 | { | |
757282ad AS |
33 | FslIMX7State *s = FSL_IMX7(obj); |
34 | char name[NAME_SIZE]; | |
35 | int i; | |
36 | ||
757282ad | 37 | |
f640a591 | 38 | for (i = 0; i < MIN(smp_cpus, FSL_IMX7_NUM_CPUS); i++) { |
757282ad | 39 | snprintf(name, NAME_SIZE, "cpu%d", i); |
f8bf4b6d TH |
40 | object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), |
41 | ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, | |
42 | NULL); | |
757282ad AS |
43 | } |
44 | ||
45 | /* | |
46 | * A7MPCORE | |
47 | */ | |
f8bf4b6d TH |
48 | sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore), |
49 | TYPE_A15MPCORE_PRIV); | |
757282ad AS |
50 | |
51 | /* | |
52 | * GPIOs 1 to 7 | |
53 | */ | |
54 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | |
757282ad | 55 | snprintf(name, NAME_SIZE, "gpio%d", i); |
f8bf4b6d TH |
56 | sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]), |
57 | TYPE_IMX_GPIO); | |
757282ad AS |
58 | } |
59 | ||
60 | /* | |
61 | * GPT1, 2, 3, 4 | |
62 | */ | |
63 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | |
757282ad | 64 | snprintf(name, NAME_SIZE, "gpt%d", i); |
f8bf4b6d TH |
65 | sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]), |
66 | TYPE_IMX7_GPT); | |
757282ad AS |
67 | } |
68 | ||
69 | /* | |
70 | * CCM | |
71 | */ | |
f8bf4b6d | 72 | sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM); |
757282ad AS |
73 | |
74 | /* | |
75 | * Analog | |
76 | */ | |
f8bf4b6d TH |
77 | sysbus_init_child_obj(obj, "analog", &s->analog, sizeof(s->analog), |
78 | TYPE_IMX7_ANALOG); | |
757282ad AS |
79 | |
80 | /* | |
81 | * GPCv2 | |
82 | */ | |
f8bf4b6d TH |
83 | sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2), |
84 | TYPE_IMX_GPCV2); | |
757282ad AS |
85 | |
86 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | |
757282ad | 87 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
f8bf4b6d TH |
88 | sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), |
89 | TYPE_IMX_SPI); | |
757282ad AS |
90 | } |
91 | ||
92 | ||
93 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | |
757282ad | 94 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); |
f8bf4b6d TH |
95 | sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]), |
96 | TYPE_IMX_I2C); | |
757282ad AS |
97 | } |
98 | ||
99 | /* | |
100 | * UART | |
101 | */ | |
102 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | |
757282ad | 103 | snprintf(name, NAME_SIZE, "uart%d", i); |
f8bf4b6d TH |
104 | sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]), |
105 | TYPE_IMX_SERIAL); | |
757282ad AS |
106 | } |
107 | ||
108 | /* | |
109 | * Ethernet | |
110 | */ | |
111 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { | |
757282ad | 112 | snprintf(name, NAME_SIZE, "eth%d", i); |
f8bf4b6d TH |
113 | sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]), |
114 | TYPE_IMX_ENET); | |
757282ad AS |
115 | } |
116 | ||
117 | /* | |
118 | * SDHCI | |
119 | */ | |
120 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | |
757282ad | 121 | snprintf(name, NAME_SIZE, "usdhc%d", i); |
f8bf4b6d TH |
122 | sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]), |
123 | TYPE_IMX_USDHC); | |
757282ad AS |
124 | } |
125 | ||
126 | /* | |
127 | * SNVS | |
128 | */ | |
f8bf4b6d TH |
129 | sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs), |
130 | TYPE_IMX7_SNVS); | |
757282ad AS |
131 | |
132 | /* | |
133 | * Watchdog | |
134 | */ | |
135 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | |
757282ad | 136 | snprintf(name, NAME_SIZE, "wdt%d", i); |
f8bf4b6d TH |
137 | sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]), |
138 | TYPE_IMX2_WDT); | |
757282ad AS |
139 | } |
140 | ||
141 | /* | |
142 | * GPR | |
143 | */ | |
f8bf4b6d | 144 | sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR); |
757282ad | 145 | |
f8bf4b6d TH |
146 | sysbus_init_child_obj(obj, "pcie", &s->pcie, sizeof(s->pcie), |
147 | TYPE_DESIGNWARE_PCIE_HOST); | |
757282ad AS |
148 | |
149 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | |
757282ad | 150 | snprintf(name, NAME_SIZE, "usb%d", i); |
f8bf4b6d TH |
151 | sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]), |
152 | TYPE_CHIPIDEA); | |
757282ad AS |
153 | } |
154 | } | |
155 | ||
156 | static void fsl_imx7_realize(DeviceState *dev, Error **errp) | |
157 | { | |
158 | FslIMX7State *s = FSL_IMX7(dev); | |
159 | Object *o; | |
160 | int i; | |
161 | qemu_irq irq; | |
162 | char name[NAME_SIZE]; | |
163 | ||
f640a591 TH |
164 | if (smp_cpus > FSL_IMX7_NUM_CPUS) { |
165 | error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", | |
166 | TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus); | |
167 | return; | |
168 | } | |
169 | ||
757282ad AS |
170 | for (i = 0; i < smp_cpus; i++) { |
171 | o = OBJECT(&s->cpu[i]); | |
172 | ||
173 | object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, | |
174 | "psci-conduit", &error_abort); | |
175 | ||
176 | /* On uniprocessor, the CBAR is set to 0 */ | |
177 | if (smp_cpus > 1) { | |
178 | object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR, | |
179 | "reset-cbar", &error_abort); | |
180 | } | |
181 | ||
182 | if (i) { | |
183 | /* Secondary CPUs start in PSCI powered-down state */ | |
184 | object_property_set_bool(o, true, | |
185 | "start-powered-off", &error_abort); | |
186 | } | |
187 | ||
188 | object_property_set_bool(o, true, "realized", &error_abort); | |
189 | } | |
190 | ||
191 | /* | |
192 | * A7MPCORE | |
193 | */ | |
194 | object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", | |
195 | &error_abort); | |
196 | object_property_set_int(OBJECT(&s->a7mpcore), | |
197 | FSL_IMX7_MAX_IRQ + GIC_INTERNAL, | |
198 | "num-irq", &error_abort); | |
199 | ||
200 | object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", | |
201 | &error_abort); | |
202 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); | |
203 | ||
204 | for (i = 0; i < smp_cpus; i++) { | |
205 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | |
206 | DeviceState *d = DEVICE(qemu_get_cpu(i)); | |
207 | ||
208 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
209 | sysbus_connect_irq(sbd, i, irq); | |
210 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
211 | sysbus_connect_irq(sbd, i + smp_cpus, irq); | |
b558e295 PM |
212 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
213 | sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq); | |
214 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); | |
215 | sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq); | |
757282ad AS |
216 | } |
217 | ||
218 | /* | |
219 | * A7MPCORE DAP | |
220 | */ | |
221 | create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, | |
222 | 0x100000); | |
223 | ||
224 | /* | |
225 | * GPT1, 2, 3, 4 | |
226 | */ | |
227 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | |
228 | static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { | |
229 | FSL_IMX7_GPT1_ADDR, | |
230 | FSL_IMX7_GPT2_ADDR, | |
231 | FSL_IMX7_GPT3_ADDR, | |
232 | FSL_IMX7_GPT4_ADDR, | |
233 | }; | |
234 | ||
235 | s->gpt[i].ccm = IMX_CCM(&s->ccm); | |
236 | object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", | |
237 | &error_abort); | |
238 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); | |
239 | } | |
240 | ||
241 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | |
242 | static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { | |
243 | FSL_IMX7_GPIO1_ADDR, | |
244 | FSL_IMX7_GPIO2_ADDR, | |
245 | FSL_IMX7_GPIO3_ADDR, | |
246 | FSL_IMX7_GPIO4_ADDR, | |
247 | FSL_IMX7_GPIO5_ADDR, | |
248 | FSL_IMX7_GPIO6_ADDR, | |
249 | FSL_IMX7_GPIO7_ADDR, | |
250 | }; | |
251 | ||
252 | object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", | |
253 | &error_abort); | |
254 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]); | |
255 | } | |
256 | ||
257 | /* | |
258 | * IOMUXC and IOMUXC_LPSR | |
259 | */ | |
260 | for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { | |
261 | static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { | |
262 | FSL_IMX7_IOMUXC_ADDR, | |
263 | FSL_IMX7_IOMUXC_LPSR_ADDR, | |
264 | }; | |
265 | ||
266 | snprintf(name, NAME_SIZE, "iomuxc%d", i); | |
267 | create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], | |
268 | FSL_IMX7_IOMUXCn_SIZE); | |
269 | } | |
270 | ||
271 | /* | |
272 | * CCM | |
273 | */ | |
274 | object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort); | |
275 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR); | |
276 | ||
277 | /* | |
278 | * Analog | |
279 | */ | |
280 | object_property_set_bool(OBJECT(&s->analog), true, "realized", | |
281 | &error_abort); | |
282 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR); | |
283 | ||
284 | /* | |
285 | * GPCv2 | |
286 | */ | |
287 | object_property_set_bool(OBJECT(&s->gpcv2), true, | |
288 | "realized", &error_abort); | |
289 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); | |
290 | ||
291 | /* Initialize all ECSPI */ | |
292 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | |
293 | static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { | |
294 | FSL_IMX7_ECSPI1_ADDR, | |
295 | FSL_IMX7_ECSPI2_ADDR, | |
296 | FSL_IMX7_ECSPI3_ADDR, | |
297 | FSL_IMX7_ECSPI4_ADDR, | |
298 | }; | |
299 | ||
d82fa734 | 300 | static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = { |
757282ad AS |
301 | FSL_IMX7_ECSPI1_IRQ, |
302 | FSL_IMX7_ECSPI2_IRQ, | |
303 | FSL_IMX7_ECSPI3_IRQ, | |
304 | FSL_IMX7_ECSPI4_IRQ, | |
305 | }; | |
306 | ||
307 | /* Initialize the SPI */ | |
308 | object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | |
309 | &error_abort); | |
310 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
311 | FSL_IMX7_SPIn_ADDR[i]); | |
312 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
313 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
314 | FSL_IMX7_SPIn_IRQ[i])); | |
315 | } | |
316 | ||
317 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | |
318 | static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { | |
319 | FSL_IMX7_I2C1_ADDR, | |
320 | FSL_IMX7_I2C2_ADDR, | |
321 | FSL_IMX7_I2C3_ADDR, | |
322 | FSL_IMX7_I2C4_ADDR, | |
323 | }; | |
324 | ||
d82fa734 | 325 | static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = { |
757282ad AS |
326 | FSL_IMX7_I2C1_IRQ, |
327 | FSL_IMX7_I2C2_IRQ, | |
328 | FSL_IMX7_I2C3_IRQ, | |
329 | FSL_IMX7_I2C4_IRQ, | |
330 | }; | |
331 | ||
332 | object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", | |
333 | &error_abort); | |
334 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); | |
335 | ||
336 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, | |
337 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
338 | FSL_IMX7_I2Cn_IRQ[i])); | |
339 | } | |
340 | ||
341 | /* | |
342 | * UART | |
343 | */ | |
344 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | |
345 | static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { | |
346 | FSL_IMX7_UART1_ADDR, | |
347 | FSL_IMX7_UART2_ADDR, | |
348 | FSL_IMX7_UART3_ADDR, | |
349 | FSL_IMX7_UART4_ADDR, | |
350 | FSL_IMX7_UART5_ADDR, | |
351 | FSL_IMX7_UART6_ADDR, | |
352 | FSL_IMX7_UART7_ADDR, | |
353 | }; | |
354 | ||
355 | static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = { | |
356 | FSL_IMX7_UART1_IRQ, | |
357 | FSL_IMX7_UART2_IRQ, | |
358 | FSL_IMX7_UART3_IRQ, | |
359 | FSL_IMX7_UART4_IRQ, | |
360 | FSL_IMX7_UART5_IRQ, | |
361 | FSL_IMX7_UART6_IRQ, | |
362 | FSL_IMX7_UART7_IRQ, | |
363 | }; | |
364 | ||
365 | ||
fc38a112 | 366 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
757282ad AS |
367 | |
368 | object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", | |
369 | &error_abort); | |
370 | ||
371 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); | |
372 | ||
373 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); | |
374 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); | |
375 | } | |
376 | ||
377 | /* | |
378 | * Ethernet | |
379 | */ | |
380 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { | |
381 | static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = { | |
382 | FSL_IMX7_ENET1_ADDR, | |
383 | FSL_IMX7_ENET2_ADDR, | |
384 | }; | |
385 | ||
386 | object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS, | |
387 | "tx-ring-num", &error_abort); | |
388 | qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); | |
389 | object_property_set_bool(OBJECT(&s->eth[i]), true, "realized", | |
390 | &error_abort); | |
391 | ||
392 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); | |
393 | ||
394 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); | |
395 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); | |
396 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); | |
397 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); | |
398 | } | |
399 | ||
400 | /* | |
401 | * USDHC | |
402 | */ | |
403 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | |
404 | static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { | |
405 | FSL_IMX7_USDHC1_ADDR, | |
406 | FSL_IMX7_USDHC2_ADDR, | |
407 | FSL_IMX7_USDHC3_ADDR, | |
408 | }; | |
409 | ||
410 | static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = { | |
411 | FSL_IMX7_USDHC1_IRQ, | |
412 | FSL_IMX7_USDHC2_IRQ, | |
413 | FSL_IMX7_USDHC3_IRQ, | |
414 | }; | |
415 | ||
416 | object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", | |
417 | &error_abort); | |
418 | ||
419 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, | |
420 | FSL_IMX7_USDHCn_ADDR[i]); | |
421 | ||
422 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); | |
423 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); | |
424 | } | |
425 | ||
426 | /* | |
427 | * SNVS | |
428 | */ | |
429 | object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort); | |
430 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); | |
431 | ||
432 | /* | |
433 | * SRC | |
434 | */ | |
b4cf3e6f | 435 | create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); |
757282ad AS |
436 | |
437 | /* | |
438 | * Watchdog | |
439 | */ | |
440 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | |
441 | static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { | |
442 | FSL_IMX7_WDOG1_ADDR, | |
443 | FSL_IMX7_WDOG2_ADDR, | |
444 | FSL_IMX7_WDOG3_ADDR, | |
445 | FSL_IMX7_WDOG4_ADDR, | |
446 | }; | |
447 | ||
448 | object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", | |
449 | &error_abort); | |
450 | ||
451 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); | |
452 | } | |
453 | ||
454 | /* | |
455 | * SDMA | |
456 | */ | |
457 | create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE); | |
458 | ||
459 | ||
460 | object_property_set_bool(OBJECT(&s->gpr), true, "realized", | |
461 | &error_abort); | |
462 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); | |
463 | ||
464 | object_property_set_bool(OBJECT(&s->pcie), true, | |
465 | "realized", &error_abort); | |
466 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); | |
467 | ||
468 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); | |
469 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); | |
470 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); | |
471 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); | |
472 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); | |
473 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); | |
474 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); | |
475 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); | |
476 | ||
477 | ||
478 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | |
479 | static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { | |
480 | FSL_IMX7_USBMISC1_ADDR, | |
481 | FSL_IMX7_USBMISC2_ADDR, | |
482 | FSL_IMX7_USBMISC3_ADDR, | |
483 | }; | |
484 | ||
485 | static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = { | |
486 | FSL_IMX7_USB1_ADDR, | |
487 | FSL_IMX7_USB2_ADDR, | |
488 | FSL_IMX7_USB3_ADDR, | |
489 | }; | |
490 | ||
d82fa734 | 491 | static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = { |
757282ad AS |
492 | FSL_IMX7_USB1_IRQ, |
493 | FSL_IMX7_USB2_IRQ, | |
494 | FSL_IMX7_USB3_IRQ, | |
495 | }; | |
496 | ||
497 | object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", | |
498 | &error_abort); | |
499 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, | |
500 | FSL_IMX7_USBn_ADDR[i]); | |
501 | ||
502 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); | |
503 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); | |
504 | ||
505 | snprintf(name, NAME_SIZE, "usbmisc%d", i); | |
506 | create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i], | |
507 | FSL_IMX7_USBMISCn_SIZE); | |
508 | } | |
509 | ||
510 | /* | |
511 | * ADCs | |
512 | */ | |
513 | for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) { | |
514 | static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = { | |
515 | FSL_IMX7_ADC1_ADDR, | |
516 | FSL_IMX7_ADC2_ADDR, | |
517 | }; | |
518 | ||
519 | snprintf(name, NAME_SIZE, "adc%d", i); | |
520 | create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i], | |
521 | FSL_IMX7_ADCn_SIZE); | |
522 | } | |
523 | ||
524 | /* | |
525 | * LCD | |
526 | */ | |
527 | create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR, | |
528 | FSL_IMX7_LCDIF_SIZE); | |
529 | } | |
530 | ||
531 | static void fsl_imx7_class_init(ObjectClass *oc, void *data) | |
532 | { | |
533 | DeviceClass *dc = DEVICE_CLASS(oc); | |
534 | ||
535 | dc->realize = fsl_imx7_realize; | |
536 | ||
537 | /* Reason: Uses serial_hds and nd_table in realize() directly */ | |
538 | dc->user_creatable = false; | |
539 | dc->desc = "i.MX7 SOC"; | |
540 | } | |
541 | ||
542 | static const TypeInfo fsl_imx7_type_info = { | |
543 | .name = TYPE_FSL_IMX7, | |
544 | .parent = TYPE_DEVICE, | |
545 | .instance_size = sizeof(FslIMX7State), | |
546 | .instance_init = fsl_imx7_init, | |
547 | .class_init = fsl_imx7_class_init, | |
548 | }; | |
549 | ||
550 | static void fsl_imx7_register_types(void) | |
551 | { | |
552 | type_register_static(&fsl_imx7_type_info); | |
553 | } | |
554 | type_init(fsl_imx7_register_types) |